Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

6.2.1. Avalon Streaming Receive Interface

Figure 45. Receive Operation—MAC With Internal FIFO Buffers


Figure 46. Receive Operation—MAC Without Internal FIFO Buffers


Figure 47. Invalid Length Error During Receive Operation—MAC With Internal FIFO Buffer


Figure 48. Invalid Length Error During Receive Operation—MAC Without Internal FIFO Buffers