Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

1.6. Performance and Resource Utilization

The estimated resource utilization and performance of the Triple-Speed Ethernet Intel® FPGA IP are obtained by compiling the IP using the Quartus® Prime software targeting a given device. The fMAX for this configuration is more than 125 MHz.
Table 5.  Resource Utilization for Agilex™ 5 Devices
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M20K)

10/100/1000 Mbps Ethernet MAC

MII/GMII.

All MAC options enabled.

Full-duplex.

2048x32 3794 5649 20

MII/GMII.

All MAC options enabled.

Full-duplex.

2048x8 3611 5427 15

MII/GMII.

All MAC options enabled.

Half-duplex.

2048x32 4058 5794 21

MII/GMII.

All MAC options enabled.

Half-duplex.

2048x8 3804 5606 16

RGMII.

All MAC options enabled.

Full-duplex.

2048x32 3758 5583 20

RGMII.

All MAC options enabled.

Full-duplex.

2048x8 3544 5356 15

RGMII.

All MAC options enabled.

Half-duplex.

2048x32 4076 5862 21

RGMII.

All MAC options enabled.

Half-duplex.

2048x8 3794 5622 16
10/100 Mbps Small MAC

MII.

Full-duplex only.

2048x32 1177 2076 10

MII.

Half-duplex only.

2048x32 1453 2166 11
1000 Mbps Small MAC

GMII.

Full-duplex only.

2048x32 1113 1939 10

RGMII.

Full-duplex only.

2048x32 1117 1919 10
1000BASE-X/SGMII PCS

SGMII bridge enabled.

N/A 887 1449 0

1000BASE-X.

N/A 667 1044 0
1000BASE-X/SGMII 2XTBI PCS only

SGMII bridge enabled.

N/A 1344 2196 2

1000BASE-X.

N/A 1275 2251 2
10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS

All MAC options enabled.

SGMII bridge enabled.

PMA block (GTS).

2048x32 6175 7922 24