Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

6.1.6.6. SGMII Status Signals

The SGMII status signals provide status information to the PCS block. When the PCS is instantiated standalone, these signals are inputs to the MAC and serve as interface control signals for that block.
Table 71.  SGMII Status Signals
Name I/O Description
set_1000 O Gigabit mode enabled. In 1000BASE-X, this signal is always set to 1. In SGMII, this signal is set to 1 if the below is met:
  • SGMII_SPEED bit is set to 10.
set_100 O 100 -Mbps mode enabled. In 1000BASE-X, this signal is always set to 0. In SGMII, this signal is set to 1 if the below is met:
  • SGMII_SPEED bit is set to 01.
set_10 O 10 -Mbps mode enabled. In 1000BASE-X, this signal is always set to 0. In SGMII, this signal is set to 1 if the below is met:
  • SGMII_SPEED bit is set to 00.
hd_ena O Half-duplex mode enabled. In 1000BASE-X, this signal is always set to 0. In SGMII, this signal is set to 1 the below is met:
  • SGMII_DUPLEX bit is set to 1.