Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

6.1.7.1. Clock Enablers

Table 73.  Clock Enablers
Note: The clock enabler signals are present only in SGMII mode.
Name I/O Description
rx_clkena O Receive clock enabler for SGMII 10M/100M operating speeds.
tx_clkena O Transmit clock enabler for SGMII 10M/100M operating speeds.