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1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
11. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters
4.1.1. MAC Architecture
4.1.2. MAC Interfaces
4.1.3. MAC Transmit Datapath
4.1.4. MAC Receive Datapath
4.1.5. MAC Transmit and Receive Latencies
4.1.6. FIFO Buffer Thresholds
4.1.7. Congestion and Flow Control
4.1.8. Magic Packets
4.1.9. MAC Local Loopback
4.1.10. MAC Reset
4.1.11. PHY Management (MDIO)
4.1.12. Connecting MAC to External PHYs
6.1.1. 10/100/1000 Ethernet MAC Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals
6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.6. 1000BASE-X/SGMII PCS Signals
6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.1.1. Clock and Reset Signals
6.1.1.2. Clock Enabler Signals
6.1.1.3. MAC Control Interface Signals
6.1.1.4. MAC Status Signals
6.1.1.5. MAC Receive Interface Signals
6.1.1.6. MAC Transmit Interface Signals
6.1.1.7. Pause and Magic Packet Signals
6.1.1.8. MII/GMII/RGMII Signals
6.1.1.9. PHY Management Signals
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7.1. Exposed Ports in the New User Interface
In the new user interface in Platform Designer, for a design that has a MAC function, you have to manually connect the exposed ports or terminate them.
In MAC variation with internal FIFO buffers, the ready latency is two in both standalone and Platform Designer flow. The Platform Designer system inserts a timing adapter to change the ready latency to zero.
Port Name | I/O | Width | Recommended Termination Value |
---|---|---|---|
xon_gen | I | 1 | 1'b0 |
xoff_gen | I | 1 | 1'b0 |
magic_wakeup | O | 1 | Left open |
magic_sleep_n | I | 1 | 1'b1 |
ff_tx_crc_fwd | I | 1 | 1'b0 |
ff_tx_septy | O | 1 | Left open |
tx_ff_uflow | O | 1 | Left open |
ff_tx_a_full | O | 1 | Left open |
ff_tx_a_empty | O | 1 | Left open |
rx_err_stat | O | 18 | Left open |
rx_frm_type | O | 4 | Left open |
ff_rx_dsav | O | 1 | Left open |
ff_rx_a_full | O | 1 | Left open |
ff_rx_a_empty | O | 1 | Left open |
The following table lists the following ports that are exposed in the Platform Designer system for a design that has MAC variation without internal FIFO buffers.
Port Name | I/O | Width | Recommended Termination Value |
---|---|---|---|
xon_gen_<n> | I | 1 | 1'b0 |
xoff_gen_<n> | I | 1 | 1'b0 |
magic_wakeup_<n> | O | 1 | Left open |
magic_sleep_n_<n> | I | 1 | 1'b1 |
ff_tx_crc_fwd_<n> | I | 1 | 1'b0 |