Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

6.1.1.2. Clock Enabler Signals

Table 40.  Clock Enabler Signals
Name I/O Description
tx_clkena I Clock enable from the PHY IP. When you turn on the Use clock enable for MAC parameter, this signal is used together with tx_clk and rx_clk to generate 125 MHz, 25 MHz, and 2.5 MHz clocks. 9
rx_clkena I Clock enable from the PHY IP. When you turn on the Use clock enable for MAC parameter, this signal is used together with tx_clk and rx_clk to generate 125 MHz, 25 MHz, and 2.5 MHz clocks. 10
9

For configurations without internal FIFO, this signal is called tx_clkena_<n>.

10

For configurations without internal FIFO, this signal is called rx_clkena_<n>.