Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

6.1.1.1. Clock and Reset Signals

Data transfers on the MAC Ethernet-side interface are synchronous to the receive and transmit clocks.
Table 38.  GMII/RGMII/MII Clock Signals
Name I/O Description
tx_clk

(In Platform Designer: pcs_mac_tx_clock_connection)

I GMII/MII transmit clock. Provides the timing reference for all GMII / MII transmit signals. The values of gm_tx_d[7:0], gm_tx_en, gm_tx_err, and of m_tx_d[3:0], m_tx_en, m_tx_err are valid on the rising edge of tx_clk.

In RGMII mode, this clock is the reference clock for the transmit interface. The frequencies are 2.5/25/125 MHz for speed modes 10/100/1000M respectively.

rx_clk

(In Platform Designer: pcs_mac_rx_clock_connection)

I GMII/MII receive clock. Provides the timing reference for all rx related signals. The values of gm_rx_d[7:0], gm_rx_dv, gm_rx_err, and of m_rx_d[3:0], m_rx_en, m_rx_err are valid on the rising edge of rx_clk.

In RGMII mode, this clock is not used.

Table 39.   Reset Signal
Name I/O Description
reset I Assert this signal to reset all logic in the MAC and PCS data and control interface. The signal must be asserted for at least three clock cycles.