Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

1.5. High-Level Block Diagrams

High-level block diagrams of different variations of the Triple-Speed Ethernet Intel® FPGA IP.
Figure 1. 10/100/1000 Mbps Ethernet MAC


Figure 2. Multiport MAC


Figure 3. 10/100/1000 Mbps Ethernet MAC and 1000BASE-X/SGMII PCS
Figure 4. 10/100/1000 Mbps Ethernet MAC and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS)
Figure 5. 1000BASE-X/SGMII PCS
Figure 6. 1000BASE-X/SGMII 2XTBI PCS