Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

6.1.4.2. GTS Transceiver Direct PHY Signals

Table 61.  GTS Transceiver Direct PHY Signals
Name I/O Description
rx_serial_data I Positive signal for the receiver serial data.
rx_serial_data_n I Negative signal for the receiver serial data.
rx_is_lockedtodata O When asserted, this signal indicates that the CDR PLL is locked to the incoming rx_serial data.
tx_serial_data O Positive signal for the transmitter serial data.
tx_serial_data_n O Negative signal for the transmitter serial data.
tx_ready O Status signal from GTS Native PHY. It is asserted when Native PHY TX datapath resets sequencing is complete.
rx_ready O Status signal from GTS Native PHY. It is asserted when Native PHY RX datapath resets sequencing is complete.
tx_pll_refclk_p I Positive signal for the 156.25 MHz reference clock input to Direct PHY.
rx_cdr_refclk_p I 156.25 MHz reference clock for CDR PLL.
phyip_reset_tx_in I TX reset input for TX transceivers and TX datapath of Direct PHY.
phyip_reset_rx_in I RX reset input for RX transceivers and RX datapath of Direct PHY.
phyip_reset_tx_ack_o O TX fully in reset indicator.
phyip_reset_rx_ack_o O RX fully in reset indicator.
system_pll_clk I 322.2656 MHz or 644.53125 MHz system PLL clock.
system_pll_lock I System PLL lock signal for system clock IP.
rx_is_lockedtoref O CDR lock status signal.
  • 1'b1: CDR is frequency locked to reference clock within the PPM threshold.
  • 1'b0: CDR is not frequency locked within the PPM threshold. Applicable to PMA only. When rx_lockedtodata stays high, the rx_is_lockedtoref signal status is insignificant.
tx_pll_locked O TX PLL locked to reference clock within the PPM threshold status signal.
  • 1'b1: Locked
  • 1'b0: Not locked