Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

6.1.7.2. PCS Reset Signals

Table 74.   Reset Signals
Name I/O Description
reset_rx_clk I Active-high reset signal for PCS receive clock domain. Assert this signal to reset the logic synchronized by rx_clk_125 and rx_clk_62_5.
reset_tx_clk I Active-high reset signal for PCS transmit clock domain. Assert this signal to reset the logic synchronized by tx_clk_125 and tx_clk_62_5.