Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

9.6.2. Simulate the IP

You can simulate your IP variation with the functional simulation model and the testbench or design example generated with your IP. The functional simulation model and testbench files are generated in a project subdirectory. This directory may also include scripts to compile and run the testbench.

For a complete list of models or libraries required to simulate your IP, refer to the scripts provided with the testbench in Simulation Model Files.

Generate the simulation model as shown in Generate the Simulation Model before simulating the testbench design.

To use the ModelSim® simulation software to simulate the testbench design, follow these steps:

  1. For Verilog testbench design:
    1. Browse to the following project directory: <variation name>_testbench/testbench_verilog/<variation name>
    2. Run the following command to set up the required libraries, to compile the generated IP Functional simulation model, and to exercise the simulation model with the provided testbench:

      do run_<variation_name>_tb.tcl

  2. For VHDL testbench design:
    1. Browse to the following project directory: <variation name>_testbench/testbench_vhdl/<variation name>_testbench
    2. Run the following command to set up the required libraries, to compile the generated IP Functional simulation model, and to exercise the simulation model with the provided testbench:

      do run_<variation_name>_tb.tcl

For more information about simulating Altera IPs, refer to the Simulating Intel FPGA Designs section in the respective Quartus® Prime Pro Edition User Guide: Third-party Simulation and Quartus® Prime Standard Edition User Guide: Third-party Simulation.

Note: Use the simulation models only for simulation and not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.