Visible to Intel only — GUID: bhc1410932188272
Ixiasoft
Visible to Intel only — GUID: bhc1410932188272
Ixiasoft
9.6.2. Simulate the IP
For a complete list of models or libraries required to simulate your IP, refer to the scripts provided with the testbench in Simulation Model Files.
To use the ModelSim® simulation software to simulate the testbench design, follow these steps:
- For Verilog testbench design:
- Browse to the following project directory: <variation name>_testbench/testbench_verilog/<variation name>
- Run the following command to set up the required libraries, to compile the generated IP Functional simulation model, and to exercise the simulation model with the provided testbench:
do run_<variation_name>_tb.tcl
- For VHDL testbench design:
- Browse to the following project directory: <variation name>_testbench/testbench_vhdl/<variation name>_testbench
- Run the following command to set up the required libraries, to compile the generated IP Functional simulation model, and to exercise the simulation model with the provided testbench:
do run_<variation_name>_tb.tcl
For more information about simulating Altera IPs, refer to the Simulating Intel FPGA Designs section in the respective Quartus® Prime Pro Edition User Guide: Third-party Simulation and Quartus® Prime Standard Edition User Guide: Third-party Simulation.