Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

4.2.8. Ten-bit Interface

In PCS variations without embedded PMA, the PCS function implements a TBI to an external SERDES.

On transmit, the SERDES must serialize tbi_tx_d[0], the least significant bit of the TBI output bus first and tbi_tx_d[9], the most significant bit of the TBI output bus last to ensure the remote node receives the data correctly, as illustrated in the following figure.

Figure 30. SERDES Serialization Overview


On receive, the SERDES must serialize the TBI least significant bit first and the TBI most significant bit last, as illustrated in the following figure.

Figure 31. SERDES De-Serialization Overview