Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals

Figure 40. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals
Note: The DATAWIDTH value depends on the FIFO width that you select in the parameter editor. Options available are 8 and 32 bits.
Table 59.  References
Interface Signal Section
Clock and reset signals Clock and Reset Signals
MAC/PCS control interface signals MAC Control Interface Signals
MAC receive interface signals MAC Receive Interface Signals
MAC transmit interface signals MAC Transmit Interface Signals
Pause and magic packet signals Pause and Magic Packet Signals
Status LED signals Status LED Control Signals