Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

6.1.4.3. GTS Reset Sequencer Signals

Table 62.  GTS Reset Sequencer Signals
Name I/O Description
o_src_rs_req O Request to GTS Reset Sequencer from Triple-Speed Ethernet IP.
i_src_rs_grant I Grant from GTS Reset Sequencer to Triple-Speed Ethernet IP.
i_pma_cu_clk I To be connected to GTS Reset Sequencer. Runs at 250 MHz frequency.