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1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
11. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters
4.1.1. MAC Architecture
4.1.2. MAC Interfaces
4.1.3. MAC Transmit Datapath
4.1.4. MAC Receive Datapath
4.1.5. MAC Transmit and Receive Latencies
4.1.6. FIFO Buffer Thresholds
4.1.7. Congestion and Flow Control
4.1.8. Magic Packets
4.1.9. MAC Local Loopback
4.1.10. MAC Reset
4.1.11. PHY Management (MDIO)
4.1.12. Connecting MAC to External PHYs
6.1.1. 10/100/1000 Ethernet MAC Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals
6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.6. 1000BASE-X/SGMII PCS Signals
6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.1.1. Clock and Reset Signals
6.1.1.2. Clock Enabler Signals
6.1.1.3. MAC Control Interface Signals
6.1.1.4. MAC Status Signals
6.1.1.5. MAC Receive Interface Signals
6.1.1.6. MAC Transmit Interface Signals
6.1.1.7. Pause and Magic Packet Signals
6.1.1.8. MII/GMII/RGMII Signals
6.1.1.9. PHY Management Signals
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A.3.1. Pause Frame Generation
When you turn on the Enable full-duplex flow control option, pause frame generation is triggered by the following events:
- RX FIFO fill level hits the rx_section_empty threshold.
- XOFF register write.
- XON register write.
- XOFF I/O pin (xoff_gen) assertion.
- XON I/O pin (xon_gen) assertion.
If the RX FIFO buffer is almost full, the MAC function triggers the pause frame generation to the remote Ethernet device.
If the local Ethernet device needs to generate pause frame via XOFF or XON register write or I/O pin assertion, it is recommended to set the rx_section_empty register to a larger value to avoid non-deterministic result.
The following table summarizes the pause frame generation based on the above events.
Register Write or I/O Pin Assertion (1) | Description | |
---|---|---|
XOFF_GEN | XON_GEN | |
1 | 0 | If the XOFF_GEN bit is set to 1, the XOFF pause frames are continuously generated and sent to the MII/GMII TX interface until the XOFF_GEN bit is cleared. |
0 | 1 | If the XON_GEN bit is set to 1, the XON pause frames are continuously generated and sent to the MII/GMII TX interface until the XON_GEN bit is cleared. |
1 | 1 | This event is not recommended as it produces non-deterministic result. |
Note to Pause Frame Generation :
|