Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

4.2.4. Transmit and Receive Latencies

Altera uses the following definitions for the transmit and receive latencies for the PCS function with an embedded PMA:
  • Transmit latency is the time the PCS function takes to transmit the first bit on the PMA-PCS interface after the bit was first available on the MAC side interface (MII/GMII).
  • Receive latency is the time the PCS function takes to present the first bit on the MAC side interface (MII/GMII) after the bit was received on the PMA-PCS interface.
Table 23.  PCS Transmit and Receive Latency
PCS Configuration Latency (ns)
Transmit Receive
Agilex™ 5
10 Mbps SGMII 2XTBI PCS 6876 8454
100 Mbps SGMII 2XTBI PCS 836 1054
1000 Mbps SGMII 2XTBI PCS 316 438
1000BASE-X 2XTBI PCS without enabling SGMII 324 438
1000 Mbps SGMII 2XTBI PCS with GTS 316 419