Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813669
Date 7/08/2024
Public
Document Table of Contents

4.1.5. MAC Transmit and Receive Latencies

Altera uses the following definitions for the transmit and receive latencies:
  • Transmit latency is the number of clock cycles the MAC function takes to transmit the first bit on the network-side interface (MII/GMII/RGMII) after the bit was first available on the Avalon® streaming interface.
  • Receive latency is the number of clock cycles the MAC function takes to present the first bit on the Avalon® streaming interface after the bit was received on the network-side interface (MII/GMII/RGMII).
Table 18.  Transmit and Receive Nominal LatencyThe transmit and receive nominal latencies in various modes. The FIFO buffer thresholds are set to the typical values specified in this user guide when deriving the latencies. Under MAC Options tab, only the following options are selected when deriving the latencies shown in the table below: Enable MAC 10/100 half duplex support, Include statistics counters and Enable magic packet detection .
MAC Configuration Latency (Clock Cycles) 3 4
Transmit Receive
MAC with Internal FIFO Buffers 5
GMII in gigabit and cut-through mode 30 112
MII in 100M and cut-through mode 20 213
MII in 10M and cut-through mode 17 211
RGMII in gigabit and cut-through mode 35 112
RGMII in 10 Mbps and cut-through mode 30 207
RGMII in 100 Mbps and cut-through mode 26 205
MAC without Internal FIFO Buffers 6
GMII 15 32
MII 24 62
RGMII in gigabit mode 16 32
RGMII in 100 Mbps 17 78
RGMII in 10 Mbps 18 78
3 The clocks in all domains are running at the same frequency.
4 The numbers in this table are from simulation.
5 The data width is set to 32 bits
6 The data width is set to 8 bits.