Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813669
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Register Space 6. Interface Signals 7. Design Considerations 8. Timing Constraints 9. Testbench 10. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 11. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs A. Ethernet Frame Format B. Simulation Parameters
1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices x
1.1. Release Information 1.2. Device Family Support 1.3. Features 1.4. 10/100/1000 Ethernet MAC Versus Small MAC 1.5. High-Level Block Diagrams 1.6. Performance and Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. IP Core Generation Output 2.5. Simulating Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.4. IP Core Generation Output x
2.4.1. Design Constraint File
3. Parameter Settings x
3.1. Core Configuration 3.2. Ethernet MAC Options 3.3. FIFO Options 3.4. PCS/Transceiver Options 3.5. Analog Parameter Settings
4. Functional Description x
4.1. 10/100/1000 Ethernet MAC 4.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA (GTS)
4.1. 10/100/1000 Ethernet MAC x
4.1.1. MAC Architecture 4.1.2. MAC Interfaces 4.1.3. MAC Transmit Datapath 4.1.4. MAC Receive Datapath 4.1.5. MAC Transmit and Receive Latencies 4.1.6. FIFO Buffer Thresholds 4.1.7. Congestion and Flow Control 4.1.8. Magic Packets 4.1.9. MAC Local Loopback 4.1.10. MAC Reset 4.1.11. PHY Management (MDIO) 4.1.12. Connecting MAC to External PHYs
4.1.3. MAC Transmit Datapath x
4.1.3.1. IP Payload Re-alignment 4.1.3.2. Address Insertion 4.1.3.3. Frame Payload Padding 4.1.3.4. CRC-32 Generation 4.1.3.5. Interpacket Gap Insertion 4.1.3.6. Collision Detection in Half-Duplex Mode
4.1.4. MAC Receive Datapath x
4.1.4.1. Preamble Processing 4.1.4.2. Collision Detection in Half-Duplex Mode 4.1.4.3. Address Checking 4.1.4.4. Frame Type Validation 4.1.4.5. Payload Pad Removal 4.1.4.6. CRC Checking 4.1.4.7. Length Checking 4.1.4.8. Frame Writing 4.1.4.9. IP Payload Alignment
4.1.4.3. Address Checking x
4.1.4.3.1. Unicast Address Checking 4.1.4.3.2. Multicast Address Resolution
4.1.6. FIFO Buffer Thresholds x
4.1.6.1. Receive Thresholds 4.1.6.2. Transmit Thresholds 4.1.6.3. Transmit FIFO Buffer Underflow
4.1.7. Congestion and Flow Control x
4.1.7.1. Remote Device Congestion 4.1.7.2. Receive FIFO Buffer and Local Device Congestion
4.1.8. Magic Packets x
4.1.8.1. Sleep Mode 4.1.8.2. Magic Packet Detection
4.1.11. PHY Management (MDIO) x
4.1.11.1. MDIO Connection 4.1.11.2. MDIO Frame Format
4.1.12. Connecting MAC to External PHYs x
4.1.12.1. Gigabit Ethernet 4.1.12.2. Programmable 10/100 Ethernet 4.1.12.3. Programmable 10/100/1000 Ethernet Operation
4.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA (GTS) x
4.2.1. 1000BASE-X/SGMII PCS Architecture 4.2.2. Transmit Operation 4.2.3. Receive Operation 4.2.4. Transmit and Receive Latencies 4.2.5. GMII Converter 4.2.6. SGMII Converter 4.2.7. Auto-Negotiation 4.2.8. Ten-bit Interface 4.2.9. 1000BASE-X/SGMII PCS Reset
4.2.2. Transmit Operation x
4.2.2.1. Frame Encapsulation 4.2.2.2. 8b/10b Encoding
4.2.3. Receive Operation x
4.2.3.1. Comma Detection 4.2.3.2. 8b/10b Decoding 4.2.3.3. Frame De-encapsulation 4.2.3.4. Synchronization 4.2.3.5. Carrier Sense 4.2.3.6. Collision Detection
4.2.6. SGMII Converter x
4.2.6.1. Transmit 4.2.6.2. Receive
4.2.7. Auto-Negotiation x
4.2.7.1. 1000BASE-X Auto-Negotiation 4.2.7.2. SGMII Auto-Negotiation
5. Configuration Register Space x
5.1. MAC Configuration Register Space 5.2. PCS Configuration Register Space 5.3. Register Initialization
5.1. MAC Configuration Register Space x
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) 5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38) 5.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B) 5.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7)
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) x
5.1.1.1. Command_Config Register (Dword Offset 0x02)
5.2. PCS Configuration Register Space x
5.2.1. Control Register (Word Offset 0x00) 5.2.2. Status Register (Word Offset 0x01) 5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) 5.2.4. An_Expansion Register (Word Offset 0x06) 5.2.5. If_Mode Register (Word Offset 0x14)
5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) x
5.2.3.1. 1000BASE-X 5.2.3.2. SGMII MAC Mode Auto Negotiation 5.2.3.3. SGMII PHY Mode Auto Negotiation
5.3. Register Initialization x
5.3.1. Triple-Speed Ethernet System with MII/GMII or RGMII 5.3.2. Triple-Speed Ethernet System with SGMII 5.3.3. Triple-Speed Ethernet System with 1000BASE-X Interface
6. Interface Signals x
6.1. Interface Signals 6.2. Timing
6.1. Interface Signals x
6.1.1. 10/100/1000 Ethernet MAC Signals 6.1.2. 10/100/1000 Multiport Ethernet MAC Signals 6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals 6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals 6.1.6. 1000BASE-X/SGMII PCS Signals 6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.1. 10/100/1000 Ethernet MAC Signals x
6.1.1.1. Clock and Reset Signals 6.1.1.2. Clock Enabler Signals 6.1.1.3. MAC Control Interface Signals 6.1.1.4. MAC Status Signals 6.1.1.5. MAC Receive Interface Signals 6.1.1.6. MAC Transmit Interface Signals 6.1.1.7. Pause and Magic Packet Signals 6.1.1.8. MII/GMII/RGMII Signals 6.1.1.9. PHY Management Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals x
6.1.2.1. Multiport MAC Clock and Reset Signals 6.1.2.2. Multiport MAC Receive Interface Signals 6.1.2.3. Multiport MAC Transmit Interface Signals 6.1.2.4. Multiport MAC Packet Classification Signals 6.1.2.5. Multiport MAC FIFO Status Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals x
6.1.3.1. TBI Interface Signals 6.1.3.2. Status LED Control Signals 6.1.3.3. SERDES Control Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals x
6.1.4.1. GMII Clock Signals 6.1.4.2. GTS Transceiver Direct PHY Signals 6.1.4.3. GTS Reset Sequencer Signals 6.1.4.4. PMA Reconfiguration Interface Signals
6.1.6. 1000BASE-X/SGMII PCS Signals x
6.1.6.1. PCS Control Interface Signals 6.1.6.2. PCS Reset Signals 6.1.6.3. MII/GMII Clocks and Clock Enablers 6.1.6.4. GMII 6.1.6.5. MII 6.1.6.6. SGMII Status Signals
6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals x
6.1.7.1. Clock Enablers 6.1.7.2. PCS Reset Signals 6.1.7.3. TBI Interface Signals
6.2. Timing x
6.2.1. Avalon Streaming Receive Interface 6.2.2. Avalon Streaming Transmit Interface 6.2.3. GMII Transmit 6.2.4. GMII Receive 6.2.5. RGMII Transmit 6.2.6. RGMII Receive 6.2.7. MII Transmit 6.2.8. MII Receive
7. Design Considerations x
7.1. Exposed Ports in the New User Interface 7.2. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA (GTS)
8. Timing Constraints x
8.1. Creating Clock Constraints 8.2. Recommended Clock Frequency
9. Testbench x
9.1. Triple-Speed Ethernet Testbench Architecture 9.2. Testbench Components 9.3. Testbench Verification 9.4. Testbench Configuration 9.5. Test Flow 9.6. Simulation Model
9.6. Simulation Model x
9.6.1. Generate the Simulation Model 9.6.2. Simulate the IP 9.6.3. Simulation Model Files
A. Ethernet Frame Format x
A.1. Basic Frame Format A.2. VLAN and Stacked VLAN Frame Format A.3. Pause Frame Format
A.3. Pause Frame Format x
A.3.1. Pause Frame Generation
B. Simulation Parameters x
B.1. Functionality Configuration Parameters B.2. Test Configuration Parameters
1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
11. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters

5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38)

The following table describes the read-only registers that collect the statistics on the transmit and receive datapaths. A hardware reset clears these registers; a software reset also clears these registers except aMacID. The statistics counters roll up when the counter is full.

The register description uses the following definitions:

  • Good frame—error-free frames with valid frame length.
  • Error frame—frames that contain errors or whose length is invalid.
  • Invalid frame—frames that are not addressed to the MAC function. The MAC function drops this frame.
Table 27.  Statistics Counters
Dword

Offset

Name R/W Description
0x18 – 0x19 aMacID RO The MAC address. This register is wired to the primary MAC address in the mac_0 and mac_1 registers.
0x1A aFramesTransmittedOK RO The number of frames that are successfully transmitted including the pause frames.
0x1B aFramesReceivedOK RO The number of frames that are successfully received including the pause frames.
0x1C aFrameCheckSequenceErrors RO The number of receive frames with CRC error.
0x1D aAlignmentErrors RO The number of receive frames with alignment error.
0x1E aOctetsTransmittedOK RO The number of data and padding octets that are successfully transmitted.

This register contains the lower 32 bits of the aOctetsTransmittedOK counter. The upper 32 bits of this statistics counter reside at the dword offset 0x0F.

0x1F aOctetsReceivedOK RO The number of data and padding octets that are successfully received, including pause frames.

The lower 32 bits of the aOctetsReceivedOK counter. The upper 32 bits of this statistics counter reside at the dword offset 0x3D.

0x20 aTxPAUSEMACCtrlFrames RO The number of pause frames transmitted.
0x21 aRxPAUSEMACCtrlFrames RO The number received pause frames received.
0x22 ifInErrors RO
The number of errored frames received with one of the following errors:
  • When Frame length is less than the configured Frame length.
  • When Frame length is more than the configured Frame length.
  • If CRC Error detected.
  • If payload does not match with the length field.
  • Malformed packet received.
  • If frames getting truncated with added exception/error injected scenario.
0x23 ifOutErrors RO The number of transmit frames with one the following errors:
  • FIFO overflow error
  • FIFO underflow error
  • Frames that encounter late or excessive collision occasions
  • Errors defined by the user application
0x24 ifInUcastPkts RO The number of valid unicast frames received.
0x25 ifInMulticastPkts RO The number of valid multicast frames received. The count does not include pause frames.
0x26 ifInBroadcastPkts RO The number of valid broadcast frames received.
0x27 Reserved — Unused.
0x28 ifOutUcastPkts RO The number of valid unicast and erroneous frames transmitted, as well as unicast frames transmitted during late and excessive collision occasions.
0x29 ifOutMulticastPkts RO The number of valid multicast frames transmitted, as well as multicast frames transmitted during late and excessive collision occasions, excluding pause frames.
0x2A ifOutBroadcastPkts RO The number of valid and erroneous broadcast frames transmitted, as well as broadcast frames transmitted during late and excessive collision occasions.
0x2B etherStatsDropEvents RO The number of frames that are dropped due to MAC internal errors when FIFO buffer overflow persists.
0x2C etherStatsOctets RO The total number of octets received. This count includes both good and errored frames.

This register is the lower 32 bits of etherStatsOctets. The upper 32 bits of this statistics counter reside at the dword offset 0x3E.

0x2D etherStatsPkts RO The total number of good and errored frames received.
0x2E etherStatsUndersizePkts RO The number of frames received with length less than 64 bytes, including pause frames. This count does not include errored frames.
0x2F etherStatsOversizePkts RO The number of frames received that are longer than the value configured in the frm_length register. This count does not include errored frames.
0x30 etherStatsPkts64Octets RO The number of 64-byte frames received. This count includes good and errored frames.
0x31 etherStatsPkts65to127Octets RO The number of received good and errored frames between the length of 65 and 127 bytes.
0x32 etherStatsPkts128to255Octets RO The number of received good and errored frames between the length of 128 and 255 bytes.
0x33 etherStatsPkts256to511Octets RO The number of received good and errored frames between the length of 256 and 511 bytes.
0x34 etherStatsPkts512to1023Octets RO The number of received good and errored frames between the length of 512 and 1023 bytes.
0x35 etherStatsPkts1024to1518Octets RO The number of received good and errored frames between the length of 1024 and 1518 bytes.
0x36 etherStatsPkts1519toXOctets RO The number of received good and errored frames between the length of 1519 and the maximum frame length configured in the frm_length register.
0x37 etherStatsJabbers RO Too long frames with CRC error.
0x38 etherStatsFragments RO Too short frames with CRC error.
0x39 Reserved — Unused.
Extended Statistics Counters (0x3C – 0x3E)
0x3C msb_aOctetsTransmittedOK RO Upper 32 bits of the respective statistics counters. By default, all statistics counters are 32 bits wide. These statistics counters can be extended to 64 bits by turning on the Enable 64-bit byte counters parameter.

To read the counter, read the lower 32 bits first, then followed by the extended statistic counter bits.
0x3D msb_aOctetsReceivedOK RO
0x3E msb_etherStatsOctets RO
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