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1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
11. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters
4.1.1. MAC Architecture
4.1.2. MAC Interfaces
4.1.3. MAC Transmit Datapath
4.1.4. MAC Receive Datapath
4.1.5. MAC Transmit and Receive Latencies
4.1.6. FIFO Buffer Thresholds
4.1.7. Congestion and Flow Control
4.1.8. Magic Packets
4.1.9. MAC Local Loopback
4.1.10. MAC Reset
4.1.11. PHY Management (MDIO)
4.1.12. Connecting MAC to External PHYs
6.1.1. 10/100/1000 Ethernet MAC Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals
6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.6. 1000BASE-X/SGMII PCS Signals
6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.1.1. Clock and Reset Signals
6.1.1.2. Clock Enabler Signals
6.1.1.3. MAC Control Interface Signals
6.1.1.4. MAC Status Signals
6.1.1.5. MAC Receive Interface Signals
6.1.1.6. MAC Transmit Interface Signals
6.1.1.7. Pause and Magic Packet Signals
6.1.1.8. MII/GMII/RGMII Signals
6.1.1.9. PHY Management Signals
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6.1.4.2. GTS Transceiver Direct PHY Signals
Name | I/O | Description |
---|---|---|
rx_serial_data | I | Positive signal for the receiver serial data. |
rx_serial_data_n | I | Negative signal for the receiver serial data. |
rx_is_lockedtodata | O | When asserted, this signal indicates that the CDR PLL is locked to the incoming rx_serial data. |
tx_serial_data | O | Positive signal for the transmitter serial data. |
tx_serial_data_n | O | Negative signal for the transmitter serial data. |
tx_ready | O | Status signal from GTS Native PHY. It is asserted when Native PHY TX datapath resets sequencing is complete. |
rx_ready | O | Status signal from GTS Native PHY. It is asserted when Native PHY RX datapath resets sequencing is complete. |
tx_pll_refclk_p | I | Positive signal for the 156.25 MHz reference clock input to Direct PHY. |
rx_cdr_refclk_p | I | 156.25 MHz reference clock for CDR PLL. |
phyip_reset_tx_in | I | TX reset input for TX transceivers and TX datapath of Direct PHY. |
phyip_reset_rx_in | I | RX reset input for RX transceivers and RX datapath of Direct PHY. |
phyip_reset_tx_ack_o | O | TX fully in reset indicator. |
phyip_reset_rx_ack_o | O | RX fully in reset indicator. |
system_pll_clk | I | 322.2656 MHz or 644.53125 MHz system PLL clock. |
system_pll_lock | I | System PLL lock signal for system clock IP. |
rx_is_lockedtoref | O | CDR lock status signal.
|
tx_pll_locked | O | TX PLL locked to reference clock within the PPM threshold status signal.
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