Visible to Intel only — GUID: bhc1410941943098
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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Devices
3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 M-Series Devices
4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series Devices
5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 Devices
6. PHY Lite for Parallel Interfaces Intel® FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
7. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
8. Document Revision History for the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration
6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
6.5.6.4.5. I/O Timing Violation
6.5.6.4.6. Internal FPGA Path Timing Violation
Visible to Intel only — GUID: bhc1410941943098
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6.4. I/O Standards
The PHY Lite for Parallel Interfaces Intel® FPGA IP allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.
I/O Standard | Valid Input Terminations (Ω) 16 | Valid Output Calibrated/Uncalibrated Terminations (Ω)16 | RZQ (Ω) 17 | Differential/Complementary I/O Support |
---|---|---|---|---|
SSTL-12 18 | 60, 120 | 40, 60 | 240 | Yes |
SSTL-125 18 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-135 18 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-15 18 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-15 Class I 19 | 0, 50 | 0, 50 | 100 | Yes |
SSTL-15 Class II19 | 0, 50 | 0, 25 | 100 | Yes |
SSTL-18 Class I19 | 0, 50 | 0, 50 | 100 | Yes |
SSTL-18 Class II19 | 0, 50 | 0, 25 | 100 | Yes |
1.2-V HSTL Class I19 | 0, 50 | 0, 50 | 100 | Yes |
1.2-V HSTL Class II19 | 0, 50 | 0, 25 | 100 | Yes |
1.5-V HSTL Class I19 | 0, 50 | 0, 50 | 100 | Yes |
1.5-V HSTL Class II19 | 0, 50 | 0, 25 | 100 | Yes |
1.8-V HSTL Class I19 | 0, 50 | 0, 50 | 100 | Yes |
1.8-V HSTL Class II19 | 0, 50 | 0, 25 | 100 | Yes |
1.2-V POD | 34, 40, 48, 60, 80, 120, 240 | 34, 40, 48, 60 | 240 | Yes |
1.2-V | — | — | — | No |
1.5-V | — | — | — | No |
1.8-V | — | — | — | No |
I/O Standard | Valid Input Terminations (Ω) 16 | Valid Output Calibrated/Uncalibrated Terminations (Ω)16 | RZQ (Ω) 17 | Differential/Complementary I/O Support |
---|---|---|---|---|
SSTL-12 20 | 60, 120 | 40, 60 | 240 | Yes |
SSTL-125 20 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-135 20 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-15 20 | 60, 120 | 34, 40 | 240 | Yes |
SSTL-15 Class I 21 | 0, 50 | 0, 50 | 100 | Yes |
SSTL-15 Class II21 | 0, 50 | 0, 25 | 100 | Yes |
SSTL-18 Class I21 | 0, 50 | 0, 50 | 100 | Yes |
SSTL-18 Class II21 | 0, 50 | 0, 25 | 100 | Yes |
1.2-V HSTL Class I21 | 0, 50 | 0, 50 | 100 | Yes |
1.2-V HSTL Class II21 | 0, 50 | 0, 25 | 100 | Yes |
1.5-V HSTL Class I21 | 0, 50 | 0, 50 | 100 | Yes |
1.5-V HSTL Class II21 | 0, 50 | 0, 25 | 100 | Yes |
1.8-V HSTL Class I21 | 0, 50 | 0, 50 | 100 | Yes |
1.8-V HSTL Class II21 | 0, 50 | 0, 25 | 100 | Yes |
1.2-V POD | 34, 40, 48, 60, 80, 120, 240 | 34, 40, 48, 60 | 240 | Yes |
1.2-V | — | — | — | No |
1.5-V | — | — | — | No |
1.8-V | — | — | — | No |
16 0 is equivalent to no termination.
17 RZQ pin is not required for uncalibrated output terminations.
18 Use this I/O standard if input termination is required with interface frequency more than 533 MHz.
19 Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz.
20 Use this I/O standard if input termination is required with interface frequency more than 533 MHz.
21 Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz.