PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

4.2.3.1. Clocks

The PHY Lite for Parallel Interfaces Intel® FPGA IP sources a reference clock from a dedicated clock pin to the PLL inside the IP. This PLL provides four clock domains for the output and input paths.

Table 59.   PHY Lite for Parallel Interfaces Intel® FPGA IP Clock Domains
Clock Domain Description
Core clock The IP generates this clock internally and uses it for all transfers between the FPGA core fabric and I/O banks. The clock phase alignment (CPA) circuitry keeps the clock in phase with the PHY clock for transfers between the core and the periphery.
PHY clock The IP uses this clock internally for PHY circuitry running at the same frequency as the core clock.
VCO clock The PLL generates this clock internally. The input and output paths use the VCO clock to generate interpolator delays that compensates for PVT variations.
Interface clock This is the clock frequency of the external device connected to the FPGA I/Os.
Table 60.  Interface Frequencies Supported by the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series Devices
Core Clock Rate Speed Grade –1 (MHz) Speed Grade –2 (MHz) Speed Grade –3 (MHz)
Min Max Min Max Min Max
Quarter 100 1,200 100 933 100 933
Half 100 800 100 666 100 600
Full 100 400 100 333 100 300