PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

6.4. I/O Standards

The PHY Lite for Parallel Interfaces Intel® FPGA IP allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.

Table 140.  I/O Standards and Termination Values for Arria® 10 Devices
I/O Standard Valid Input Terminations (Ω) 16 Valid Output Calibrated/Uncalibrated Terminations (Ω)16 RZQ (Ω) 17 Differential/Complementary I/O Support
SSTL-12 18 60, 120 40, 60 240 Yes
SSTL-125 18 60, 120 34, 40 240 Yes
SSTL-135 18 60, 120 34, 40 240 Yes
SSTL-15 18 60, 120 34, 40 240 Yes
SSTL-15 Class I 19 0, 50 0, 50 100 Yes
SSTL-15 Class II19 0, 50 0, 25 100 Yes
SSTL-18 Class I19 0, 50 0, 50 100 Yes
SSTL-18 Class II19 0, 50 0, 25 100 Yes
1.2-V HSTL Class I19 0, 50 0, 50 100 Yes
1.2-V HSTL Class II19 0, 50 0, 25 100 Yes
1.5-V HSTL Class I19 0, 50 0, 50 100 Yes
1.5-V HSTL Class II19 0, 50 0, 25 100 Yes
1.8-V HSTL Class I19 0, 50 0, 50 100 Yes
1.8-V HSTL Class II19 0, 50 0, 25 100 Yes
1.2-V POD 34, 40, 48, 60, 80, 120, 240 34, 40, 48, 60 240 Yes
1.2-V No
1.5-V No
1.8-V No
Table 141.  I/O Standards and Termination Values for Cyclone® 10 GX Devices
I/O Standard Valid Input Terminations (Ω) 16 Valid Output Calibrated/Uncalibrated Terminations (Ω)16 RZQ (Ω) 17 Differential/Complementary I/O Support
SSTL-12 20 60, 120 40, 60 240 Yes
SSTL-125 20 60, 120 34, 40 240 Yes
SSTL-135 20 60, 120 34, 40 240 Yes
SSTL-15 20 60, 120 34, 40 240 Yes
SSTL-15 Class I 21 0, 50 0, 50 100 Yes
SSTL-15 Class II21 0, 50 0, 25 100 Yes
SSTL-18 Class I21 0, 50 0, 50 100 Yes
SSTL-18 Class II21 0, 50 0, 25 100 Yes
1.2-V HSTL Class I21 0, 50 0, 50 100 Yes
1.2-V HSTL Class II21 0, 50 0, 25 100 Yes
1.5-V HSTL Class I21 0, 50 0, 50 100 Yes
1.5-V HSTL Class II21 0, 50 0, 25 100 Yes
1.8-V HSTL Class I21 0, 50 0, 50 100 Yes
1.8-V HSTL Class II21 0, 50 0, 25 100 Yes
1.2-V POD 34, 40, 48, 60, 80, 120, 240 34, 40, 48, 60 240 Yes
1.2-V No
1.5-V No
1.8-V No
16 0 is equivalent to no termination.
17 RZQ pin is not required for uncalibrated output terminations.
18 Use this I/O standard if input termination is required with interface frequency more than 533 MHz.
19 Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz.
20 Use this I/O standard if input termination is required with interface frequency more than 533 MHz.
21 Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz.