PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

4.5.2. Reference Clock

Intel recommends that you source the reference clock to the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series devices from a dedicated clock pin. Use the clock pin in the I/O sub-bank with the following command:
set_location_assignment <PIN_NUMBER> -to <pll_ref_clock_signal_name>