PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

4.2.4.3. Dynamic Reconfiguration Guidelines

The PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series devices allows you to dynamically reconfigure the features of the interface. No traffic should occur during reconfiguration. Reframing is necessary, particularly in continuous strobe mode of operation. Intel recommends performing dynamic calibration for application with core clock frequency of more than 533 MHz. This section provides the general guidelines for calibrating Agilex™ 7 F-Series and I-Series I/O architecture.

Note: Follow the guidelines when generating your own dynamic reconfiguration controller.