PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

3.2.1.1. Clocks

The PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 M-Series devices sources the reference clock from a dedicated clock pin to the PLL inside the IP. This PLL provides four clock domains for the output and input paths.
Table 34.   PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 M-Series Devices Clock Domains
Clock Domain Description
Core clock The IP generates this clock internally and uses it for all transfers between the FPGA core fabric and I/O banks. The clock phase alignment (CPA) circuitry keeps the clock in phase with the PHY clock for transfers between the core and the periphery.
PHY clock The IP uses this clock internally for PHY circuitry.
VCO clock The PLL generates this clock internally. The input and output paths use the VCO clock to generate interpolator delays that compensate for PVT variations.
Interface clock This is the clock frequency of the external device connected to the FPGA I/Os.
Table 35.  Interface Frequencies Supported by the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 M-Series Devices
Interface Frequency (MHz) Core Clock Rate (PHYLITE_IN_RATE) VCO Frequency Multiplier Factor (PHYLITE_OUT_RATE) VCO Clock Frequency (MHz) PHY Clock (MHz) Core Clock Frequency (MHz)
600-1250 4 1 600-1250 300-625 150-312.5
300-600 2 2 600-1200 300-600 150-300
150-300 1 4 600-1200 300-600 150-300
Note: The core clock rate of the PHY Lite for Parallel Interfaces Intel® FPGA IP is fixed based on selected interface frequency.