PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

3.5.1. Generating the Design Example

To generate a design example, click Generating Example Design in the IP Parameter Editor.

The software generates a user-defined directory in which the design example files reside.

There are two variants of design example available for PHY Lite for Parallel Interfaces Intel® FPGA IP:

  • Without dynamic reconfiguration
  • With dynamic reconfiguration
Table 55.   PHY Lite for Parallel Interfaces Intel® FPGA IP Design Example Variants
Design Example Variant Design File Description
Dynamic Reconfiguration On ed_synth.qsys (synthesis only) Consists of PHY Lite for Parallel Interfaces Intel® FPGA IP instance with Calibration IP.
ed_sim.qsys (simulation only) Consists of PHY Lite for Parallel Interfaces Intel® FPGA IP instance with Calibration IP, IOSSM Tester, Tester Core, and Tester I/O
Off ed_synth.qsys (synthesis only) Consists of PHY Lite for Parallel Interfaces Intel® FPGA IP instance.
ed_sim.qsys (simulation only) Consists of PHY Lite for Parallel Interfaces Intel® FPGA IP instance with Tester Core and Tester I/O.