PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

6.5.5. Dynamic Reconfiguration

If you are using the dynamic reconfiguration feature, all interfaces of the External Memory Interfaces and PHY Lite for Parallel Interfaces Intel® FPGA IP cores in the same I/O column must share the reset signal. Multiple IP cores requiring Avalon core access require daisy chain connectivity.