PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

2.3. Getting Started

You can instantiate the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series devices from IP Catalog in the Quartus® Prime software. Intel provides an integrated parameter editor that allows you to customize this IP to support a wide variety of applications. The IP generation can be invoked from both the GUI and command line.

In IP Catalog, you can search the PHY Lite IP from, Libraries > Basic Function > I/O as shown in the following figure.

Figure 12.  PHY Lite for Parallel Interfaces Intel® FPGA IP in IP CatalogThis figure shows Invoking PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series devices.

Selecting PHY Lite for Parallel Interfaces Intel® FPGA IP launches the IP Parameter Editor as shown in the succeeding figure.

Figure 13. IP Parameter EditorThis figure shows the IP Parameter Editor for PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series devices.

The IP parameters can be set from the IP Parameter Editor. The grayed-out parameters are computed automatically. The parameters with an adjacent checkbox can either be set automatically or manually. For example, in the preceding figure, if the checkbox Use recommended PLL reference clock frequency is selected, the parameter PLL reference clock frequency is grayed out and its value is computed automatically. Unchecking the checkbox enables selecting other values for this parameter. After parameterizing, users can select Generate HDL or Generate Example Design.

Alternatively, the IP GUI can be invoked with the following command:

qsys-edit <IP name>.ip --new-component-type=phylite_ph2 --family=”Agilex 5” 
--part=<part_name>

For example:

qsys-edit new.ip --new-component-type=phylite_ph2 --family=”Agilex 5” 
--part=A5EC065BB32AE5S

Using ip-deploy command, the default value for a few of the parameters can be changed:

ip-deploy --family="Agilex 5" --part=" A5EC065BB32AE5SR0" --output-name="dut"
--component-name="phylite_ph2" 
--component-param="GUI_PHYLITE_MEM_CLK_FREQ_MHZ=800.0"
--component-param="BYTE_IO_STANDARD=IO_STANDARD_IOSTD_POD12"
--component-param="GUI_GROUP_0_PIN_TYPE=INPUT"