PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

4.3.1.2. Write Latency

Table 70.  Maximum Write LatencyThis shows the maximum write latency value supported by PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 devices based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate VCO Multiplier Factor Write Latency (External Memory Clock Cycle)
Quarter 1 17
2 15
4 14
8 14
Half 1 11
2 9
4 7
8 8
Full 1 8
2 6
4 5
8 5