PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

6.2.5.1. RTL Connectivity

The PHY Lite for Parallel Interfaces Intel® FPGA IP exposes the Avalon® memory-mapped interface master and Avalon® memory-mapped interface slave interfaces when you enable the dynamic reconfiguration feature. If the generated IP is the only PHY Lite for Parallel Interfaces Intel® FPGA IP (with dynamic reconfiguration) or External Memory Interface IP in the I/O column, connect only the Avalon® memory-mapped interface slave interface with a master in the core. Otherwise, connect Avalon® memory-mapped interface master and slave interfaces as described in the following section.