PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 7/15/2024
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Document Table of Contents
Document Table of Contents x
1. About the PHY Lite for Parallel Interfaces IP 2. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Devices 3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 M-Series Devices 4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series Devices 5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 Devices 6. PHY Lite for Parallel Interfaces Intel® FPGA IP for Arria® 10 and Cyclone® 10 GX Devices 7. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives 8. Document Revision History for the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
1. About the PHY Lite for Parallel Interfaces IP x
1.1. Device Family Support 1.2. Features
2. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Devices x
2.1. Release Information 2.2. Functional Description 2.3. Getting Started 2.4. I/O Standards 2.5. Design Example
2.2. Functional Description x
2.2.1. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Devices Top Level Interfaces 2.2.2. Dynamic Reconfiguration
2.2.1. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Devices Top Level Interfaces x
2.2.1.1. Clocks 2.2.1.2. Output Path 2.2.1.3. Input Path
2.2.2. Dynamic Reconfiguration x
2.2.2.1. Calibration IP 2.2.2.2. Dynamic Reconfigurable Delays 2.2.2.3. Register Map
2.3. Getting Started x
2.3.1. Parameter Settings 2.3.2. Signals
2.3.2. Signals x
2.3.2.1. Clock and Reset Interface Signals 2.3.2.2. Output Path Signals 2.3.2.3. Input Path Signals
2.4. I/O Standards x
2.4.1. Design Guidelines
2.4.1. Design Guidelines x
2.4.1.1. DQS Trees 2.4.1.2. Pin Placement Restrictions 2.4.1.3. Maximum Number of DQ Data Pin Configurations
2.4.1.3. Maximum Number of DQ Data Pin Configurations x
2.4.1.3.1. Automatic and Manual Pin Placement 2.4.1.3.2. Single-Ended Pin Configurations 2.4.1.3.3. Differential Pin Configurations 2.4.1.3.4. Mixed Pin Configurations
2.5. Design Example x
2.5.1. Generate the Design Example 2.5.2. Verify Simulation Design Examples using Tester IP
2.5.1. Generate the Design Example x
2.5.1.1. Design Example without Dynamic Reconfiguration 2.5.1.2. Design Example with Dynamic Reconfiguration
2.5.1.1. Design Example without Dynamic Reconfiguration x
2.5.1.1.1. Generate the Synthesis Design Example without Dynamic Reconfiguration 2.5.1.1.2. Generate the Simulation Design Example Without Dynamic Reconfiguration 2.5.1.1.3. Run the Simulation Design Example Without Dynamic Reconfiguration
2.5.1.2. Design Example with Dynamic Reconfiguration x
2.5.1.2.1. Generate the Synthesis Design Example With Dynamic Reconfiguration 2.5.1.2.2. Generate the Simulation Design Example with Dynamic Reconfiguration 2.5.1.2.3. Run the Simulation Design Example Without Dynamic Reconfiguration
2.5.2. Verify Simulation Design Examples using Tester IP x
2.5.2.1. PHY Lite Interface 2.5.2.2. I/O Model 2.5.2.3. IOSSM Tester 2.5.2.4. Write Test 2.5.2.5. Read Test 2.5.2.6. Calbus Test
3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 M-Series Devices x
3.1. Release Information 3.2. Functional Description 3.3. Getting Started 3.4. I/O Standards 3.5. Design Example
3.2. Functional Description x
3.2.1. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 M-Series Devices Top Level Interfaces 3.2.2. Dynamic Reconfiguration 3.2.3. I/O Timing
3.2.1. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 M-Series Devices Top Level Interfaces x
3.2.1.1. Clocks 3.2.1.2. Output Path 3.2.1.3. Input Path
3.2.1.1. Clocks x
3.2.1.1.1. Clock Frequency Relationships
3.2.2. Dynamic Reconfiguration x
3.2.2.1. Calibration IP 3.2.2.2. Dynamic Reconfigurable Delays 3.2.2.3. Register Map
3.3. Getting Started x
3.3.1. Parameter Settings 3.3.2. Signals
3.3.2. Signals x
3.3.2.1. Clock and Reset Interface Signals 3.3.2.2. Output Path Signals 3.3.2.3. Input Path Signals
3.4. I/O Standards x
3.4.1. Design Guidelines
3.4.1. Design Guidelines x
3.4.1.1. DQS Trees 3.4.1.2. Pin Placement Restrictions
3.5. Design Example x
3.5.1. Generating the Design Example 3.5.2. Verifying Simulation Design Examples using Tester IP
3.5.1. Generating the Design Example x
3.5.1.1. Design Example without Dynamic Reconfiguration 3.5.1.2. Dynamic Reconfiguration Design Examples
3.5.1.1. Design Example without Dynamic Reconfiguration x
3.5.1.1.1. Generating the Synthesis Design Example 3.5.1.1.2. Generating the Simulation Design Example
3.5.1.2. Dynamic Reconfiguration Design Examples x
3.5.1.2.1. Generating the Synthesis Design Example 3.5.1.2.2. Generating the Simulation Design Example
4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series Devices x
4.1. Release Information 4.2. Functional Description 4.3. Getting Started 4.4. I/O Standards 4.5. Design Guidelines 4.6. Design Example
4.2. Functional Description x
4.2.1. Agilex™ 7 F-Series and I-Series I/O Sub-bank Interconnects 4.2.2. Agilex™ 7 F-Series and I-Series Input DQS/Strobe Tree 4.2.3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series Devices Top Level Interfaces 4.2.4. Dynamic Reconfiguration 4.2.5. I/O Timing
4.2.3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series Devices Top Level Interfaces x
4.2.3.1. Clocks 4.2.3.2. Output Path 4.2.3.3. Input Path
4.2.3.1. Clocks x
4.2.3.1.1. Clock Frequency Relationships
4.2.4. Dynamic Reconfiguration x
4.2.4.1. Connectivity 4.2.4.2. Reconfiguration Features and Register Addressing 4.2.4.3. Dynamic Reconfiguration Guidelines
4.2.4.2. Reconfiguration Features and Register Addressing x
4.2.4.2.1. Control Registers Addresses 4.2.4.2.2. Control Registers
4.2.4.3. Dynamic Reconfiguration Guidelines x
4.2.4.3.1. Strobe Enable Window Calibration 4.2.4.3.2. Output and Strobe Enable Minimum and Maximum Phase Settings 4.2.4.3.3. Input DQ/DQS Delay Chains Maximum Values
4.3. Getting Started x
4.3.1. Parameter Settings 4.3.2. Signals
4.3.1. Parameter Settings x
4.3.1.1. Read Latency 4.3.1.2. Write Latency
4.3.2. Signals x
4.3.2.1. Clock and Reset Interface Signals 4.3.2.2. Output Path Signals 4.3.2.3. Input Path Signals
4.4. I/O Standards x
4.4.1. Input Buffer Reference Voltage (VREF) 4.4.2. On-Chip Termination (OCT)
4.4.2. On-Chip Termination (OCT) x
4.4.2.1. RZQ_GROUP Assignment
4.5. Design Guidelines x
4.5.1. Guidelines: Group Pin Placement 4.5.2. Reference Clock 4.5.3. Reset
4.6. Design Example x
4.6.1. Generating the Design Example
4.6.1. Generating the Design Example x
4.6.1.1. Design Example without Dynamic Reconfiguration 4.6.1.2. Dynamic Reconfiguration Design Examples
4.6.1.1. Design Example without Dynamic Reconfiguration x
4.6.1.1.1. Generating the Synthesis Design Example 4.6.1.1.2. Generating the Simulation Design Example
4.6.1.2. Dynamic Reconfiguration Design Examples x
4.6.1.2.1. Generating the Synthesis Design Example 4.6.1.2.2. Generating the Simulation Design Example
5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 Devices x
5.1. Release Information 5.2. Functional Description 5.3. Getting Started 5.4. I/O Standards 5.5. Design Guidelines 5.6. Design Example
5.2. Functional Description x
5.2.1. Top Level Interfaces 5.2.2. Clocks 5.2.3. Output Path 5.2.4. Input Path 5.2.5. Dynamic Reconfiguration
5.2.2. Clocks x
5.2.2.1. Clock Frequency Relationships
5.2.3. Output Path x
5.2.3.1. Output Path Data Alignment
5.2.4. Input Path x
5.2.4.1. Input Path Data Alignment
5.2.5. Dynamic Reconfiguration x
5.2.5.1. RTL Connectivity 5.2.5.2. Address Lookup 5.2.5.3. Reconfiguration Features and Register Addressing 5.2.5.4. Calibration Guidelines
5.2.5.1. RTL Connectivity x
5.2.5.1.1. Daisy Chain
5.2.5.2. Address Lookup x
5.2.5.2.1. Strobes 5.2.5.2.2. Parameter Table Examples
5.2.5.3. Reconfiguration Features and Register Addressing x
5.2.5.3.1. PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 Devices Control Registers Addresses 5.2.5.3.2. Control Registers Description
5.2.5.4. Calibration Guidelines x
5.2.5.4.1. Strobe Enable Window Calibration 5.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
5.3. Getting Started x
5.3.1. Parameter Settings 5.3.2. Signals
5.3.1. Parameter Settings x
5.3.1.1. Read Latency 5.3.1.2. Write Latency
5.3.2. Signals x
5.3.2.1. Clock and Reset Interface Signals 5.3.2.2. Output Path Signals 5.3.2.3. Input Path Signals 5.3.2.4. Avalon Configuration Bus Interface Signals 5.3.2.5. Termination Signals
5.4. I/O Standards x
5.4.1. Input Buffer Reference Voltage (VREF) 5.4.2. On-Chip Termination (OCT)
5.4.1. Input Buffer Reference Voltage (VREF) x
5.4.1.1. Calibrated VREF Settings
5.4.2. On-Chip Termination (OCT) x
5.4.2.1. RZQ_GROUP Assignment 5.4.2.2. Manual Insertion of OCT Block
5.5. Design Guidelines x
5.5.1. Guidelines: Group Pin Placement 5.5.2. Reference Clock 5.5.3. Reset 5.5.4. Constraining Multiple PHY Lite for Parallel Interfaces Intel® FPGA IP to One I/O Bank 5.5.5. Dynamic Reconfiguration 5.5.6. Timing
5.5.6. Timing x
5.5.6.1. Timing Components 5.5.6.2. Timing Constraints and Files 5.5.6.3. Timing Analysis 5.5.6.4. Timing Closure Guidelines
5.5.6.2. Timing Constraints and Files x
5.5.6.2.1. <variation_name>.sdc 5.5.6.2.2. <variation_name>_parameter.tcl 5.5.6.2.3. <variation_name>_ip_parameters.tcl 5.5.6.2.4. <variation_name>_pin_map.tcl 5.5.6.2.5. <variation_name>_report_timing.tcl 5.5.6.2.6. <variation_name>_report_timing_core.tcl
5.5.6.4. Timing Closure Guidelines x
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration 5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 5.5.6.4.5. I/O Timing Violation 5.5.6.4.6. Internal FPGA Path Timing Violation
5.6. Design Example x
5.6.1. Generating the Design Example
5.6.1. Generating the Design Example x
5.6.1.1. Design Example without Dynamic Reconfiguration 5.6.1.2. Dynamic Reconfiguration Design Examples
5.6.1.1. Design Example without Dynamic Reconfiguration x
5.6.1.1.1. Generating the Hardware Design Example 5.6.1.1.2. Generating the Simulation Design Example
5.6.1.2. Dynamic Reconfiguration Design Examples x
5.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine
6. PHY Lite for Parallel Interfaces Intel® FPGA IP for Arria® 10 and Cyclone® 10 GX Devices x
6.1. Release Information 6.2. Functional Description 6.3. Getting Started 6.4. I/O Standards 6.5. Design Guidelines 6.6. Design Example 6.7. Application Specific Design Example
6.2. Functional Description x
6.2.1. Top Level Interfaces 6.2.2. Clocks 6.2.3. Output Path 6.2.4. Input Path 6.2.5. Dynamic Reconfiguration
6.2.2. Clocks x
6.2.2.1. Clock Frequency Relationships
6.2.3. Output Path x
6.2.3.1. Output Path Data Alignment
6.2.4. Input Path x
6.2.4.1. Input Path Data Alignment
6.2.5. Dynamic Reconfiguration x
6.2.5.1. RTL Connectivity 6.2.5.2. Address Lookup 6.2.5.3. Reconfiguration Features and Register Addressing 6.2.5.4. Calibration Guidelines
6.2.5.1. RTL Connectivity x
6.2.5.1.1. Daisy Chain
6.2.5.2. Address Lookup x
6.2.5.2.1. Strobes 6.2.5.2.2. Parameter Table Examples
6.2.5.3. Reconfiguration Features and Register Addressing x
6.2.5.3.1. PHY Lite for Parallel Interfaces Intel® FPGA IP for Arria® 10 and Cyclone® 10 GX Address Registers 6.2.5.3.2. Control Registers Description
6.2.5.4. Calibration Guidelines x
6.2.5.4.1. Strobe Enable Window Calibration 6.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
6.3. Getting Started x
6.3.1. Parameter Settings 6.3.2. Signals
6.3.1. Parameter Settings x
6.3.1.1. Read Latency 6.3.1.2. Write Latency
6.3.2. Signals x
6.3.2.1. Clock and Reset Interface Signals 6.3.2.2. Output Path Signals 6.3.2.3. Input Path Signals 6.3.2.4. Avalon Configuration Bus Interface Signals 6.3.2.5. Termination Signals
6.4. I/O Standards x
6.4.1. Input Buffer Reference Voltage (VREF) 6.4.2. On-Chip Termination (OCT)
6.4.1. Input Buffer Reference Voltage (VREF) x
6.4.1.1. Calibrated VREF Settings
6.4.2. On-Chip Termination (OCT) x
6.4.2.1. RZQ_GROUP Assignment 6.4.2.2. Manual Insertion of OCT Block
6.5. Design Guidelines x
6.5.1. Guidelines: Group Pin Placement 6.5.2. Reference Clock 6.5.3. Reset 6.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 6.5.5. Dynamic Reconfiguration 6.5.6. Timing
6.5.6. Timing x
6.5.6.1. Timing Components 6.5.6.2. Timing Constraints and Files 6.5.6.3. Timing Analysis 6.5.6.4. Timing Closure Guidelines
6.5.6.2. Timing Constraints and Files x
6.5.6.2.1. <variation_name>.sdc 6.5.6.2.2. <variation_name>_parameter.tcl 6.5.6.2.3. <variation_name>_ip_parameters.tcl 6.5.6.2.4. <variation_name>_pin_map.tcl 6.5.6.2.5. <variation_name>_report_timing.tcl 6.5.6.2.6. <variation_name>_report_timing_core.tcl
6.5.6.4. Timing Closure Guidelines x
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration 6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 6.5.6.4.5. I/O Timing Violation 6.5.6.4.6. Internal FPGA Path Timing Violation
6.6. Design Example x
6.6.1. Generating the Design Example
6.6.1. Generating the Design Example x
6.6.1.1. Design Example without Dynamic Reconfiguration 6.6.1.2. Dynamic Reconfiguration Design Examples
6.6.1.1. Design Example without Dynamic Reconfiguration x
6.6.1.1.1. Generating the Hardware Design Example 6.6.1.1.2. Generating the Simulation Design Example
6.6.1.2. Dynamic Reconfiguration Design Examples x
6.6.1.2.1. Dynamic Reconfiguration with Debug Kit 6.6.1.2.2. Dynamic Reconfiguration Using Finite State Machine
6.7. Application Specific Design Example x
6.7.1. Implementation using the PHY Lite for Parallel Interfaces Intel® FPGA IP
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Devices
3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 M-Series Devices
4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series Devices
5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 Devices
6. PHY Lite for Parallel Interfaces Intel® FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
7. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
8. Document Revision History for the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

5.3.1. Parameter Settings

Table 95.   PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 Devices Parameter Settings
GUI Name Values Default Values Description
Parameter
Number of groups 1 to 18 1 Number of data and strobe groups in the interface. The value is set to 1 by default.
General Tab- these parameters are set on a per interface basis
Clocks
Interface clock frequency 100 MHz - 1200 MHz 533.0 MHz External memory clock frequency.
Note: To achieve timing closure at 534 MHz and above, use dynamic reconfiguration to calibrate the interface. Compile your design with Quartus® Prime with accurate board skew information for final timing analysis.
Use recommended PLL reference clock frequency On, Off On

If you want to calculate the PLL reference clock frequency automatically for best performance, turn on this option.

If you want to specify your own PLL reference clock frequency, turn off this option.

PLL reference clock frequency Dependent on desired memory clock frequency 133.25 MHz PLL reference clock frequency. You must feed a clock of this frequency to the PLL reference clock input of the memory interface.
Note: There is no minimum range, but the maximum output frequency is 1600 MHz, limited by the clock network. The minimum range for the ref_clk signal is 10 MHz but the maximum is dependent on the speed grade.
VCO clock frequency Calculated internally by PLL 1066.0 MHz The frequency of this clock is calculated internally by the PLL based on the interface clock and the core clock rate.
Clock rate of user logic Full, Half, Quarter Quarter Determines the clock frequency of user logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800 MHz, a "Quarter rate" interface means that the user logic in the FPGA runs at 200 MHz.
Specify additional output clocks based on existing PLL On, Off Off Exposes additional output clocks from the existing PLL.
Output Clocks
Note: These parameters are available only if the Specify additional output clocks based on existing PLL parameter is turned on
Number of additional clocks 0 to 4 0 Specifies the number of additional clocks to be exposed.
outclk[4:0] (Reserved) — — PLL output clocks with the flag (Reserved) in the QSYS GUI are reserved for PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP internal functionality.
Desired Frequency — 133.25 MHz Specifies the output clock frequency of the corresponding output clock port, outclk[], in MHz. The minimum and maximum values depend on the device used. The PLL only reads the numerals in the first six decimal places.
Actual Frequency — 133.25 MHz Allows you to select the actual output clock frequency from a list of achievable frequencies.
Phase shift units ps or degrees ps Specifies the phase shift unit for the corresponding output clock port, outclk[], in picoseconds (ps) or degrees.
Phase shift — 469.0 ps Specifies the requested value for the phase shift. The default value is 0 ps.
Actual phase shift — 469.0 ps Allows you to select the actual phase shift from a list of achievable phase shift values. The default value is the closest achievable phase shift to the desired phase shift.
Desired duty cycle 0.0–100.0 50.0 % Specifies the requested value for the duty cycle.
Actual duty cycle — 50.0 % Allows you to select the actual duty cycle from a list of achievable duty cycle values. The default value is the closest achievable duty cycle to the desired duty cycle.
Dynamic Reconfiguration
Use dynamic reconfiguration On, Off Off Exposes an Avalon memory-mapped interface, allowing you to control the configuration of the PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP settings.
First PHYLite Instance in the Avalon Chain On, Off On

Select this parameter if this IP instance is the first instance in the Avalon chain, connected to the master.

This parameter is only available when you select Use dynamic reconfiguration .

Important: Do not select this parameter if there is an External Memory Interface IP selected as the first instance in the chain, available in the same column.
Interface ID — 0 The ID used to identify this interface in the I/O column over the Avalon memory-mapped bus.
I/O Settings
I/O standard

SSTL-12

SSTL-125

SSTL-135

SSTL-15

SSTL-15 Class I

SSTL-15 Class II

SSTL-18 Class I

SSTL-18 Class II

1.2-V-HSTL Class I

1.2-V-HSTL Class II

1.5-V-HSTL Class I

1.5-V-HSTL Class II

1.8-V-HSTL Class I

1.8-V-HSTL Class II

1.2-V POD

1.2-V

1.5-V

1.8-V

None

SSTL-15 Class I Specifies the I/O standard of the interface's strobe and data pins written to the .qip file of the IP instance. When you choose None, the I/O standard is unspecified in the generated IP.
Reference clock I/O configuration

Single-ended,

LVDS with on-chip termination,

LVDS without on-chip termination

 Single-ended Specify the reference clock I/O configuration.
General Settings
Fast simulation model On, Off Off

Turn on this option to reduce PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP simulation time.

Note: This option is preliminarily supported in Quartus® Prime v18.1.
Group <x> - these parameters are set on a per group basis
Group <x> Parameter Settings
Copy parameters from another group On, Off Off Select this option when you want to copy the parameter settings from another group.

Set Number of groups to more than 1 to enable this option.

Group 1 - 17 1 Choose the group index that you want as the parameter settings source. The changes made to the source is updated automatically to all the target groups.

You can only choose the group index which the parameter settings are not copied from another group.

Set Number of groups to more than 1 to enable this option.

Group <x> Pin Settings
Note: These parameters are disabled when Copy parameters from another group is enabled.
Pin type Input, Output, Bidirectional Bidirectional Direction of data pins. This value is set to Bidirectional by default.
Pin width 1 to 48 9 Number of pins in this data/strobe group.

A data width up to 48 is achievable if no strobe is used in the group. The number of strobes is controlled by the Use output strobe, Strobe configuration and Use separate capture strobe parameters.

DDR/SDR DDR, SDR DDR Double/single data rate.
Group <x> Input Path Settings
Note: These parameters are disabled when Copy parameters from another group is enabled.
Read latency 1 to 63 external interface clock cycles 7 Expected read latency of the external device in memory clock cycles.

For example, a design with an external clock frequency of 533 MHz in half-rate has a valid read latency range of 5 to 63 external interface clock cycles.

Refer to the Read Latency topic for minimum read latency settings based on FPGA core clock rate.

Swap capture strobe polarity On, Off Off Internally swap the negative and positive capture strobe input pins. This feature is only available for complementary strobe configurations.
Capture strobe phase shift 0, 45, 90, 135, 180 90 Internally phase shift the input strobe relative to input data.
Group <x> Output Path Settings
Note: These parameters are disabled when Copy parameters from another group is enabled.
Write latency 0 to 3 (maximum value is dependent on the rate) 0 Additional delay added to the output data in memory clock cycles.

Refer to the Write Latency topic for write latency settings based on FPGA core clock rate.

Use output strobe On, Off On Use an output strobe.
Output strobe phase 0, 45, 90, 135, 180 90 Phase shift of the output strobe relative to the output data.
Group <x> General Data Settings
Note: These parameters are disabled when Copy parameters from another group is enabled.
Data configuration Single ended Single ended

Selects the type of data. Single ended data type uses one pin. Differential data type uses 2 pins.

PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP does not support differential data pins.

Refer to the I/O Standards topic for a list of supported I/O standards.

Group <x> General Strobe Settings
Note: These parameters are disabled when Copy parameters from another group is enabled.
Strobe configuration Single ended, Differential, Complementary Single ended

Select the type of strobe. A single ended strobe uses one pin, which reduces the maximum possible number of data pins in the group to 47. Differential/complementary strobe types use 2 pins, which reduces the maximum possible number of data pins in the group to 46.

Note: The differential strobe configuration uses a differential input buffer, which produces a single clock for the capture DDIO and read FIFO. The complementary strobe configuration uses two single-ended input buffers and clocks the data into the capture DDIO and read FIFO using both clocks (as required by protocols such as QDRII). The output path functionality is the same.

Refer to the I/O Standards topic for a list of supported I/O standards.

Use separate strobes On, Off Off Separate the bidirectional strobe into input and output strobe pins. Use separate strobes is only available for a bidirectional data group with the output strobe enabled.
Group <x> OCT Settings
Note: These parameters are disabled when Copy parameters from another group is enabled.
OCT enable size

0 - 15 ( Stratix® 10 devices)

1 Specifies the delay between the OCT enable signal assertion and the dqs_enable signal assertion. You must set a value that is large enough to ensure that the OCT is turn on before sampling input data.
Expose termination ports On, Off Off

Turn on to expose the series and parallel termination ports to connect separate OCT block.

To enable this option, turn off Use Default OCT Values parameter and select a value for Input OCT Value or Output OCT Value parameters.

Use Default OCT Values — — Use default OCT values based on the I/O standard parameter setting.
Input OCT Value No termination, <n> ohm with calibration No termination

Specifies the group's data and strobe input termination values to be written to the .qip of the IP instance. The list of legal values is dependent on the I/O standard parameter setting. Refer to the I/O Standards topic.

This option is available when the Use Default OCT Values option is disabled.

Output OCT Value No termination, <n> ohm with calibration, <n> with no calibration No termination

Specifies the group's data and strobe input termination values to be written to the .qip of the IP instance. The list of legal values is dependent on the I/O standard parameter setting. Refer to the I/O Standards topic supported termination values.

This option is available when the Use Default OCT Values option is disabled.

Group <x> Timing Settings
Note: These parameters are disabled when Copy parameters from another group is enabled.
Generate Input Delay Constraints for this group On, Off On Instructs SDC to generate set_input_delay constraints for this group.
Input Strobe Setup Delay Constraint Constraint in ns 0.03 ns Specifies the group's input setup delay constraint against the input strobe.
Input Strobe Hold Delay Constraint Constraint in ns 0.03 ns Specifies the group's input hold delay constraint against the input strobe.
Inter Symbol Interference of the Read Channel Constraint in ns 0.09 ns Specifies the Inter Symbol Interference value for DQS signal of read channel.

Specify a positive value to decrease the setup and hold slack by half of the entered value.

Generate Output Delay Constraints for this group On, Off On Instructs SDC to generate set_output_delay constraints for this group.
Output Strobe Setup Delay Constraint Constraint in ns 0.03 ns Specifies the group's output setup delay constraint against the input strobe.
Output Strobe Hold Delay Constraint Constraint in ns 0.03 ns Specifies the group's output hold delay constraint against the input strobe.
Inter Symbol Interference of the Write Channel Constraint in ns 0.09 ns Specifies the Inter Symbol Interference value for DQS signal of write channel.

Specify a positive value to decrease the setup and hold slack by half of the entered value.
Group <x> Dynamic Reconfiguration Timing Settings
Note: These parameters are disabled when Copy parameters from another group is enabled.
Dynamic Reconfiguration Read Deskew Algorithm DQ Per-Bit Deskew, DQ Group Deskew, Custom Deskew DQ Per-Bit Deskew Specifies the Read Deskew algorithm for Timing Analyzer to use when performing I/O timing analysis:
  • DQ Per-Bit Deskew: Each DQ pin is adjusted independently to minimize the skew within the DQ bits. DQS signal is adjusted to center-align to the de-skewed DQ bus. Each DQ bit may have different delay chain settings.
  • DQ Group Deskew: DQS signal is adjusted center-align to the DQ bus without de-skewing individual DQ bits. All DQ bits within the same group has same delay chain settings.
  • Custom Deskew: DQS is aligned based on the recoverable setup and hold slack you defined.

You must select Use dynamic reconfiguration option to enable this parameter.

Setup Slack Recoverable of Custom Read Deskew Algorithm Constraint in ns 0.0 ns Specifies the amount of positive setup slack available based on your custom read deskew algorithm.
This parameter is available with the conditions:
  • Use dynamic reconfiguration is turn on
  • Pin type is set to Input or Bidirectional and
  • Dynamic Reconfiguration Read Deskew Algorithm is set to Custom Deskew
Hold Slack Recoverable of Custom Read Deskew Algorithm Constraint in ns 0.0 ns Specifies the amount of positive hold slack available based on your custom read deskew algorithm.
This parameter is available with the conditions:
  • Use dynamic reconfiguration is turn on
  • Pin type is set to Input or Bidirectional and
  • Dynamic Reconfiguration Read Deskew Algorithm is set to Custom Deskew
Dynamic Reconfiguration Write Deskew Algorithm DQ Per-Bit Deskew, DQ Group Deskew, Custom Deskew DQ Per-Bit Deskew Specifies the Write Deskew algorithm for Timing Analyzer to use when performing I/O timing analysis:
  • DQ Per-Bit Deskew: DQS signal is centered to each individual DQ bits. Each DQ bit may have different delay chain settings.
  • DQ Group Deskew: DQS signal is centered to the DQ bus group. All DQ bits within the same group has same delay chain settings.
  • Custom Deskew: DQS is aligned based on the recoverable setup and hold slack you defined.

You must select Use dynamic reconfiguration option to enable this parameter.

Setup Slack Recoverable of Custom Write Deskew Algorithm Constraint in ns 0.0 ns Specifies the amount of positive setup slack available based on your custom write deskew algorithm.
This parameter is available with the conditions:
  • Use dynamic reconfiguration is turn on
  • Pin type is set to Output or Bidirectional and
  • Dynamic Reconfiguration Write Deskew Algorithm is set to Custom Deskew
Hold Slack Recoverable of Custom Write Deskew Algorithm Constraint in ns 0.0 ns Specifies the amount of positive hold slack available based on your custom write deskew algorithm.
This parameter is available with the conditions:
  • Use dynamic reconfiguration is turn on
  • Pin type is set to Output or Bidirectional and
  • Dynamic Reconfiguration Write Deskew Algorithm is set to Custom Deskew

Section Content
Read Latency
Write Latency

Related Information
Level Two Title