4.2.3.3. Input Path

PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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Date 7/15/2024

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4.2.3.3. Input Path

The input path of the IP consists of a data path, a strobe path, and a read enable path as shown in the following figure.

Figure 97. Input Path

Table 62. Blocks in Data, Strobe, and Read Enable Paths
Path	Description
Data Path	Receives data from external device to the FPGA core logic. The data path consists of a PVT compensated delay chain, a DDIO and a read FIFO. DDIO and read FIFO—Responsible for deserialization with a factor of up to 8 (in DDR quarter-rate). The transfer between the DDIO and the read FIFO is a zero-cycle transfer. Signals used in this path are: `group_data_in`—Input data from external device. `group_data_io`—Input and output data from/to external device. `group_data_to_core` (output)—Output data to the Intel FPGA core. `phy_clk`—This is an internal clock signal that provides clock to the blocks used in this path. The IP supports SDR input by sending data on single clock cycle from the external device.
Strobe Path	Input strobe (`dqs`) to capture input data from external device. The strobe path consists of pstamble_reg (a gating component) and a PVT compensated delay chain. pstamble_reg—This gating circuitry ensures that only clock edges associated with valid input data are used. PVT compensated delay chain—Provides a phase offset between the strobe and the data (for example, center aligning edge-aligned inputs). Signals used in this path are: `group_strobe_in`, `group_strobe_in_n` (input)—Input strobe from external device. . `group_strobe_io`, `group_strobe_io_n`(bidirectional)—Input and output strobe from/to external device. `group_strobe_io_n` is used when strobe configuration is set to Differential. `dqs_clean`(output)—This internal signal is the refined version of `strobe_in` signal. `dqs`(input)—This internal signal is an input strobe to DDIO and Read FIFO in the data path, after phase shift adjustment.
Read and Strobe Enable Path	Generates control signals for strobe calibration and reading data from Read FIFO. The read and strobe enable path consists of VFIFO, DQS_EN FIFO, and an interpolator. VFIFO—Takes the `rdata_en` signal from the core and delays it separately for two outputs, one for the read enable on the Read FIFO, and one for the strobe enable. These delays are calculated at generation time based on the read latency that you provide. DQS_EN FIFO and interpolator—Used for the strobe enable delay, the DQS_EN FIFO and interpolator are identical to the Write FIFO and interpolator circuitry in the output path. The DQS_EN FIFO and interpolator are configured to match the output delay for a group with no additional output delay (Write latency = `0`). Signals used in this path are: `group_rdata_valid` (output)—This signal determines which data are valid when reading from Read FIFO. This signal is delayed by the Read latency value set in the parameter editor. `group_rdata_en` (input)—This signal represents the number of expected words to read from the external device. `dqs_enable_in` (input)—This is an internal signal that provides dqs delay value to the pstamble_reg module to process a refined dqs signal. `dqs_enable_out` (output)— This is an internal strobe with the delayed value specified by the dqs_enable_in signal. `phy_clk`—This is an internal clock for VFIFO and Read FIFO modules. `phy_clk_phs`—This is an internal clock for the interpolator. `interpolator_clk`—This is an internal clock for DQS_EN FIFO module.

Table 63. Read Operation SequenceA read operation is performed as listed in this table.
Read Operation Sequence Number	Operation
1	The core asserts the `rdata_en` signal to the PHY Lite for Parallel Interfaces Intel® FPGA IP and issues a read command to the external device.
2	VFIFO and DQS_EN FIFO generate the `dqs_enable` signal to pstamble_reg. This signal is delayed by the programmed read latency (which should match the latency of the external device).
3	The pstamble_reg generates `dqs_clean` signal as valid data enters the read path.
4	The Delay Chain (PVT) adjusts the strobe with phase offset between the strobe and the input data (for example, 90° phase shift for DDR center-alignment).
5	The `dqs` signal is then used as strobe to read data from external device into the DDIO and Read FIFO modules.
6	The VFIFO asserts the `read_enable` signal to Read FIFO and the `rdata_valid` signal to the core simultaneously. The PHY Lite for Parallel Interfaces Intel® FPGA IP sends the captured data to the core with the associated valid signal.