PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

2.2.1.1. Clocks

The PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series sources an external reference clock from a dedicated clock pin to the PLL inside the IP. This PLL provides four clock domains for the output and input paths.

Table 2.  Clock Domains of the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series
Clock Domain Description
Interface clock This is the clock frequency of the external device connected to the FPGA I/Os.
VCO clock The PLL generates this clock internally. The input and output paths use the VCO clock to generate interpolator delays that compensates for PVT variations.
PHY clock The IP uses this clock internally for PHY circuitry.
Core clock The IP generates this clock internally and uses it for all transfers between the FPGA core fabric and I/O banks. The clock phase alignment (CPA) circuitry keeps the clock in phase with the PHY clock for transfers between the core and the periphery.

The clock frequency of user logic and other clocks are derived from the interface clock frequency based on predetermined PHYLITE_IN_RATE and PHYLITE_OUT_RATE parameters as shown in the following equation and are summarized in the following table. The calculated core clock frequency is fixed based on the selected interface clock frequency and displayed in the IP parameter editor as a grayed-out value as shown in the following figure.

Equation 1. Relationships Between Clock DomainsThese equations describe the relationships between the clock domains available in the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series.

Table 3.  Interface Frequencies Supported by the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Devices
Interface Frequency (MHz) PHYLITE_IN_RATE (Core Clock Rate) PHYLITE_OUT_RATE (VCO Frequency Multiplier Factor) VCO Clock Frequency (MHz) PHY Clock Frequency (MHz) Core Clock Frequency (MHz)
600-1250 4 1 600-1250 300-625 150-312.5
300-600 2 2 600-1200 300-600 150-300
150-300 1 4 600-1200 300-600 150-300
Note:
  • For the boundary frequencies of 300 MHz, PHYLITE_IN_RATE = 1 and PHYLITE_OUT_RATE = 4.
  • For the boundary frequencies of 600 MHz, PHYLITE_IN_RATE = 2 and PHYLITE_OUT_RATE = 2.
Figure 3. Clock Settings in the IP Parameter Editor of PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Devices