PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

6.2.4.1. Input Path Data Alignment

The bus ordering of data_to_core, rdata_en, and rdata_valid is identical to the ordering of the output path. That is, the LSBs of the bus hold the first time slice of data received.

The rdata_valid delay is always set by the IP to match the rdata_en alignment. For example, quarter-rate delays are multiples of four external memory clock cycles (one quarter rate clock cycle).

Figure 151. Example Input (Quarter Rate DDR) - AlignedThe waveform shows an example of aligned reads on the input path of the PHY Lite for Parallel Interfaces Intel® FPGA IP. At the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows data of 4'hf, which represents all incoming data are aligned. The group_0_rdata_valid bus shows the data of 4'hf, which represents all incoming data are valid. Therefore, the incoming read data on the group_0_data_to_core bus matches the data seen on the group_0_data_io bus.


Reading from an unaligned memory address is called unaligned reads. Unaligned reads results in unaligned rdata_valid and data_to_core with data and valid signals packed to the LSBs. This request causes the IP to do two or more read operations.

Figure 152. Example Input (Quarter Rate DDR) - UnalignedThe waveform shows an example of unaligned reads on the input path of the PHY Lite for Parallel Interfaces Intel® FPGA IP.

The data from an unaligned read operation comes in two phases. At the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows value of 4'he, which shows there are 6 bytes of incoming data from group_0_data_io bus. On the subsequent clock cycle, the group_0_rdata_en bus shows value of 4'h1, which shows there are 2 bytes of incoming data from group_0_data_io bus.

The valid data are transfer to the IP through the group_0_data_to_core bus. At first rising edge of the core_clk_out signal, group_0_rdata_valid bus shows a value of 4'h7, which represents the first 6 bytes of the data from the group_0_data_to_core bus are valid and the last 2 bytes are invalid. On the subsequent clock cycle, group_0_rdata_valid bus shows the value of 4'h1, which shows the last 2 bytes of the data from the group_0_data_to_core bus are valid.