PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

4.6.1.2.1. Generating the Synthesis Design Example

The make_qii_design.tcl generates a synthesizable hardware design example and an Quartus® Prime project, ready for compilation.

To generate synthesizable design example, run the following script at the end of IP generation:
quartus_sh -t make_qii_design.tcl
To specify an exact device to use, run the following script:
quartus_sh -t make_qii_design.tcl [device_name]

This script generates a qii directory containing a project called ed_synth.qpf. You can open and compile this project using the Quartus® Prime software.

The synthesis design example provides an example of the core and I/O connectivity for your IP configuration with Calibration IP as the interface for the Avalon® memory-mapped interface calibration addresses. The connection of Calibration IP to PHY Lite for Parallel Interfaces Intel® FPGA IP is limited to one calibration IP per row.

Figure 107. Connection of Calibration IP to PHY Lite for Parallel Interfaces Intel® FPGA IP This figure shows an example of multiple (five in this example) PHY Lite for Parallel Interfaces Intel® FPGA IPs within one I/O row. Thus, only one calibration IP is needed to connect all five PHY Lite for Parallel Interfaces Intel® FPGA IPs to the Calibration IP.
Note: Follow the guidelines described in the Dynamic Reconfiguration Guidelines section when generating your own dynamic reconfiguration controller.