PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

5.4.2.2. Manual Insertion of OCT Block

You may also instantiate the OCT Intel® FPGA IP separately in your project and connect the termination ports to the PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 devices.

  1. Expose the PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 devices termination ports by disable Use Default OCT Values.
  2. Select the available OCT values in the Input OCT Value parameter. This displays the Expose termination ports parameter.
    Note: For supported input and output OCT values, refer to the I/O Standards topic.
  3. Select Expose termination ports to expose the termination ports in the IP.
  4. Connect the termination ports to a OCT Intel® FPGA IP either in power-up or user mode.
Figure 131. RTL View of PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 Devices Interfacing with OCT Intel® FPGA IP in User Mode