PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: jzb1599794048302
Ixiasoft
Visible to Intel only — GUID: jzb1599794048302
Ixiasoft
5.4.2.2. Manual Insertion of OCT Block
You may also instantiate the OCT Intel® FPGA IP separately in your project and connect the termination ports to the PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 devices.
- Expose the PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 devices termination ports by disable Use Default OCT Values.
- Select the available OCT values in the Input OCT Value parameter. This displays the Expose termination ports parameter.
Note: For supported input and output OCT values, refer to the I/O Standards topic.
- Select Expose termination ports to expose the termination ports in the IP.
- Connect the termination ports to a OCT Intel® FPGA IP either in power-up or user mode.