PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

2.5. Design Example

The PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series devices is able to generate a design example that matches the same configuration chosen for the IP. The design example is a simple design that does not target any specific application. However, you can use the design example as a reference on how to instantiate the IP and what behavior to expect in a simulation.

You can generate a design example by clicking Generating Example Design in the IP Parameter Editor.

Note: The generated .qsys files are for internal use during design example generation only. You should not edit the files.