PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

4.3.1.1. Read Latency

Table 69.  Minimum Read Latency This table shows the minimum read latency value supported by PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 devices based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate VCO Multiplier Factor Read Latency (External Memory Clock Cycle)
Quarter Rate 1 17
2 16
4 15
8 14
Half Rate 1 11
2 10
4 9
8 8
Full Rate 1 8
2 7
4 6
8 5