PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

4.2.3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series Devices Top Level Interfaces

The PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series devices consists of the following ports:

  • Clocks and reset
  • Core data and control (divided into input and output paths)
  • I/O (divided into input and output paths)
Figure 95. Top-Level Interface This figure shows the top-level diagram of the PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series devices interface.