PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

2.5.2. Verify Simulation Design Examples using Tester IP

The design examples, both with dynamic reconfiguration and without dynamic reconfiguration, use Tester IP to verify PHY Lite for Parallel Interfaces IP functionality. The tester exercises read and write operations to the PHY Lite for Parallel Interfaces IP to verify its functionality.

At a high level, the tester is a state machine that repeatedly performs read/write operations. Disabling a test causes the corresponding tester state to be skipped. The following lists the tester states in the order they are performed:

  1. STATE_INIT: Initialization
  2. STATE_TEST_CALBUS: Calibration when dynamic reconfiguration is enabled
  3. STATE_TEST_WRITE: Enabled only in output and bidirectional modes
  4. STATE_TEST_READ: Enabled only in input and bidirectional modes
  5. STATE_DONE: All bursts of data successfully transmitted

The following table shows the port connections between the PHY Lite for Parallel Interfaces IP instance and Tester module. Tester ports not shown in the table are pass_out and fail_out which signal the success or failure of the test. Multiple PHY Lite for Parallel Interfaces IP groups can be tested by daisy chaining testers and connecting pass_out and fail_out of each tester to the pass_in and fail_in ports of the next tester in chain. The Calbus ports are not shown in the table as well.

In the write tests, PHYLite Interface module sends pseudorandom binary sequence (PRBS) pattern, strobe, and control signals to PHY Lite IP instance, and PHY Lite IP instance outputs the data and strobe to the I/O model, where the data are checked against the PRBS pattern. In the read tests, the reverse happens.

Table 28.  PHY Lite IP Instance and Tester Port ConnectionsThis table lists the PHY Lite IP instance and Tester port connections.
Ports Connection PHY Lite for Parallel Interfaces Ports Width Tester Ports
PHY Lite for Parallel Interfaces interface submodule group_X_data_from_core GROUP_DATA_WIDTH group_data_from_core
group_X_oe_from_core GROUP_CTRL_WIDTH group_oe_from_core
group_X_strobe_from_core GROUP_STROBE_WIDTH group_strobe_from_core
group_X_strobe_out_en GROUP_CTRL_WIDTH group_strobe_out_en
group_X_data_to_core GROUP_DATA_WIDTH group_data_to_core
group_X_rdata_en GROUP_CTRL_WIDTH group_rdata_en
group_X_rdata_valid GROUP_CTRL_WIDTH group_rdata_valid
I/O model group_X_data_out GROUP_PIN_WIDTH group_data_out
group_X_data_out_n GROUP_PIN_WIDTH group_data_out_n
group_X_data_in GROUP_PIN_WIDTH group_data_in
group_X_data_in_n GROUP_PIN_WIDTH group_data_in_n
group_X_data_io GROUP_PIN_WIDTH group_data_io
group_X_data_io_n GROUP_PIN_WIDTH group_data_io_n
group_X_strobe_out 1 group_strobe_out
group_X_strobe_out_n 1 group_strobe_out_n
group_X_strobe_in 1 group_strobe_in
group_X_strobe_in_n 1 group_strobe_in_n
group_X_strobe_io 1 group_strobe_io
group_X_strobe_io_n 1 group_strobe_io_n

The tester instantiates the following three submodules:

  • I/O model: Connects to the PHY Lite for Parallel Interfaces I/O interface. Includes two instances of pseudorandom binary sequence (PRBS) channel, one to generate random pattern for read tests, and one to check the received pattern in the write tests.
  • PHYLite interface: Connects to the PHY Lite for Parallel Interfaces IP core interface. Includes two instances of PRBS channel, one to generate random pattern for write tests, and one to check received pattern in the read tests. Reframing logic is also included in this module.
  • IOSSM tester: Exposes an AXI4-Lite IP Interface and performs reads and writes to change the TX delay on pin 0. Only available for simulation example design with dynamic reconfiguration.
Table 29.  Tester Module Top Level Interfaces
Module Parameter Default value Description
IOSSM Tester TESTER_PRBS_SEED 36'b000000111110000011110000111000110010 Seed for the LFSRs used to generate the pseudorandom bitstream that is used for test data
TESTER_NUM_REPEATS 8 How many times to repeat the test sequence
TESTER_NUM_BURSTS 1024 Number of bursts to send per test. In this tester a "burst" refers to one core clock of data (e.g., 8 bits in QR DDR). This is not to be confused with the internal burst length setting in the PHY.
TESTER_PREAMBLE_MODE ONE_CYCLE Refer to Read Test section for a visual illustration.
TESTER_IS_LAST_IN_CHAIN 1 Whether this tester is the last one in the daisy-chain. This will mean that in simulation it calls $finish() after reaching the end of its testing.
PHYLite Interface PHYLITE_USE_DYNAMIC_RECONFIGURATION 0

0 – without dynamic reconfiguration

1 – with dynamic reconfiguration

PHYLITE_MEMCLK_PERIOD_PS 1667 Period of the interface frequency in picoseconds
PHYLITE_IN_RATE 4 Rate conversion factor
PHYLITE_READ_LATENCY 8 Latency from rddata_en to DQS ungate
PHYLITE_WRITE_STROBE_ALIGNMENT CENTER_ALIGNED Either "CENTER_ALIGNED" or "EDGE_ALIGNED" - Alignment of data output by PHYLite
PHYLITE_READ_STROBE_ALIGNMENT CENTER_ALIGNED Either "CENTER_ALIGNED" or "EDGE_ALIGNED" - Alignment of data input to PHYLite
Group GROUP_PIN_WIDTH 8 1-22
GROUP_PIN_TYPE BIDIRECTIONAL INPUT, OUTPUT or BIDIRECTIONAL
GROUP_DDR_SDR_MODE DDR SDR or DDR
GROUP_DATA_CONFIG SINGLE_ENDED SINGLE_ENDED or DIFFERENTIAL
GROUP_STROBE_CONFIG DIFFERENTIAL SINGLE_ENDED or DIFFERENTIAL