List of Messages

ID:10099 Input port PINPERSTN of PCI Express Hard IP node "<text>" is not connected to an I/O.
ID:10100 Input port <name> of PCI Express Hard IP node "<name>" should not be connected to GND or VCC.
ID:10104 Unable to find a path between I/O pad and PINPERST port of PCI Express Hard IP.
ID:10151 "<text>" is not a legal location for "<text>" connected to PINPERSTN of PCI Express Hard IP.
ID:10371 <cell>
ID:10729 No hardware or devices were detected while indexing connections. Verify that the target board is attached and powered on the reindexed connections.
ID:10848 Calibration must be rerun after enabling the all groups to be attempted for calibration to apply the setting.
ID:10878 Calibration must be rerun after disabling guaranteed read testing during calibration to apply the setting.
ID:10905 Generated the EDA functional simulation netlist because it is the only supported netlist type for this device.
ID:10907 Missing required Base Revision assignment in current persona or aggregate revision.
ID:10908 Unable to establish a connection because no <connection type> targets exist on the linked device.
ID:10914 Error #<number> <name>: <name> in frame <name>.
ID:10919 Specify programming hardware setup.
ID:10927 In Stratix V engineering sample device, a false EDCRC error on frame 0 occurs after PR completes.
ID:10929 The Fitter is disabling hold optimization on the following clock transfers, because the estimated amount of delay added for hold on these transfers is too large. Usually this is due to bad timing constraints (e.g. missing multicycle, false path on the transfers). For more information, refer to the "Ignored Clock Transfers Due to Huge Delay Added for Hold" section in the Fitter report. If you want to force hold optimization on these transfers, set the ENABLE_HOLD_BACK_OFF setting to OFF.
ID:10930 Error occurred while running the System Console command <tcl command>. System Console returned the result <tcl error>. You must shutdown the toolkit and restart.
ID:10931 Multiple persona usage partition "<name>" has unsupported bidirectional port "<name>"
ID:10933 Combinational logic "<name>" depth is over 6000, which may cause stack overflow. The synthesis may fail.
ID:11080 Multiple remote update factory pages detected
ID:11082 An error occurred while running jtagconfig. The jtagconfig process returned the result <process status> with error code <error code>.
ID:11083 Preparing to run jtagconfig.
ID:11084 Running jtagconfig completed successfully.
ID:11085 Combinational logic depth is over 6000, which may cause stack overflow. The synthesis may fail.
ID:11087 PMA direct channel(s) detected and needs to be constrained based on the guidelines in Arria V Device Handbook Volume 2: Transceiver chapter
ID:11088 Logic constrained to the region <llr> can be fed by the <clktype> clock signal(s) listed below, but the region overlaps multiple <clktype> clock regions: <regions>
ID:11089 Signal <optional> promoted to a <clktypes> network: <name>
ID:11090 Logic constrained to the region <llr> can be fed by the clock signal(s) listed below, which reserved <num_regions> spine clock region(s)
ID:11091 <PLL output counter> cannot route to any <destination type>
ID:11092 Invalid emulation mode hardware driver <requested version>.
ID:11093 Creating emulation mode hardware driver <driver version>.
ID:11094 Dumping of internal data is not supported for connection <connection name>.
ID:11098 Selected on-board programming hardware is disabled
ID:11099 Unable to generate the EDA simulation netlist files because the Quartus Prime software does not currently support post-compilation simulation for the <name> devices.
ID:11100 More than one <name> index option specified
ID:11101 Unable to generate the VHDL EDA simulation netlist files because the Quartus Prime software does not currently support VHDL post-compilation simulation for the <name> devices.
ID:11104 Parallel Compilation has detected <num_threads_detected> hardware threads are supported by <num_cores_detected> physical processor cores. Parallel compilation will use up to <num_threads> threads.
ID:11105 For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
ID:11106 Shared VREF <name> is used as GPIO (<name>). This action reduces fMAX performance of this pin.
ID:11107 ATX PLL node "<name>" uses a VCO frequency that is not currently supported.
ID:11108 Hardware <hardware name> and device <device name>, which are linked, have no connections.
ID:11110 Successfully unlinked project from device.
ID:11111 PLL "<name>" is used for LVDS or external memory interfaces, but the PLL is not an integer PLL.
ID:11112 Input port <port_type> on atom "<name>" is not connected to a valid source.
ID:11113 Input port "<port_type>" must be connected to a PLL or a clock buffer
ID:11114 Active serial configuration mode is selected with the INIT_DONE pin disabled. Depending on the configuration setup and board design, the INIT_DONE pin may need to be enabled in the design. For more information, refer to the Intel FPGA Knowledge Database solution number rd05092012_239
ID:11115 PHY clock tree is driven by PLL output <output_port> (counter: <pll_counter_index>, location: <location>)
ID:11116 PLL output counters 0-3 or 14-17 are not used for driving the PHY clock tree in your device
ID:11117 PLL counters that drive the PHY clock tree can be constrained using the set_location_assignment <PLL counter location> -to <PLL output signal> assignment
ID:11118 PLL output counters driving PHY clock tree are not recommended for use in the memory IP PHY clock tree and may cause decreased performance
ID:11121 Memory interface <connection name> with protocol type <protocol enum> is not supported for IP version <IP version>.
ID:11122 Settings use_phase_ctrlin and invert_phase must match between "<div_name>" and "<ipa_name>".
ID:11123 Atoms "<div_name>" and "<ipa_name>" must be connected to the same DQS configuration atom.
ID:11124 Atoms "<div_name>" and "<ipa_name>" must be connected to the same DLL.
ID:11125 Connection to <connection name> cannot be established because the connection type is not supported.
ID:11126 The following locations cannot be used because they are not supported on all the specified migration devices
ID:11128 The following signal cannot be routed: <name>. The device does not contain the routing resources required to make this connection
ID:11131 Completed upgrading IP component <name> with file "<name>"
ID:11133 IP component <name> with file "<name>" upgrade failed
ID:11135 Directory "<directory>" does not exist or the directory path is invalid
ID:11136 File "<directory>" does not exist or the file path is invalid
ID:11138 Invalid explicit clock region "<name>". Clock regions of type "<name>" range from <number>-<number>.
ID:11139 The explicit clock region "<name>" appears to be a list of Clock Spine indices, but one or more of the index values is invalid. Values in the list need to be integers in the range from <number>-<number>.
ID:11140 Input pin <name> has too many fanouts (number of fanouts is <name> which is larger than the threshold value of <name>) -- the delay chains of the input pin will not be optimized
ID:11141 PLL "<name>" drives a non-DPA LVDS interface, but the PLL is not in LVDS compensation mode.
ID:11142 PCIe Gen3 HIP is not supported in autonomous mode "<name>".
ID:11147 Netlist is corrupted. Fitter found different logic interfaces (number <number> and <number>) that are connected to Avalon Memory-Mapped instance: <name>
ID:11148 Netlist is corrupted. Fitter cannot find any logic interfaces connected to Avalon Memory-Mapped instance: <name>
ID:11162 <name> with <number> fanout uses <string> clock <string>
ID:11164 Can't fit design in device
ID:11165 Fitter preparation operations ending: elapsed time is <time>
ID:11166 Previous compilation results are reused as part of this compilation and may cause the error on this compilation.
ID:11167 io_smart_recompile option processes the following assignments only:
ID:11168 Assignment <text>
ID:11169 PLL compensation delay chain reconfiguration operation is skipped - no timing information is available
ID:11170 Starting IP generation for the debug fabric: <entity name>.
ID:11171 Finished IP generation for the debug fabric: <entity name>.
ID:11172 <message>
ID:11175 <message>
ID:11176 <message>
ID:11177 Node drives <string> from (<number>, <number>) to (<number>, <number>)
ID:11178 Promoted <number> clock<string> <string>
ID:11179 The <cell> could not be placed in any location to satisfy its connectivity requirements
ID:11180 PLL node "<name>" uses a VCO frequency of <name> MHz that exceeds the PMA maximum frequency of <name> MHz in targeted speed grade "<name>".
ID:11181 Could not place cell <name> at <name> due to a location constraint to <name>
ID:11186 Fanout is constrained to region from (<number>, <number>) to (<number>, <number>)
ID:11191 Automatically promoted <number> clock<string> <string>
ID:11192 Input port "<text>[<number>]" of "<text>" cannot connect to PLD port "<text>[<number>]" of "<text>" for node "<text>".
ID:11193 Output port "<text>[<number>]" of "<text>" cannot connect to PLD port "<text>[<number>]" of "<text>" for node "<text>".
ID:11195 ATX PLL node "<name>" uses a frequency that may not be supported on all ATX PLLs.
ID:11212 Too many clock sources are connected to atom "<name>" via xN clocking, only <number> clock lines are available.
ID:11215 Input port "<text>" of "<text>" cannot connect to PLD port "<text>" of "<text>" for node "<text>".
ID:11216 Output port "<text>" of "<text>" cannot connect to PLD port "<text>" of "<text>" for node "<text>".
ID:11217 Node "<name>" has no location constraint.
ID:11218 Fitter post-fit operations ending: elapsed time is <time>
ID:11219 Device <name> does not support HPS IOCSR.
ID:11220 Invalid executable path.
ID:11224 JTAG Debug Information File (.jdi) for the project does not match the specified target device because not all nodes have hierarchy info.
ID:11225 Requested read address <address> is not in the valid address range. Returning 0.
ID:11226 Assigning the partition to non-critical region (0) will cause a soft error in the partition to be ignored.
ID:11230 Selected configuration device, (<string>), does not support die_erase instruction
ID:11231 Selected configuration device, (<string>), does not support bulk_erase instruction
ID:11237 Already placed at this location: <cell>
ID:11238 The following <number> <type> locations are already occupied, and the Fitter cannot merge the previously placed nodes with these instances. The nodes may have incompatible inputs or parameters.
ID:11239 Location <location> is already occupied by <cell>.
ID:11250 Command has too many specified options
ID:11375 Can't place PR block <name> in dedicated location (<number>, <number>, <number>)
ID:11376 Design partition "<name>" assigned to a non-critical error detection region.
ID:11378 Bus from node "<name>" to node "<name>" may not be connected properly. The lsb of source and destination are not aligned.
ID:11379 Inversions on the input from node "<name>" to node "<name>" are inconsistent.
ID:11380 Input from node "<name>" to node "<name>" is extended from a number without MSB(s).
ID:11381 Input from node "<name>" to node "<name>" is a deficient number and the node is a multiplier.
ID:11382 Extension on the input from node "<name>" to node "<name>" is inconsistent with the sign property.
ID:11383 Input from node "<name>" to node "<name>" is unsigned but this node is a signed operator.
ID:11384 Input from node "<name>" to node "<name>" is signed but this node is an unsigned operator.
ID:11385 Unable to generate the Verilog EDA simulation netlist files because the Quartus Prime software does not currently support Verilog post-compilation simulation for the <name> devices.
ID:11451 Input pipeline register clock of atom "<name>" must be set to output clock in Systolic mode.
ID:11452 Data files for part <part name> required by the project are not available. Ensure that all data files for family <family name> are installed.
ID:11453 Can't generate this report. Routing utilization report is not supported for current device.
ID:11454 Can't generate this report -- Fitter (quartus_fit) failed or was not run. Run the Fitter (quartus_fit) successfully first.
ID:11457 Error occurred when creating the <report type> report.
ID:11458 Successfully created <report type> report in <time> seconds.
ID:11488 Clock phase select atom "<name>" is inconsistent with current QSF assignments.
ID:11489 Connection path <connection path> was not indexed in a previous query of connections. Verify that the hardware has not changed and reset the target.
ID:11490 Number of connections found in the current list of connections does not match the list of previous connections. Verify that the hardware has not changed and reset the target.
ID:11491 Read request of <expected size> words was sent to the target but only <actual size> was returned.
ID:11492 Could not determine a device service path for hardware <hardware name> and device <device name>.
ID:11493 Could not determine the device name from the device connection path <connection path>.
ID:11494 Could not determine the hardware name from the device connection path <connection path>.
ID:11495 Destination: core logic constrained to <name> fed by <name>
ID:11497 Report name cannot be empty.
ID:11498 Read ISSP functionality is not available in the <hardware driver name> fake hardware driver.
ID:11500 Linking device <hardware name> on hardware <device name> using .sof file <sof file name>.
ID:11501 System Console warning during design link: <warning message>.
ID:11504 Device <size> is detected as EPC device instead of MAX II/MAX V.
ID:11559 Reserved Logic Lock region "<name>" does not fully enclose one or more core blocks.
ID:11561 <name> with <number> fanout was merged with this clock
ID:11562 dqsupdateen input of DQS delay chain "<name>" must be driven by the same DLL as the delayctrlin input when connected
ID:11563 No <name> output file specified.
ID:11564 No <name> input file specified.
ID:11566 Found mismatched device name for MSF and SOF files. MSF: <name>, SOF: <name>
ID:11569 Invalid setting: <name> can only be used when <name> is enable. To use <name>, please enable <name>
ID:11570 Invalid setting: <name> and <name> can only be used when <name> is enable. To use <name> or <name>, please enable <name>
ID:11571 Found mismatched device name for MSF and SOF files. MSF: <name>, SOF: <name>
ID:11572 Fitter cannot use this non-default slow timing corner <name> for timing-driven compilation. It will use the default slow corner <name> instead. This may lead to bad timing closure results, as the fitter is optimized for the default corner, not the user-specified corner.
ID:11573 Can't enable DCLK because the device initialization clock is in active serial configuration mode.
ID:11574 ATX PLL node "<name>" uses an output frequency of <name> MHz that exceeds the maximum frequency of <name> MHz in the targeted speed grade "<name>" for a <name> ATX PLL in a transceiver bank.
ID:11575 ATX PLL node "<name>" uses an output frequency of <name> MHz that exceeds the maximum frequency of <name> MHz for GT parts in the targeted speed grade "<name>" for a <name> ATX PLL in a transceiver bank on the <name> side of the device.
ID:11577 The <name> node's ARESET/ACLR port is illegally connected. All registers in an IOREG must use the same ARESET signal.
ID:11578 Cannot place due to overuse of <core resource type> resources
ID:11579 Estimated usage is <core resource estimation in # of blocks> resource<plural>.
ID:11581 <number of locations affected> location<plural> affected
ID:11582 <location name>
ID:11584 Location has <core resource count> resource<plural>.
ID:11586 Also placed at this location: <other signal>
ID:11617 DQS Delay Chain '<DQS Delay Chain instance name>' is not connected to a DLL, which may result in unexpected values of the phase shift. The delays annotated on the DQS Delay Chains that are not connected to a DLL are invalid in the Timing Analyzer. Intel suggests that all DQS Delay Chains be connected to a DLL
ID:11618 Netlist is corrupted. Fitter found unexpected Netlist related to instance: <name>
ID:11619 REFCLK pin "<text>" is placed in a RX Data Channel location.
ID:11620 Corrected error #<number> : <name> in frame <name> at bit <name>.<name>
ID:11622 Corrected error #<number> : <name> in frame <name>.
ID:11623 <number> frame error(s) corrected in device <number>.
ID:11624 Found Partial Reconfiguration regions vertically overlapped in SCRUB mode.
ID:11625 Found Partial Reconfiguration regions vertically overlapped in SCRUB mode
ID:11626 <number>% of device bits are critical for ASD region <number>
ID:11630 Converted the rules in the Quartus Prime Message Suppression Rule File to the latest format.
ID:11632 Error #<number> <name>: <name> in frame <name> at bit <name> and bit <name>.<name>
ID:11633 Corrected error #<number> : <name> in frame <name> at bit <name> and bit <name>.<name>
ID:11640 REFCLK pin "<text>" is placed in a RX Data Channel location. This feature is not supported in ES devices.
ID:11650 Skip device <size> key verification
ID:11653 Output port "<text>[<number>]" of "<text>" cannot connect to HSSI port "<text>[<number>]" of "<text>" for node "<text>".
ID:11654 Output port "<text>" of "<text>" cannot connect to HSSI port "<text>" of "<text>" for node "<text>".
ID:11655 Can't locate programming file <name> in <name>. Found and loaded programming file <name> from the current Chain Description File directory <name>
ID:11656 Imported partitions contain unsupported format -- rerun Partition Merge
ID:11657 Partition "<name>" was compiled for device <name> -- ignoring placement
ID:11658 Ignoring previous placement for partitions compiled for incompatible devices
ID:11661 Design uses HSSI PLLs that are not supported in the selected device.
ID:11662 Output port "<text>[<number>]" of "<text>" cannot connect to HSSI port "<text>[<number>]" of "<text>". Check this connection if routing fails.
ID:11663 Output port "<text>[<number>]" of "<text>" cannot connect to HSSI port due to missing route information "<text>[<number>]" of "<text>". Check this connection if routing fails.
ID:11665 Fitter failed to read .mif file: <name>. Refer to Fitter report for related RAM instances.
ID:11666 Device "<name>" does not support "<name>".
ID:11667 Input reference clock of <name> must originate from a clock pin
ID:11668 Partial Reconfiguration requires a separate license, in addition to the subscription license.
ID:11670 Project name required.
ID:11671 Illegal project name "<name>".
ID:11672 Illegal top-level entity name "<name>".
ID:11673 Selected feature of the Fitter is not available with your current license, or the license does not exist.
ID:11678 File <path> is read-only!
ID:11679 Cannot generate top-level file because folder <path> does not exist
ID:11681 Advanced SEU Detection data for the current design is compressed to <number> bytes.
ID:11682 Fitter errors out for missed reconfiguration controller.
ID:11684 Differential I/O pin "<name>" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "<name>"
ID:11685 <number> differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins
ID:11686 <text>. Your design contains an illegal constraint in transceiver bank: <text>. Change the location of the specified signals so that the transceiver bank contains only two PLLs.
ID:11687 Channel <text> is assigned to location <text> and channel <text> is assigned to location <text>. However, channels with different reconfiguration controllers cannot be placed in the same channel triplet. Modify your design so that both channels share the same reconfiguration controller.
ID:11688 Channel <text> is assigned to location <text> and channel <text> is assigned to location <text>, however channels with different PMA auxiliary block assignments cannot be placed in the same quadrant. Modify your design so that the channels are in different quadrants, or the channels have the same PMA auxiliary block.
ID:11689 <text> and <text> cannot be merged, cannot be assigned to <text>.
ID:11690 <text> is assigned to <text>, which is not compatible with the previous location constraint <text>.
ID:11691 <text> is assigned from <text> and <text> is assigned from <text>. <text> and <text> constraints are incompatible with each other.
ID:11692 <number> pma_aux_blocks under reference clocks set <text> exceed the HSSI strip capacity of <number>.
ID:11696 <number> <name> assignments found for <name>. Only the assignment assigned to <name> will take effect
ID:11697 <name> has <name> set to <name>.
ID:11698 <text> is assigned to <text> and <text> is assigned to <text>. <text> and <text> constraints are not on the same strip.
ID:11699 Power analysis is not supported for the selected device <name> in the Intel Quartus Prime software Power Analyzer.
ID:11700 EDCRC feature is disabled when using partial reconfiguration
ID:11701 EDCRC feature is disabled when using CvP
ID:11702 I/O standard assignment '<name>' to pin <name> is not supported by the device. The name '<name>' is not a valid I/O standard name
ID:11705 Can't find any pins with the given conditions.
ID:11706 <text>. Illegal constraint in six pack: <text>
ID:11708 Can't recognize SLD node for device <number>
ID:11710 Found <number> design error detection region(s)
ID:11711 <text>
ID:11712 Illegal value or string encountered while parsing ASM HPS string
ID:11713 The configuration of the Hard Processor Subsystem (HPS) within this design has changed. The Preloader software that initializes the HPS requires an update. Using <name>, run the Preloader Support Package Generator to update your Preloader software
ID:11714 Can't generate HPS IOCSR file.
ID:11715 <number>% of device bits are design critical bits, with some bits shared across the <number> ASD regions.
ID:11718 Partial Reconfiguration compression feature is not supported when CvP feature is enabled and Partial Reconfiguration encryption feature is disabled
ID:11719 Cannot generate a Partial Reconfiguration bitstream with the Compression and CvP options enabled and Partial Reconfiguration Encryption feature disabled.
ID:11776 Run Partition Merge (quartus_cdb --merge) with top-level entity name "<name>" before running Fitter (quartus_fit)
ID:11777 Run Analysis and Synthesis (quartus_map) with top-level entity name "<name>" before running Fitter (quartus_fit)
ID:11778 Device part "<name>" is illegal
ID:11779 Run Analysis and Synthesis (quartus_map) with Incremental Compilation set to Off for top-level entity name "<name>" before running Fitter (quartus_fit)
ID:11780 Run Partition Merge (quartus_cdb --merge) with Incremental Compilation set to incremental synthesis for top-level entity name "<name>" before running Fitter (quartus_fit)
ID:11781 Run Analysis and Synthesis (quartus_map) with Incremental Compilation enabled for top-level entity name "<name>" before running Fitter (quartus_fit)
ID:11782 Analysis and Synthesis (quartus_map) must be run using device family <name> before running the Fitter (quartus_fit) with device part <name>
ID:11783 Analysis and Synthesis (quartus_map) must be run using device family <name> before running the Fitter (quartus_fit)
ID:11784 Design partition boundaries were not preserved on a previous compilation - Design partitions will not be used for this compilation
ID:11785 Use of the AUTO device part is not supported for family <family>. Ensure a valid device part is selected before running the Fitter.
ID:11787 Family "<name>" is illegal
ID:11788 Interactive use of the Quartus Fitter (quartus_fit) is not supported using the device family <name>
ID:11789 The device "<name>" is not valid as not all the required device files are installed
ID:11793 Fitter databases successfully split.
ID:11804 Found the same source (<name>) driving multiple ports on node <name>
ID:11807 Cannot generate a Partial Reconfiguration bitstream with the Compression option enabled for a Cyclone V device.
ID:11808 Partial Reconfiguration compression feature is not supported on Cyclone V devices
ID:11809 <name> feature is not supported for the <name> device family.
ID:11810 Double Accumulator feature is not supported when the Accumulator is disabled. To enable Accumulator, set the "ACCUMULATOR" parameter to "YES".
ID:11811 Invalid setting: <name> can only be used when <name> is enabled. To use <name>, enable <name>
ID:11812 Invalid setting: <name> and <name> can only be used when <name> is enabled. To use <name> or <name>, please enable <name>
ID:11813 Cannot use output port <name> of the ALTERA_MULT_ADD megafunction with the <name> device family.
ID:11814 Cannot select more than three clock and clock enable pairs in the <name> device family.
ID:11815 Cannot select asynchronous clear signals aclr2 or aclr3 for the <name> device family.
ID:11816 Cannot use input port <name> of the ALTERA_MULT_ADD megafunction with the <name> device family.
ID:11817 WIDTH_COEF parameter value is illegal.
ID:11818 Illegal parameter value: <name> is greater than <name> for PREADDER_MODE=INPUT
ID:11819 Illegal parameter value: SYSTOLIC_DELAY1 and SYSTOLIC_DELAY3 can only be used when NUMBER_OF_MULTIPLIERS equals to 2 or 4
ID:11820 Illegal parameter value: SYSTOLIC_DELAY1 and SYSTOLIC_DELAY3 are used without the chainin port.
ID:11821 Illegal parameter value: <name> port is not instantiated.
ID:11822 Illegal parameter value: LOADCONST_VALUE of <name>
ID:11823 Illegal parameter value: port <name> is not instantiated for PREADDER_MODE=<name>
ID:11824 Clock source error: illegal value <text> for <name> parameter.
ID:11825 EXTRA_LATENCY parameter supports the value of 0 only.
ID:11826 NUMBER_OF_MULTIPLIERS parameter setting is <number>, but the value of NUMBER_OF_MULTIPLIERS parameter must be less than or equal to 4
ID:11827 Parameter error: illegal value <text> for the DEDICATED_MULTIPLIER_CIRCUITRY parameter.
ID:11828 Value for <name> parameter must be greater than 0.
ID:11829 Adder direction error: illegal value <text> for <name> parameter.
ID:11830 Number representation error: illegal value <text> for <name> parameter.
ID:11831 Cannot connect <name> port when the NUMBER_OF_MULTIPLIERS parameter has a value of <number>. The value must be greater than or equal to 2.
ID:11832 Cannot connect <name> port when the NUMBER_OF_MULTIPLIERS parameter has a value of <number>. The value must be equal to 4.
ID:11833 Asynchronous clear source error: illegal value <text> for <name> parameter.
ID:11834 LogicLock region "<name>" is set to rough. Assignment is ignored because rough regions are not allowed.
ID:11835 DDIO_OUT half rate input "<name>" mode must be set to TRUE when feeding a DDIO_OUT or a FF atom
ID:11836 DDIO_OUT full rate input "<name>" mode must be set to FALSE when feeding an IO_BUFF atom
ID:11837 Started upgrading IP component <name> with file "<name>"
ID:11838 No IP component that requires a required upgrade is found in the project
ID:11844 Fitter has determined that multiple output signals have been mapped to the same physical device output port.
ID:11846 Fitter has determined that multiple input signals have been mapped to the same physical device port, but not all are sourced by the same output signal.
ID:11848 When Hard Reset Controller is enabled, input pin "pin_perst" of PCI Express Hard IP cannot be connected to GND, VCC or user logic and must be wired to an I/O pin. "pin_perst" is connected to input port "PINPERSTN" of "<text>" node ("<text>").
ID:11853 Fitter has determined that one or more input signals have been mapped to more than one physical device input port.
ID:11855 Fitter has determined that one or more output signals have been mapped to a physical device port that does not exist.
ID:11857 Fitter has determined that one or more input signals have been mapped to a physical device port that does not exist.
ID:11859 Fitter has determined that one or more pairs of output and input signals have been mapped to the same physical device port.
ID:11861 Output port <afi_port>[<afi_port_end_index>:<afi_port_start_index>] on module instance "<tile_ctrl_inst>", which is a <tile_ctrl_wys_name> primitive, must be connected to input port AC_HMC[<ac_hmc_end_index>:<ac_hmc_start_index>] on a <lane_wys_name> primitive with a fanout of 1.
ID:11862 Module instance "<tile_ctrl_inst>", which is a <tile_ctrl_wys_name> primitive, has AFI interface output ports <afi_port_one> and <afi_port_two> connected to the AC_HMC input ports of different <lane_wys_name> primitives. These ports must connect to the same <lane_wys_name> primitive.
ID:11863 In PCI Express Hard IP, input pin "pin_perst" cannot be driven by user logic. "pin_perst" is connected to input port "PINPERSTN" of "<text>" node ("<text>").
ID:11865 <name>, port: <name> on node: "<name>"
ID:11866 <name>, "<name>"
ID:11867 <name>, port: <name> on node: "<name>"
ID:11868 <name>, "<name>"
ID:11869 "<name>" connects to <name>, port: <name> on node: "<name>"
ID:11870 Input signal "<name>" connecting to <name> port: <name> on node: "<name>" and <name> output signal "<name>"
ID:11874 Module instance "<tile_ctrl_inst>", which is a <tile_ctrl_wys_name> primitive, has AFI interface output ports <afi_port_one> and <afi_port_two> connected to the AC_HMC input port of the same <lane_wys_name> primitive. These ports must connect to different <lane_wys_name> primitives.
ID:11875 HPS IO File does not support multiple pages and cascaded device chain
ID:11877 Engineering Change Order (ECO) Fitter is skipping Place and Route
ID:11878 Hard Processor Subsystem configuration has not changed and a Preloader software update is not required
ID:11879 Perform Analysis and Elaboration before opening the RTL Viewer.
ID:11880 Project name is required.
ID:11881 "<name>" is not a valid project name.
ID:11882 "<name>" is not a valid focus entity name.
ID:11883 Can't display top-level design entity because the entity is encrypted.
ID:11884 <netlist> is not a valid netlist type.
ID:11885 Perform Analysis and Synthesis before opening the Technology Map Viewer.
ID:11887 The following pin <cell> was placed in a reserved GND location. This may cause decreased performance for HMC. Intel recommends the pin location to be grounded
ID:11888 Total time spent on timing analysis during <name> is <name> seconds.
ID:11889 IP component upgrade failed
ID:11890 Unable to automatically upgrade IP component from Quartus Standard. To upgrade, open "<file>" in Platform Designer.
ID:11891 RTL Viewer found a nameless and unconnected port.
ID:11894 Found board delay larger than <time> ns
ID:11895 Following <number> output pins have "Output Pin Load" capacitance assignments. This assignment is obsolete -- use "Board Model Far C" capacitance assignment using the board trace model instead.
ID:11896 Ignored "Output Pin Load" capacitance assignment on "<pin name>". Assignment is obsolete.
ID:11897 Following <number> input pins have illegal "Input Transition Time" assignments. Default values will be used instead
ID:11898 Input Transition Time "<rise_or_fall>" assignment of "<user specified input transition time>" ps on "<pin name>" is ignored because the value is too small. The minimum value of input transition time for the current I/O standard is "<minimum input transition time>" ps. Using the default input transition time, "<default input transition time>" ps, for this I/O standard.
ID:11899 Ignored "Input Transition Time" assignment of "<user specified input transition time>" ps on "<pin name>" for IO standard, "<io standard>". Input transition time dependent input buffer delays are not supported for differential I/O standards.
ID:11900 An error has occurred while trying to create the Fitter netlist.
ID:11901 File <file> is not a valid variation file
ID:11902 Backing up file "<file>" to "<file>"
ID:11903 File "<file>" is write-protected
ID:11904 Restoring file "<file>" to "<file>"
ID:11907 Can't generate other netlist output files because the license for encrypted file "<name>" is not available. Using INI to enable IBIS output files generation instead
ID:11910 Entering the Tcl queue flush loop
ID:11912 Can't open the RTL Viewer without performing Analysis and Elaboration
ID:11913 Can't display <name> netlist -- top-level design entity is encrypted or does not contain lower-level nodes
ID:11914 Can't execute netlist processing
ID:11917 Cannot use ALTMULT_ACCUM wrapper with <name> device family
ID:11918 Module instance "<serdes_inst>", which is a <serdes_wys_type> primitive and belongs to an ALTLVDS interface, has an illegal parallel data width. The parallel data width of a single channel must fall between <min_width> and <max_width> inclusive
ID:11919 Module instance "<serdes_dpa_inst>", which is a <serdes_dpa_wys_type> primitive, is not configured in a legal mode.
ID:11920 Module instance "<serdes_dpa_inst>", which is a <serdes_dpa_wys_type> primitive and belongs to an ALTLVDS interface using DPA, cannot be driven by a clock pin.
ID:11923 All <serdes_dpa_wys_type> primitives driven by module instance "<lvds_clock_tree_inst>", which is a <lvds_clock_tree_wys_type> primitive, must, or must not use clock pin drive exclusively.
ID:11924 Bank '<name>' has conflicting <name> settings
ID:11926 The node <name> has following assignments: <assignments> Are you sure you want to delete the node and assignments?
ID:11927 '<name>' setting of <name> specified by assignment to bank '<name>'
ID:11928 '<name>' with I/O standard <name>, was constrained to be within bank '<name>'
ID:11929 '<name>' is a valid <name> value
ID:11930 The node <name> is in the design file. Update the top-level design file after deleting.
ID:11931 Reference clock pin <text> for ATT channel is locked to <text>, lock to <text> to use direct route between <text> and the RX channel.
ID:11932 Invalid XCVR_RECONFIG_GROUP .qsf setting "<text>" for "<text>" connected to merged Avalon Memory-Mapped interface shared by duplex channel.
ID:11933 Invalid XCVR_RECONFIG_GROUP .qsf setting "<text>" for merging Avalon Memory-Mapped interface of two RX-only channels "<text>" and "<text>".
ID:11934 Invalid XCVR_RECONFIG_GROUP .qsf setting "<text>" for Avalon Memory-Mapped interface merging of two transceiver (TX)-only channels "<text>" and "<text>".
ID:11935 Invalid XCVR_RECONFIG_GROUP .qsf setting "<text>" for Avalon Memory-Mapped interface merging of two Master CGBs "<text>" and "<text>".
ID:11936 Invalid XCVR_RECONFIG_GROUP .qsf setting "<text>" for Avalon Memory-Mapped interface merging of two LC PLLs "<text>" and "<text>".
ID:11937 Invalid XCVR_RECONFIG_GROUP .qsf setting "<text>" for Avalon Memory-Mapped interface merging of two CDR PLLs "<text>" and "<text>".
ID:11938 Invalid XCVR_RECONFIG_GROUP .qsf setting "<text>" for Avalon Memory-Mapped interface merging of "<text>" and "<text>".
ID:11939 Avalon Memory-Mapped interface for XCVR_RECONFIG_GROUP .qsf setting "<text>" is already merged to instance "<text>".
ID:11940 Avalon Memory-Mapped interface for XCVR_RECONFIG_GROUP .qsf setting "<text>" to instance "<text>" is invalid.
ID:11942 Module instance "<prim_inst>", which is a <prim_wys_type> primitive and belongs to an ALTLVDS interface and is driven by a clock pin, should not have the <loaden_port> port connected
ID:11943 Can't pack register node <name> into non-LAB location
ID:11944 operation_mode of atom "<name>" is invalid. Can't implement the selected mode with selected device.
ID:11947 Only one XCVR_RECONFIG_GROUP "<text>" .qsf setting for interface instance "<text>". Check .qsf setting's validity.
ID:11948 No netlist was specified to be exported for partition "<name>"
ID:11949 Module instance "<serdes_dpa_inst>", which is a <serdes_dpa_wys_type> primitive and belongs to an ALTLVDS interface, is configured as a receiver but has some transmitter-only ports connected.
ID:11950 Module instance "<serdes_dpa_inst>", which is a <serdes_dpa_wys_type> primitive and belongs to an ALTLVDS interface, is configured as a transmitter but has some receiver-only ports connected.
ID:11951 Module instance "<serdes_inst>", which is a <serdes_wys_type> primitive and belongs to an ALTLVDS interface, should have a bus width of exactly <word_width> connected to <parallel_data_port> port.
ID:11953 Quartus Prime software cannot find the selected device family.
ID:11957 <name> is currently not supported on this device and will be disabled
ID:11958 Can't open Technology Map Viewer -- atom netlist not available
ID:11959 Can't open Technology Map Viewer (Post-Mapping) -- post-mapping atom netlist not available
ID:11971 Cannot use ALTMULT_ADD wrapper: The ALTMULT_ADD megafunction is no longer supported for the <name> device family
ID:11972 Can't find node <name> in design file <name>
ID:11973 Can't display node -- node is encrypted. Displaying non-encrypted portions of RTL schematic.
ID:11974 You opened a Signal Tap file of which the content was automatically stripped by the Quartus Prime software after a compilation. The file name is restored back to its original name when you saved this file
ID:11975 The file with the same name is already open. Close the open file before opening this file
ID:11980 File conversion is not allowed for external active serial clock source when you enable the CvP and design security features
ID:11981 File conversion is not allowed for internal active serial clock source that is greater than 12.5 MHz when you enable the CvP and non-volatile design security features
ID:11983 Volatile key programming mode is selected. File conversion is allowed. However, file conversion is not allowed if non-volatile programming mode is selected
ID:11984 File conversion is not allowed for internal active serial clock source that is greater than 12.5MHz when CvP and non-volatile design security features are enabled.
ID:11985 File conversion is not allowed for external active serial clock source when CvP and design security features are enabled.
ID:11986 Volatile key programming mode is selected. However, when CvP and non-volatile design security features are enabled, file conversion is not allowed for internal active serial clock source that is greater than 12.5MHz
ID:11987 Current design is compliant. However, when CvP and non-volatile design security features are enabled, file conversion is not allowed for internal active serial clock source that is greater than 12.5MHz
ID:11988 Current design is compliant. File conversion is allowed. However, file conversion is not allowed for internal active serial clock source greater than 12.5 MHz when you enable the CvP and non-volatile design security features
ID:11989 I/O standard assignment '<name>' to pin <name> is not supported by the device
ID:11990 Pin <name> does not support current strength setting <name>. It must be <name>.
ID:11991 No IP component that requires an optional upgrade is found in the project
ID:11992 No IP components found in the project
ID:11994 State machine <state_machine> will not be constructed for viewing due to long processing time
ID:11995 Design cannot be fitted into HSSI quadrant.
ID:11996 Possible cause: <text>
ID:11997 Design has <text>, exceeds the capacity of targeted device, <number> channels.
ID:11998 Design has <text>, exceeds the capacity of targeted device, <number> PLLs.
ID:11999 Channel(s) under reference clocks: <text> are <text>, which exceeds the capacity for the targeted device's HSSI tile, <number> channels.
ID:12260 There are <number> CDR PLLs under reference clocks: <text> , which exceeds the capacity of <number> PLLs provided by the HSSI channel. Modify the design to ensure CDR PLLs driven by the reference clock set is less than the number of CDR PLLs supported for the target device.
ID:12261 Incremental compilation failed to move I/O assignment "<name>" for atom "<name>"
ID:12262 Starting Fitter periphery placement operations
ID:12268 Subpartition "<name>" is empty. Export will be performed without flattening child partitions
ID:12269 Merged HSSI Avalon Memory-Mapped interface instances "<text>" and "<text>" into single Avalon Memory-Mapped Interface.
ID:12270 Cannot generate a Partial Reconfiguration bitstream with the Compression option enabled.
ID:12271 Cannot generate a Partial Reconfiguration bitstream with the Compression option enabled.
ID:12272 Failed to reestablish connection to license server for feature <text>.
ID:12273 Cannot use port <name> and port <name> simultaneously
ID:12274 A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid and the Fitter must be restarted.
ID:12275 Unable to find any component. Please check the find option.
ID:12276 Finished searching document. Can't find search text.
ID:12283 Assignment <acf_name> on transceiver refclk clk buf/pin <atom_name> is not supported
ID:12284 Can't proceed with filter. Choose nodes in similar hierarchies level.
ID:12286 Netlist is corrupted. Fitter cannot find any valid nodes connected to Avalon Memory-Mapped instance: <name>
ID:12288 Fitter is ignoring the value of ROUTER_EFFORT_MULTIPLIER since that option is no longer supported.
ID:12290 Loading the periphery placement data.
ID:12291 Periphery placement data loaded: elapsed time is <time>
ID:12294 The revision name is not valid.
ID:12295 Periphery placement of all unplaced cells complete: elapsed time is <time>
ID:12296 Generated the <name> report: elapsed time is <time>
ID:12297 Cannot find any effective error for the specified region for device <number>
ID:12298 Device <number> - Cannot match error at Frame <name> Bit <name> and Type <name> with any injected error
ID:12299 Device <number> - Failed to <name> at Frame <name> Bit <name>
ID:12301 Specified frame, bit, or both are out of range. Valid frame is <name>. Valid bit is <name>
ID:12302 Ignored -post_fpp option. The Timing Analyzer does not allow timing analysis of the post-periphery placer netlist after you run the Fitter.
ID:12305 Can't specify a non-contiguous shape for Partial Reconfiguration region "<name>"
ID:12307 Filtering across ten or more hierarchy levels increases processing time. Do you want to continue?
ID:12309 Device <number> - Random Sequence Test is using <name> as sequence key
ID:12311 Hexadecimal (Intel-Format) File contains an unsupported record type at "<name>" line <number>. Saving the file will discard the unsupported record
ID:12312 Device <number> - Failed to read system error status
ID:12313 Device <number> - Detected system error while fault injecting frame <name> at bit <name> (index <number>)
ID:12314 Device <number> - Current IP does not support Random Sequence Test
ID:12315 Decompression feature is not supported in AS and FPP configuration scheme for device(s): <device name>. The decompression feature is disabled automatically
ID:12318 Failed to use the selected key programming file. Found device database mismatch between key programming file and the target device
ID:12319 Failed to use the selected key programming file. Missing key information to generate encrypted bitstream for Partial Reconfiguration design
ID:12320 SMH files specified are more than the specified SOF(s)
ID:12321 SMH index specified does not match any SOF(s) index
ID:12322 Transceiver PLL "<name>" has illegal data rate of <number> -- the maximum data rate possible when using the xN transmitter clock network to drive bonded transmitter channels cannot exceed <number>
ID:12323 Transceiver PLL "<name>" has illegal data rate of <number> -- the maximum data rate possible when using the xN transmitter clock network to drive non-bonded transmitter channels cannot exceed <number>
ID:12324 <name> index specified is duplicated
ID:12326 You are not logged in to the notification server or your session expired. Notifications are disabled. Login to the notification server to resume notifications.
ID:12331 Fault injection IP on device <number> is invalid
ID:12332 The Fitter normally places <name> later
ID:12333 PLL "<name>" drives a non-DPA LVDS interface on the top or bottom edge, but the PLL is not in LVDS compensation mode
ID:12334 PLL "<name>" drives a non-DPA LVDS interface on the left or right edge, but the PLL is not in direct compensation mode
ID:12336 Your username or password is incorrect. Verify your login information.
ID:12338 Error communicating with the notification server. Try again later.
ID:12339 Can't connect to the notification server. Check that your internet connection is working properly, and that your proxy settings and login information are correct. The Quartus Prime software does not support proxy auto-config (.PAC) files.
ID:12341 The <name> pin <name> has a <name> I/O standard, but the selected device does not support <name> pin operation with a <name> I/O standard.
ID:12342 Can't turn on open-drain option for differential I/O pin <name>
ID:12343 Avalon Memory-Mapped interfaces cannot be merged because Avalon Memory-Mapped Interface I_AVMMCLK port for channel <text> is <text> while Avalon Memory-Mapped Interface I_AVMMCLK port for PLL <text> is <text>
ID:12344 Reference clock: <text> are locked to pin <text>, which is not a legal HSSI reference clock pin location
ID:12349 Fitter was unable to route the <type (including space if not blank)>PLL feedback path for <name>
ID:12350 A process is in progress. Upgrade the IP components after the process completes
ID:12354 IP component "<file>" does not support IP component upgrade through command line
ID:12355 Current strength assignment '<name>' to pin <name> is not supported by the device. The name '<name>' is not a valid current strength name
ID:12356 OCT assignment '<name>' to pin <name> is not supported by the device. The name '<name>' is not a valid OCT name
ID:12359 No open project
ID:12360 Unable to find an active revision for the current project
ID:12362 <family name> devices are not supported in this Quartus Prime software edition. Use a Quartus Prime software edition that supports your device. Visit the <download center url> section of the Intel FPGA website for more information.
ID:12364 Assignment "<name>" contains invalid argument "<argument name>". Remove assignment from Quartus Prime Settings file.
ID:12367 RAM content is different from the mif. RAM: <name> MIF file: <name>
ID:12368 This design expects at least one ATX PLL to run between 7.05 to 7.5 Gbps. Please verify in the fitter report that the ATX PLLs intended to run between 7.05-7.5 Gbps are configured properly. If this is not the case, please edit the appropriate IP per Altera's guidance
ID:12381 Can't launch default web browser
ID:12382 Instantiation of "<name>" is invalid. UIB block is not supported in <name> device family.
ID:12387 Instantiation of "<name>" is invalid. FP_MAC block is not supported in the target device.
ID:12389 LVDS RX channel with DPA is not supported for data rate range from 1.001 Gbps to 1.249 Gbps in the current version of the Quartus Prime software
ID:12390 LVDS RX channel with DPA is not supported for data rate range from 1.250 Gbps to 1.299 Gbps for Arria V device in I3 speed grade in the current version of the Quartus Prime software
ID:12391 ATX PLL node "<name>" has a bandwidth setting that is not supported for the combination of reference clock and output clock frequency. Parameter: "<name>".
ID:12392 Feedback return path used by PLL(s) in location <name> is not of the recommended type
ID:12394 Cannot read file <file_name> <error_message>
ID:12395 Cannot read file <file_name> in Netlist Viewer File format
ID:12396 Found mismatched device name for input <name> files: <name> and <name>
ID:12397 Found mismatched programming data size for input <name> files
ID:12398 Failed to merge input <name> files
ID:12399 Total number of input files <name> specified after <name> in the argument is illegal
ID:12400 Total number of input files does not match with the specified argument <name>
ID:12401 The specified "<name>" DSP block WYSIWYG primitive does not support preadder subtraction with unsigned datain in <name> device family.
ID:12403 You must specify two or more data input files
ID:12406 Port <name> of I/O buffer "<name>" must be connected to a top-level pin
ID:12407 Output port <name> of I/O output buffer "<name>" has too many fan-outs. The I/O output buffer is allowed to drive only one top-level pin, but the I/O output buffer has <number> fan-outs
ID:12408 I/O input buffer "<name>" has too many "<name>" fan-outs. The maximum number allowed is <number>.
ID:12409 I/O Pad "<name>" must drive an input buffer primitive when the I/O pad atom is in input/bidirectional mode
ID:12410 I/O PAD "<name>" must be driven by an output buffer primitive when the I/O pad atom is in output/bidirectional mode
ID:12411 Input port <name> of I/O pad "<name>" must be driven by an output buffer primitive
ID:12412 I/O pad "<name>" must drive only one input buffer primitive
ID:12413 Output port "<name>" of PSEUDO_DIFF_OUT primitive "<name>" must drive only one OBUF primitive on the I port
ID:12414 <name> port of PSEUDO_DIFF_OUT primitive "<name>" is not connected to the "<name>" port of OBUF primitive <name>
ID:12415 PSEUDO_DIFF_OUT primitive "<name>" cannot drive true differential output buffer "<name>", where "<name>" port of output buffer is connected
ID:12416 Complement pin obtained for the bidirectional pin <name> is different via the input and output paths -- the configuration is invalid
ID:12417 Current Strength logic option is set to <text> for pin <name>, but setting is not supported by I/O standard <name>
ID:12418 Termination logic option is set to <name> for <name> pin <name>, but setting is not supported by I/O standard <name>
ID:12419 Slew Rate logic option is set to <number> for pin <name>, but setting is not supported by I/O standard <name>
ID:12420 Slew Rate logic option is set to <number> for pin <name>, but setting is not supported by Termination setting <name>
ID:12421 Slew Rate logic option is set to <number> for <name>, but setting is not supported by Current Strength setting <name>
ID:12422 Can't turn on open-drain option for differential I/O pin <name>
ID:12423 Enabling strict preservation for partition "<name>" because it is a child of strictly preserved partition "<name>"
ID:12425 Strictly preserved partition "<name>" must be assigned to a Logic Lock region
ID:12426 Region "<name>" containing strictly preserved partition has its size set to Auto, but this functionality is not supported for strict preservation flow
ID:12427 Region "<name>" containing strictly preserved partition has its state set to Floating, but this functionality is not supported for strict preservation flow
ID:12428 Region "<name>" containing strictly preserved partition must be set to Reserved
ID:12429 Region "<name>" containing strictly preserved logic "<name>" has nodes assigned to it that are not strictly preserved
ID:12430 Region "<name>" containing members of strictly preserved hierarchy "<name>" has nodes assigned to it that belong to the different strictly preserved hierarchy
ID:12431 Reported margins may differ from board margins due to delay chain step size granularity and operating conditions.
ID:12474 DSP "<name>" in 27x27 mode has mismatching Coefficient Select clock and/or enables
ID:12475 Illegal DSP atom <name> with unconnected inputs
ID:12476 Transceiver PLL "<name>" drives the xN clock network to bonded transmitter channels. The bonded span and/or data rate <number> exceeds the xN bonded mode beyond transmitter specification
ID:12477 Transceiver PLL "<name>" drives the xN clock network to non-bonded transmitter channels. The channel span and/or data rate <number> exceeds the xN non-bonded mode beyond transmitter specification
ID:12478 PLL "<name>" is used for LVDS RX channel with DPA, but the PLL is configured such that the DPA clock frequency may change dynamically. The dynamic frequency range for DPA is limited in the current device family. Refer to the family errata sheet for details.
ID:12479 LVDS RX channel in soft-CDR mode is not supported for data rate range from 0.841 Gbps to 1.219 Gbps. For more details, refer to the <family> errata sheet
ID:12481 Expected the PROJECT_SHOW_ENTITY_NAME assignment to be turned on for design with transceiver PHY IP, but the assignment is turned off
ID:12495 Only post-fit netlist with routing can be exported for strictly preserved partition: "<name>".
ID:12498 Child partition "<name>" has different strict preservation setting.
ID:12499 Input clock of PLL <name>, which drives at least one non-DPA mode SERDES, must be driven by a dedicated clock pin of the PLL.
ID:12500 Strictly preserved partition "<name>" must have Post-Fit netlist type
ID:12501 Fitter preservation level for strictly preserved partition "<name>" must be set to "Placement and Routing"
ID:12504 No debuggable memory interfaces were found in the I/O column interface: <io_col>
ID:12505 LVDS RX channel in DPA mode is only supported with rx_dpll_hold for data rate range from 0.841 Gbps to 1.219 Gbps. For more details, refer to the <family> errata sheet
ID:12508 The bit-string specified for pin <name> is "<text>" but it must be a binary string containing 0 and/or 1 and must be of length <number>.
ID:12509 Bit-string specified for pin <name> is "<text>", but it must be a binary string containing 0 and/or 1 and must not be all zeros
ID:12510 The drive strength assignment on pin <name> is incomplete. You must specify both pull-up and pull-down drive strength.
ID:12516 Starting periphery placement operations
ID:12517 Periphery placement operations ending: elapsed time is <time>
ID:12518 LVDS RX channel in DPA mode and soft-CDR mode is not supported for data rate range from 1.22 Gbps to 1.25 Gbps for I4 speed grade with the partial reconfiguration feature enabled. For more details, refer to the <family> errata sheet
ID:12519 PLL <text>'s output <text> are illegal. It is dropped by the Fitter.
ID:12520 Successfully set active interface for connection <connection> to <interface>.
ID:12521 Strict preservation of pin "<name>" failed because the specified partition does not exist: "<name>"
ID:12525 This signal is driven by core routing -- it may be moved during placement to reduce routing delays
ID:12528 Strictly preserved pin "<name>" connects to logic residing in a partition other than the one specified in the assignment.
ID:12529 Pin "<name>" has unspecified strict preservation setting but connects to a strictly preserved partition.
ID:12531 Strict preservation of pin "<name>" will be ignored because the specified partition "<name>" is not strictly preserved.
ID:12532 Programmable pre-emphasis option is set to <number> for pin <name>, but setting is not supported by I/O standard <name>
ID:12533 Programmable VOD option is set to <number> for pin <name>, but setting is not supported by I/O standard <name>
ID:12536 Can't reserve pin <name> -- pin name is an illegal or unsupported format
ID:12537 Ignored one or more illegal reserve pin AS_VREF keywords
ID:12538 RESERVE_PIN setting for pin <name> has an illegal value
ID:12539 Can't reserve pin <name> as a Signal Probe output pin -- device family <name> does not support Signal Probe compilation
ID:12540 Reserve pin assignment ignored because of existing pin with name "<name>"
ID:12541 Can't reserve pin "<name>" because its name already exists with a different direction
ID:12542 Can't reserve pin <name> because it has an illegal I/O standard assignment
ID:12543 Can't reserve pin <name> -- pin has a differential I/O standard assignment
ID:12544 Can't reserve pin <name> because it lacks a legal location assignment
ID:12545 The CRC emulation on "<name>" is only supported if compiling together with a companion "<name>" device
ID:12546 CRC block is not available in device
ID:12547 Real-time CRC must be enabled for CRC block
ID:12548 There are <number> pins driven by the <name> port of the <name> cyclical redundancy check (CRC) block. However, there is only one CRCERROR pin location in the selected device.
ID:12549 PR pins are not available on this device.
ID:12550 PR pins are enabled but no prblock wysiwyg found in the design. Partial Reconfiguration feature is not enabled.
ID:12551 The <type> port of the prblock wysiwyg is not connected.
ID:12552 PR pins are enabled, but prblock wysiwyg CORECTL port is connected to VCC which indicate Partial Reconfiguration with an internal host.
ID:12553 PR pins are disabled, but prblock wysiwyg CORECTL port is connected to GND which indicate Partial Reconfiguration with an external host through PR pins.
ID:12554 The prblock wysiwyg CORECTL port is not connected to VCC or GND.
ID:12555 The prblock wysiwyg CORECTL port is connected to user logic, but the EXTERNALREQUEST port is not connected.
ID:12556 There are <number> pins driven by the <name> port of the <name> Partial Reconfiguration (PR) block. However, there is only one dedicated pin can be connected to this port.
ID:12557 PR pins are enabled, but the prblock wysiwyg <type> port is not connected to PR pins on the device.
ID:12558 PR pins are enabled, but the prblock wysiwyg does not have the correct connections to PR pins on the device.
ID:12559 Can't reserve pin <name>: <text>
ID:12560 Arria V/Stratix V/Arria V GZ design used DPA feature and compiled before Quartus II 13.0sp1 is incompatible with current version. Please recompile design.
ID:12561 Pad <number> of non-differential I/O pin '<name>' in pin location <name> is too close to pad <number> of differential I/O pin '<name>' in pin location <name> -- pads must be separated based on Cyclone V differential pad placement rule in Cyclone V Pin Connection Guideline document. Please use the Pad Mapping file to debug.
ID:12562 Other invalid location for non-differential <name> pin: Pad <number>, Location <name>.
ID:12565 Can't specify Routing Region "Expanded" for region "<name>" because the region contains non-contiguous parts
ID:12566 Chainout port "<name>" for DSP block WYSIWYG primitive "<name>" is connected to two or more chainin pins of DSP "<name>"
ID:12569 Can't specify Routing Region "Expanded" for region "<name>" because the region has an ancestor region with that setting
ID:12570 Can't specify Routing Region "Expanded" for region "<name>" because the region has a descendant region with that setting
ID:12571 Can't specify that region "<name>" is a child of region "<name>" because this would make a region with Routing Region set to "Expanded" become a descendant of another such region
ID:12572 Can't specify Routing Region "Expanded" for region "<name>" because the region is floating
ID:12582 Input port <name> of "<name>" must not be connected.
ID:12584 This specific device does not support the enhanced DDR HIO. Parameter "<name>" of atom "<name>" must be set to FALSE.
ID:12587 Can't specify Routing Region "Off" for Partial Reconfiguration region "<name>". Using "Expanded" instead
ID:12596 Export of strictly preserved partition "<name>" failed because it has a strictly preserved parent partition.
ID:12603 Ports <name> and <name> of atom <name> must both be connected or disconnected
ID:12604 The <name> parameter of atom <name> must be set to <name> due to its connectivity
ID:12608 I/O pad "<name>" is in bidirectional mode, but its output buffer is configured as true differential
ID:12615 Input port <name> of atom node "<name>" and Input Port <name> of atom node "<name>" are expected to have the same source
ID:12617 Cannot place pin '<name>' in the following location(s):
ID:12618 <number> input pin(s) will use non-dedicated clock routing -- review the clock promotion messages above for details
ID:12619 Location <name> because the location is reserved by strictly preserved logic <name>.
ID:12620 Input port <name> of I/O output buffer "<name>" is not connected, but the atom is driving a bi-directional pin
ID:12623 DATA[0] dual-purpose pin not reserved
ID:12624 Design has remote update block "<name>", but the selected configuration scheme "<name>" does not support remote update
ID:12625 Pin <name> not reserved as output driving an unspecified signal for active serial memory interface (ASMI) block
ID:12626 Node name <name> causes a name conflict with a reserved programming pin name -- change the node name
ID:12627 Pin <name> is reserved at location <name>
ID:12628 Invalid Platform Designer system file -- "<name>"
ID:12629 This specific device does not support memory initialization or ROM for Internal Configuration mode. Remove memory initialization of atom "<name>".
ID:12630 There are CPRI 6G channels at the six pack <text>. Only three channels can be placed inside six pack.
ID:12633 Device chain in Fault Injection Debugger does not match physical device chain -- expected <number> device(s) but found <number> device(s)
ID:12634 Failed to program signature in device <number>.
ID:12639 Fault Injection IP not loaded
ID:12640 Routing Region "<name>" overlaps routing region "<name>". This overlap is not allowed because both regions constrain routing with the "Expanded" setting
ID:12658 On Chip Termination and current strength values can not be specified for pin <name> when bit-level custom current strength values are specified.
ID:12659 Persona file for partition "<name>" exported to "<name>".
ID:12660 Persona file for partition "<name>" imported to "<name>".
ID:12663 Persona file for partition "<name>": "<name>" does not exist.
ID:12664 Persona file for partition "<name>": "<name>" already exists.
ID:12666 Partition "<name>" can not be specified because all static partitions are stored in PERSONA archive of Top partition.
ID:12667 I/O standard <name> on output or bidirectional pin <name> is illegal -- I/O standard only allowed on input pins
ID:12668 I/O standard <name> on input or bidirectional pin <name> is illegal -- I/O standard only allowed on output pins
ID:12669 Enable Bus-Hold Circuitry and Weak Pull-Up Resistor logic options cannot both be enabled for <name> pin
ID:12670 Enable Bus-Hold Circuitry logic option and differential I/O standard cannot both be enabled for pin <name>
ID:12671 Enable Weak Pull-Up Resistor logic option and differential I/O standard cannot both be enabled for pin <name>
ID:12672 Pin <name> is using Slew Rate setting <number> and Termination setting <name>. Slew Rate setting is changed to the required maximum of <number>
ID:12673 Current Strength logic option is set to <text> for pin "<name>", but setting is not allowed with a Termination assignment
ID:12677 No exact pin location assignment(s) for <number> pins of <number> total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report
ID:12679 Floorplan has reconfigurable regions that share columns.
ID:12680 Floorplan has reconfigurable regions that share abutting columns.
ID:12683 Perform analysis and elaboration before opening the State Machine Viewer.
ID:12692 Cannot parse Routing Constraints File <name>, line <number>: the line does not represent a valid routing resource for a resource list.
ID:12695 Cannot process the netlist.
ID:12738 Device family <name> does not have <name> blocks
ID:12750 The currently selected device family does not support Rapid Recompile.
ID:12751 PLL <text> and master CGB <text> for HIP channels must share same Avalon Memory-Mapped interface.
ID:12752 Perform NLV Preprocess (quartus_npp) before opening the State Machine Viewer.
ID:12753 Perform Analysis and Elaboration before opening the State Machine Viewer.
ID:12755 Router found <number> routing resources listed in section "<name>" of a routing constraints file.
ID:12759 PLL <text> drives <number> transceiver channels, which exceeds x1 clock network capacity.
ID:12760 Channel <text> and channel <text> must be locked within the same six pack
ID:12762 The power supply pin <name> at pin location <name> of device <name> requires <name>. However, the same pin on the migration device <name> requires <name>
ID:12763 Region "<name>" containing strictly preserved partition has its size set to Auto, but this functionality is not supported for strict preservation flow
ID:12764 Region "<name>" containing strictly preserved partition has its state set to Floating, but this functionality is not supported for strict preservation flow
ID:12765 Strictly preserved partition "<name>" must have Post-Fit netlist type
ID:12766 Fitter preservation level for strictly preserved partition "<name>" must be set to "Placement and Routing"
ID:12767 The Strict Preservation is enabled for top partition, but assigning the top partition to a strictly preserved logic is not allowed
ID:12768 Cannot parse Routing Constraints File <name>, line <number>: the line refers to resource list "<name>", but this resource list does not exist and will be ignored.
ID:12770 Read System Error
ID:12771 Reset System
ID:12772 Device <number> - Detected system error
ID:12775 Bidirectional I/O "<name>" uses parallel termination, but the dynamic termination control is not connected
ID:12776 I/O "<name>" has the dynamic termination control connected, but does not use parallel termination
ID:12777 Output I/O "<name>" has dynamic termination control connected
ID:12779 Error detection CRC feature is disabled when using partial reconfiguration
ID:12780 Output buffer atom "<name>" has port "<name>" connected, but does not use calibrated on-chip termination
ID:12781 I/O "<name>" has a termination control block assignment, but does not use calibrated on-chip termination
ID:12782 I/O "<name>" has netlist connections to on-chip termination control block "<name>" but has an assignment associating it with control block "<name>"
ID:12783 I/O "<name>" has voltage "<name>" and impedance value "<name>".
ID:12784 On-chip termination control block "<name>" is associated with conflicting I/Os
ID:12785 Fitter finished merging On-chip termination (OCT) logic blocks
ID:12786 Removing unused on-chip termination logic block "<name>" from the netlist
ID:12787 RX channel <text> and TX channel <text> are locked to the same duplex channel. In order for both the RX and TX channel to use the same duplex channel, you must assign them to the same group so the Fitter merges them into a single Avalon Memory-Mapped interface. To assign both channels to a group, use the Transceiver Avalon Memory-Mapped Interface Group logic option.
ID:12788 Error detection CRC feature is disabled when using CvP
ID:12789 Real-time CRC ERROR_CHECK_FREQUENCY_DIVISOR value (<number>) in design does not match value (<number>) in the Quartus Prime Settings File
ID:12790 Can't use active serial memory interface block -- configuration scheme is not Active Serial
ID:12791 Active serial configuration mode is selected with the INIT_DONE pin disabled. Depending on the configuration setup and board design, the INIT_DONE pin may need to be enabled in the design. For more information, refer to the Intel FPGA Knowledge Database solution number rd05092012_239
ID:12792 Can't enable DCLK because the device initialization clock is in active serial configuration mode.
ID:12793 Rapid Recompile does not support certain project assignments or settings that have been added, modified, or deleted since the previous compilation
ID:12799 Rapid Recompile may ignore certain project assignments or settings that have been added, modified or deleted since the previous compile.
ID:12802 Found <number> <type> blocks in design -- only one <type> block is allowed
ID:12807 Routing resource "<name>" was listed in too many resource lists in an RCF file. Listings after <number> are ignored.
ID:12819 Rapid Recompile may ignore modifying, adding, or deleting SDC files.
ID:12821 Mac Block "<name>" is improperly configured. Parameter signed_mby must be set to 'false' when Mode is 18x18 Plus 36.
ID:12822 At least <number> PCS bonding channels (for example, <name>) are driven by feedback compensation PLL, which exceeds tile size 6
ID:12823 The Fitter is unable to place the periphery of the design. Add a location constraint for <number> PCS bonding channels (for example, <name>) and bonding PLL (for example, <name>) may allow fitter to find legal placement
ID:12828 RX PCS atom <name> must be in duplex mode when RX rate match FIFO is enabled.
ID:12829 Failed to merge HSSI Avalon Memory-Mapped interface instances "<text>" and "<text>" into single Avalon Memory-Mapped Interface.
ID:12830 The parameter "<parameter value>" of DSP block WYSIWYG primitive "<atom name>" must be set to "NONE" when port <port name> is a constant value or disconnected.
ID:12831 All pipeline register must share the same clock source for DSP block WYSIWYG primitive "<atom name>" and the input pipeline register must be enabled.
ID:12833 Found mismatched device name for PSM and SOF files. MSF: <name>, SOF: <name>
ID:12834 Transceiver PLL "<name>" drives the xN clock network to bonded transmitter channels. The bonded span or data rate <number> exceeds the xN bonded mode beyond transmitter specification
ID:12835 Transceiver PLL "<name>" has illegal data rate of <number> -- the maximum data rate when using the xN transmitter clock network to drive non-bonded transmitter channels cannot exceed <number>
ID:12836 Transceiver PLL "<name>" drives the xN clock network to non-bonded transmitter channels. The channel span or data rate <number> exceeds the xN non-bonded mode beyond the transmitter specification
ID:12841 <text> is placed on a location that does not support CPRI or deterministic latency
ID:12843 Assignment <name> of value "<name>" for atom "<name>" is invalid. Can't implement the selected setting with selected device.
ID:12844 Assignment <assignment name> with value <assignment value> was <modified/deleted/added> <extra info>.
ID:12845 SDC file was <modified/deleted/added>: <SDC file name and path>.
ID:12847 Failed to write Quartus Settings File (QSF)
ID:12848 "<name>" is locked to the right side of the device. There are no HSSI channels on the right side of the device.
ID:12850 ATX PLL "<name>", which uses GT clock output, can connect only two GT channels in the adjacent triplet. use the Main/Above/Below clocking architecture to connect up to 6 GT channels.
ID:12851 The currently selected flow does not support Rapid Recompile. Rapid Recompile was run with <flow description>.
ID:12852 Data integrity error is detected during JTAG communication. The Signal Tap result is not trustworthy. Please check the JTAG chain.
ID:12857 HIP reset pin "<name>" is locked to "<name>", which is illegal.
ID:12859 You must be registered and signed in to Intel FPGA Notification Center to receive compilation status notifications.
ID:12860 Can't place carry chain that starts with node "<name>"
ID:12861 Can't place combinational node "<name>" -- node appears in a carry chain
ID:12862 Can't place combinational node "<name>" and combinational node "<name>" in the same ALM -- nodes appear consecutively in a carry chain
ID:12863 Can't place combinational or register nodes in Adaptive Logic Module (ALM): <text>
ID:12864 Register node "<name>" assigned to location <name>
ID:12865 Combinational node "<name>" assigned to location <name>
ID:12866 MLAB node "<name>" assigned to location <name>
ID:12867 Can't place one or more nodes assigned to the Adaptive Logic Module (ALM) containing location <name>
ID:12868 Can't place nodes assigned to location <name> -- multiple nodes assigned to same location
ID:12869 Nodes in Partitions <name> and <name> have conflicting previous placement constraints to <name>
ID:12870 Found <number> location resource conflicts due to Partitions preserving their previous placements
ID:12871 Found <number> location resource conflicts due to user location assignments
ID:12872 Partial Reconfiguration status: Cannot access the Partial Reconfiguration IP in JTAG debug mode.
ID:12876 Transmit PLL "<name>" is connected to more than one Central CGB. It can only connect to one Central CGB.
ID:12877 Output port "<text>[<number>]" of "<text>" can connect to:
ID:12878 Port "<text>[<number>]" of "<text>".
ID:12879 Input port "<text>[<number>]" of "<text>" can connect to:
ID:12880 Port "<text>[<number>]" of "<text>".
ID:12881 Too many 2.5-V SE IO in bank <name> with LVDS TX pin <name>. Reduce the number of 2.5-V I/Os used and re-run the analysis again. Please refer to the guideline from the Knowledge Base solution ID: rd10102013_979 and ensure the total % of SSN for the following SE I/O pins does not exceed 100%.
ID:12882 HardCopy command "<name>" is not supported in this Quartus Prime version
ID:12883 Assignment <assignment name> with value <assignment value> is not supported with Rapid Recompile.
ID:12884 Intel FPGA IP Evaluation Mode specification file "<name>" specified a timeout value of <value> seconds that exceed the max value of <value> seconds.
ID:12885 The following assignments are not supported with Rapid Recompile. <extra info>
ID:12886 The following assignments are not supported with Rapid Recompile. <extra info>
ID:12887 Too many 2.5-V SE IO in bank <name> with LVDS RX pin <name>. Reduce the number of 2.5-V I/Os used and re-run the analysis again. Please refer to the guideline from the Knowledge Base solution ID: rd10102013_979 and ensure the total % of SSN for the following SE I/O pins does not exceed 100%.
ID:12888 Cross talk of LVDS Pin <name> from SE IO is too high. Reassign or move one or more of the following SE I/Os pins location and re-run the analysis again. Please refer to the guideline from the Knowledge Base solution ID: rd10102013_979 and ensure the total % of crosstalk for the following SE I/O pins does not exceed 100%.
ID:12890 The CGB parameter x1_div_m_sel is set to "<number>". When operating in external feedback mode, the divider value for the X1 high frequency PLL mux (x1_div_m_sel) must be set to 1
ID:12895 Partial Reconfiguration status: <text>
ID:12896 Partial Reconfiguration status: Cannot recognize Partial Reconfiguration IP in the device chain.
ID:12897 Partial Reconfiguration status: <text>
ID:12898 Performing Partial Reconfiguration at device index <number>
ID:12899 SE I/O <name> contributed to <name>% of the margin due to SSN
ID:12900 SE I/O <name> contributed to <name>% of margin due to crosstalk
ID:12902 Device <text>
ID:12903 Configuration voltage level '<name>' is not supported by the configuration scheme (<name>)
ID:12904 Configuration voltage level '<text>' is not compatible with the '<text>' configuration scheme
ID:12905 Configuration voltage level (<name>) cannot be enforced on the I/O bank <name> because the voltage level is not supported by the bank
ID:12906 Configuration voltage level is automatically enforced for the device family '<name>' with the configuration scheme '<name>'
ID:12908 Programming error
ID:12909 Cannot parse Routing Constraints File <name>, line <number>: the line refers to port "<name>", but this port does not exist.
ID:12910 The Quartus Prime software cannot launch the Device Installer for some Windows operating systems. You can launch the Device Installer directly from the Windows Start Menu.
ID:12913 "<name>" family is not supported in this Quartus Prime version
ID:12914 The file, <file name>, is not embedded into sof file as expected. Some tools, such as System Console, may not function fully.
ID:12918 I/O buffer "<name>" and I/O buffer "<name>" are terminated by the same OCT block but are in two different partitions
ID:12926 Set I/O standard of pin "<name>" to "<name>" to comply with pins driven by the corresponding OCT control block
ID:12927 I/O standard assignment '<name>' to pin <name> is not supported by the device. The name '<name>' is not a valid I/O standard name
ID:12928 Created on-chip termination (OCT) RZQ pin "<name>"
ID:12929 Cannot parse Routing Constraints File include directive "<name>" found in file <name>.
ID:12930 An EMIF PLL reference clock (<name>) is locked to a location (<name>) which is not a dedicated clock pin
ID:12934 Fitter was unable to place an EMIF/PHYLite system
ID:12935 Include directive "<name>" found in file <name> is at recursion depth <number>. It will not be parsed as it represents a possible "include" cycle.
ID:12936 DQS input (<name>) is locked to a non-DQS pin (<name>)
ID:12937 DQS x8/x9 input (<name>) is locked to a location (<name>) which is not a dedicated DQS x8/x9 pin
ID:12938 DQS x16/x18 input (<name>) is locked to a location (<name>) which is not a dedicated DQS x16/x18 pin
ID:12940 DQS x32/x36 input (<name>) is locked to a location (<name>) which is not a dedicated DQS x32/x36 pin
ID:12941 IOs associated with an io_12_lane atom are locked to locations that correspond to different lane blocks
ID:12943 io_12_lane atom: <name>
ID:12944 <name> is locked to <name> location which is associated with <name>
ID:12945 IOs related to an EMIF/PHYLite system are constrained to multiple IO columns
ID:12946 <name> is constrained to <name> (region: <name>)
ID:12947 Active Serial programming file <name> is either outdated or a examined file
ID:12948 Tap point directive <number> cannot be parsed because it too high. Only tap points <number> and lower are supported.
ID:12949 Configuration voltage level of <name> is enforced on the I/O bank <name>. The VCCIO of the I/O bank <name> is set to <name>.
ID:12956 There was a validation error
ID:12957 <msgs>
ID:12958 There was one or more missing <type> port-map(s)
ID:12959 Atom <Atom ID>, port <Port name>, offset <Bus offset>
ID:12960 User has specified Fast Fit which is not supported by the family. Instead Fitter is performing an Auto Fit compilation.
ID:12962 There was one or more missing attribute(s)
ID:12963 <Attribute type> attribute <Attribute name> on <BCM name> was not set
ID:12964 Device assignment AUTO is not supported with Rapid Recompile
ID:12968 IOs from two EMIF/PHYLite systems have been constrained to an IO bank (IOBANK_<name>), but the interfaces have different PLL configurations
ID:12969 Interfaces sharing an IO bank should use same PLL reference clock/reset signals and have identical output counter settings
ID:12970 PLLs with different configurations:
ID:12971 <name>
ID:12974 Input port "<name>[<number>]" of PHY Clock Buffer "<name>" can only be driven by output port "<name>[<number>]" of a PLL.
ID:12975 PHY Clock Buffer "<name>" is driven by multiple PLLs. Input clocks of a PHY Clock Buffer can only be driven by the same PLL.
ID:12976 Output port "<name>[<number>]" of PHY Clock Buffer "<name>" can only be connected to one of the valid ports listed below.
ID:12978 Can be connected to <name>
ID:12979 Bitstream signature generation does not support multiple SOF data items. No authentication report will be generated for configuration device file <name>
ID:12981 SMH and SOF file CRC of device <number> mismatch.
ID:12986 Bidirectional pin "<name>" is connected to PHY Clock Buffer but no DQ_GROUP assignment was found on the pin. DQ_GROUP assignment is required on DQ/DM pins.
ID:12987 Input port "<name>" of IO Clock Divider node "<name>" must be connected to output port "<name>" of a PHY Clock Buffer.
ID:12988 There were too many errors; A subset of error messages follows
ID:12997 EMIF/PHYLite systems belonging to different partitions have been constrained to the same IO column
ID:12998 EMIF/PHYLite IOs belonging to following <number> partitions have been constrained to the same column
ID:12999 Partition: <name>
ID:13000 Registers with preset signals will power-up high
ID:13001 NOT_GATE_PUSH_BACK-forbidden assignments are ignored
ID:13002 NOT_GATE_PUSH_BACK performed on <name>
ID:13003 DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
ID:13004 Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
ID:13005 Duplicate registers merged to single register
ID:13006 Reduced registers with stuck control signals
ID:13007 Reduced register "<name>" with stuck signal "<name>" to <name>
ID:13008 TRI or OPNDRN buffers permanently disabled
ID:13009 TRI or OPNDRN buffers permanently enabled
ID:13010 Node "<name>"
ID:13011 Bidirectional pin "<name>" feeds itself
ID:13012 Latch <name> has unsafe behavior
ID:13013 Ports <name> and <name> on the latch are fed by the same signal <name>
ID:13023 LCELL buffers have been ignored
ID:13024 Output pins are stuck at VCC or GND
ID:13025 Duplicate LATCH primitives merged into single LATCH primitive
ID:13026 Duplicate LATCH primitive "<name>" merged with LATCH primitive "<name>"
ID:13027 Removed fan-outs from the following always-disabled I/O buffers
ID:13028 Removed fan-out from the always-disabled I/O buffer "<name>" to the node "<name>"
ID:13029 Converted the fanout from the always-disabled tri-state buffer "<name>" to the node "<name>" to VCC
ID:13030 Reduced the following open-drain buffers that are fed by GND
ID:13031 Reduced fanout from the always-enabled open-drain buffer "<name>" to the output pin "<name>" to GND
ID:13032 The following tri-state nodes are fed by constants
ID:13033 The <name> "<name>" is fed by <name>
ID:13034 The following nodes have both tri-state and non-tri-state drivers
ID:13035 Inserted always-enabled tri-state buffer between "<name>" and its non-tri-state driver.
ID:13036 One or more bidirectional pins are fed by always-enabled (GND-fed) open-drain buffers
ID:13037 Fan-out of permanently enabled (GND-fed) open-drain buffer feeding bidirectional pin "<name>" is set to GND
ID:13038 Illegal configuration of the instance "<name>" of IO primitive ALT_IOBUF. Port "io" should be connected to a bidirectional pin, not to an output pin.
ID:13039 The following bidirectional pins have no drivers
ID:13040 bidirectional pin "<name>" has no driver
ID:13041 Illegal configuration of the I/O primitive instance "<name>"
ID:13042 Tri-state bus <name> is feeding itself
ID:13043 WYSIWYG bidirectional pin "<name>" feeds the pin "<name>" from a port other than padio
ID:13044 Always-enabled tri-state buffer(s) removed
ID:13045 Converted the fanout from the always-enabled tri-state buffer "<name>" to the node "<name>" into a wire
ID:13046 Tri-state node(s) do not directly drive top-level pin(s)
ID:13047 Converted the fan-out from the tri-state buffer "<name>" to the node "<name>" into an OR gate
ID:13048 Converted tri-state node <name> into a selector
ID:13049 Converted tri-state buffer "<name>" feeding internal logic into a wire
ID:13050 Open-drain buffer(s) that do not directly drive top-level pin(s) are removed
ID:13051 Converted the fanout from the open-drain buffer "<name>" to the node "<name>" into a wire
ID:13053 Tri-state bus "<name>" fed by inverted tri-state bus "<name>" but can be fed only by tri-state primitives
ID:13054 Design requires <number> channels in a triplet, but only <number> channels are allowed when there are GT channels
ID:13055 Channel <name> at location <text> (<text>) is a <text> channel
ID:13056 The clock source of a <lvds_clock_tree_wys_type> primitive, "<clock_source>", must exclusively drive <lvds_clock_tree_wys_type> primitives.
ID:13059 The DDIO_OUT WYSIWYG primitive "<name>" feeding the <name> "<name>" has multiple fan-outs
ID:13060 One or more bidirectional pins are fed by always enabled tri-state buffers
ID:13061 Fan-out of permanently enabled tri-state buffer feeding bidirectional pin "<name>" is moved to its source
ID:13062 Bidirectional pin "<name>" feeds bidirectional pin "<name>"
ID:13065 The bidirectional pin "<name>" is fed by multiple output buffers
ID:13066 Illegal directional connection from the <object> "<name>" to the <object> "<name>"
ID:13067 The "<name>" port of the instance <name> of the <name> megafunction variation has multiple fanouts - it can only have a single fanout.
ID:13068 The "oe" port of the I/O primitive <name> is not connected properly
ID:13069 The megafunction instance <name> feeds the I/O primitive <name> invertedly.
ID:13070 The ALT_BIDIR_DIFF or the ALT_BIDIR_BUF primitive instance <name> is not connected to the altddio_bidir megafunction
ID:13071 The ALT_BIDIR_DIFF or the ALT_BIDIR_BUF primitive instance <name> is used in an illegal configuration
ID:13072 The tri-state buffer "<name>" directly or indirectly feeds itself.
ID:13073 The tri-state buffer "<name>" feeding the pin "<name>" directly or indirectly feeds itself.
ID:13074 The open-drain buffer "<name>" directly or indirectly feeds itself.
ID:13075 The open-drain buffer "<name>" feeding the pin "<name>" directly or indirectly feeds itself.
ID:13076 The <name> "<name>" has multiple drivers.
ID:13077 The tri-state buffer "<name>" feeding the pin "<name>" directly or indirectly feeds its own output enable.
ID:13078 The tri-state buffer "<name>" directly or indirectly feeds its own output enable.
ID:13079 Changed operation mode of WYSIWYG I/O primitives to match their padio pin type
ID:13080 Changed operation mode of WYSIWYG I/O primitive "<name>" from type <type> to type <type> to match type of pin "<name>" connected to its padio port
ID:13081 The Fitter cannot route to <type>
ID:13082 Following WYSIWYG I/O primitives are not properly connected to top level pins
ID:13085 WYSIWYG I/O primitive "<name>" is in <name> mode, but it is connected to the pin "<name>" in <name> mode
ID:13086 Performing gate-level register retiming
ID:13087 Performing gate-level register retiming for hierarchy "<name>"
ID:13088 Performing gate-level register retiming for the top-level hierarchy
ID:13089 The Quartus Prime software applied gate-level register retiming to <number> clock domains
ID:13090 Gate-level register retiming applied to <number> clock domains for hierarchy "<name>"
ID:13091 Gate-level register retiming applied to <number> clock domains for the top-level hierarchy
ID:13092 The Quartus Prime software applied gate-level register retiming to clock "<clock name>": created <number> new registers, removed <number> registers, left <number> registers untouched
ID:13093 Not allowed to move <number> registers
ID:13094 Not allowed to move at least <number> registers because they are in a sequence of registers directly fed by input pins
ID:13095 Not allowed to move at least <number> registers because they feed output pins directly
ID:13096 Not allowed to move at least <number> registers because they are fed by input pins
ID:13097 Not allowed to move at least <number> registers because they feed output pins
ID:13098 Not allowed to move at least <number> registers because they are fed by registers in a different clock domain
ID:13099 Not allowed to move at least <number> registers because they feed registers in a different clock domain
ID:13100 Not allowed to move at least <number> registers because they feed clock or asynchronous control signals of other registers
ID:13101 Not allowed to move at least <number> registers due to user assignments
ID:13102 Not allowed to move at least <number> registers due to timing assignments
ID:13103 Not allowed to move at least <number> registers because they are connected to SERDES
ID:13104 EMIF/PHYLite systems sharing a PLL reference clock are constrained to multiple IO columns
ID:13106 I/O standard of RZQ pin "<name>" is set to "<name>" which is not compatible with the calibrated pins of the corresponding OCT control block. OCT control block is calibrating pins with I/O standard of "<name>"
ID:13107 Pins constrained to an IO column in region <name>
ID:13108 <name>
ID:13110 PLL reference clock is constrained to an IO bank outside the bank(s) used by EMIF/PHYLite system(s)
ID:13111 <name> is constrained to <location>
ID:13112 IO banks used by EMIF/PHYLite system(s): <name>
ID:13114 <text> is a GT channel, and is assigned to location <text>, which is a non-GT location. <text> are valid GT channel locations.
ID:13115 There are <number> GT channels in the design, but there are only <number> GT channels available in the selected part.
ID:13116 There are <number> GT channels in the design, but this part does not support GT channels..
ID:13117 Reference clock <text> is constrained to the right side of the device.. As a result, <text> has to be placed to right side of device, which has no GT location.
ID:13118 PCS bonding channels must be locked in ascending and continuous order. The following channels <text> use PCS bonding, but are not constrained in ascending order. Modify your location assignments in the Assignment Editor to lock the PCS channels in ascending and continuous order.
ID:13119 Channels <text> are driven by X1 clock network and need to be placed in the same six-pack due to user location constraints. However, only <number> of the six-pack channels are usable.
ID:13121 <name>
ID:13122 <name>
ID:13123 <name>
ID:13124 PCS bonded channels are driven by the following master CGBs, which are different type of PLLs (with/without feedback compensation):
ID:13133 Output port's "<text>[<number>]" node name is "<text>".
ID:13134 Input port's "<text>[<number>]" node name is "<text>".
ID:13135 Address/command pin (<name>) is constrained to an illegal location (PIN_<name>). The legal location for this pin is PIN_<name>
ID:13136 Address/command pins are constrained to multiple IO banks.
ID:13137 <name> is constrained to <name>
ID:13138 Please try constraining some of the following signals to pin locations or IO banks
ID:13139 <list of IOs>
ID:13140 There are <number> GT transceiver groups in the design but the device can only fit <number> GT groups.
ID:13143 The evaluation of TCL Script u2b2_tcl_script.tcl failed. <text>
ID:13144 There were too many <type> port mappings
ID:13145 Atom <Atom ID>, port <Port name>, offset <Bus offset> was mapped to
ID:13146 Port <Mapped port name>
ID:13149 EMIF/PHYLite systems sharing a PLL reference clock do not have identical <name> inputs for following io_aux atoms
ID:13150 <name>
ID:13151 There were conflicting drivers for the same <type> port
ID:13152 Port <Port> was driven by conflicting sources
ID:13153 Driver <Driving source name>
ID:13159 Cannot parse Routing Constraints File <name>, line <number>: the line does not represent a valid routing resource for a weights list.
ID:13163 Cannot parse Routing Constraints File <name>, line <number>: Node weight <number> was used, but node weights may only be in the range from <number> to <number>. The incorrect node weight will be ignored.
ID:13164 Cannot parse Routing Constraints File <name>, line <number>: Node weight <number> was used, but node weights may only used in a weights_list section. The incorrect node weight will be ignored.
ID:13166 <Node type> <Destination Node> is being clocked by <Clock Node>
ID:13173 <name> (<number> fanout) drives <string>, with the buffer placed at <string>
ID:13176 Port: <name> of HPS atom "<name>" must be connected to a top-level pin
ID:13177 Your design targets the device family "<name>". The specified family is not a valid device family, is not installed, or is not supported in this version of the Quartus Prime software. If you restored a project from an archived version, your project was successfully restored, but you still must specify or install a supported device family.
ID:13179 JTAG block <name> does not support input port <name>
ID:13180 Destination of port <name> in JTAG block <name> must be a pin
ID:13181 Source of port <name> in JTAG block <name> must be pin
ID:13182 The JTAG pin "<name>" is defined as virtual I/O pin
ID:13183 Can't place <name> pin <name> in dedicated location
ID:13184 Fitter is attempting to run in Rapid Recompile mode.
ID:13185 Rapid Recompile is attempting to preserve results from <number> out of <number> design partition(s):
ID:13186 Partition "<name>" -- Placement preservation requested is <name> percent.
ID:13187 Rapid Recompile has disengaged on <number> out of <number> design partition(s) prior to fitting:
ID:13188 Partition "<name>" -- <name>.
ID:13190 Rapid Recompile is not required for <number> out of <number> design partition(s):
ID:13191 Rapid Recompile is not required to preserve results for design partition "<name>" because of user-set partition settings
ID:13194 Invalid value for <low junction temperature, high junction temperature>. Valid values: <name>.
ID:13195 The reference strictly preserved region mask file "<name>" cannot be located. Region mask verification will be skipped for strictly preserved region <name>.
ID:13198 Your project was successfully restored, but the device information in the Flow Summary report cannot be updated until the design targets a supported device family.
ID:13199 EMIF/PHYLite systems have too many unique <clock/reset> connections
ID:13200 The following <number> atoms have unique <clock/reset> connections but the device can only support <number> distinct <clock/reset> connections
ID:13201 Atom <number>: <io_aux atom>
ID:13202 Signal <number>: <clock or reset signal>
ID:13205 Sample node name: <long name>
ID:13206 Generic PLL instance "<name>" is configured as a fractional PLL, but Generic PLLs do not support fractional frequency synthesis in "<family>". Please update the design by either changing the current PLL to support only integer frequency synthesis or replacing this instance with an explicitly generated fractional PLL.
ID:13207 The clock core fanout consists of <fanout size> node(s)
ID:13208 This core logic is driven by <clock source sizes> clock source(s)
ID:13210 Fitter failed while performing Rapid Recompile.
ID:13211 The pr_write_count parameter value is <number>
ID:13212 The PR bitstream framesize value is <number>
ID:13213 Using common directory <name>
ID:13214 Files to be archived don't share a common directory
ID:13215 Files to be archived don't share a common directory - creating an archive based on a virtual common directory
ID:13217 There are <number> HIPs in the design. But device can only fit <number> HIPs.
ID:13219 Skew computation may take a long time due to a large network of skew paths.
ID:13220 <name>
ID:13222 Input port <name> of "<name>" must be connected to outclk of PHYCLK buffer.
ID:13223 Verilog HDL or VHDL error: <text>
ID:13224 Verilog HDL or VHDL error at <location>: <text>
ID:13225 Can't open VHDL or Verilog HDL file "<name>"
ID:13226 Can't open encrypted VHDL or Verilog HDL file "<name>" -- current license file does not contain a valid license for encrypted file
ID:13227 Verilog HDL or VHDL warning: <text>
ID:13228 Verilog HDL or VHDL warning at <location>: <text>
ID:13229 Verilog HDL or VHDL information: <message description>
ID:13230 Verilog HDL or VHDL information at <location>: <text>
ID:13231 Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "<name>" into its bus
ID:13233 VHDL information: ignored user-defined design library "<name>"
ID:13234 Verilog HDL unsupported feature error at file "<name>" line (<number>): can't synthesize pull-up or pull-down primitive
ID:13235 Verilog HDL unsupported feature error at file "<name>" (line <number>): cannot synthesize MOS switch gate primitive
ID:13236 Verilog HDL unsupported feature error at file "<name>" (line <number>): can't synthesize tran, rtran, or tranif bidirectional pass gate primitive
ID:13237 Can't create symbol/include/instantiation/component file for module "<name>" with list of ports that includes part select(s), bit select(s), concatenation(s), or explicit port(s)
ID:13238 Can't create symbol/include/instantiation/component file for module "<name>" because port "<name>" has an unsupported type
ID:13239 VHDL warning at <location>: can't infer memory for variable '<name>' with attribute '<value>'.
ID:13240 Can't create symbol/include/instantiation/component file for entity "<name>" because port "<name>" are not currently supported by the Quartus Prime symbol/include/instantiation/component file generator
ID:13241 Verilog HDL or VHDL XML Interface error at <location>: port "<name>" has an unsupported type
ID:13242 Verilog HDL or VHDL XML Interface error at <location>: parameter or generic "<name>" has an unsupported type
ID:13243 Verilog HDL XML Interface error at <location>: list of ports for module "<name>" contains unsupported port expression(s)
ID:13245 SOPC Builder Annotation error at <text>: <text>
ID:13246 Can't recognize finite state machine "<name>" because it has a complex reset state
ID:13247 Ignored IP debug alias "<name>" due to name or index conflicts
ID:13248 Ignored <name> synthesis attribute for port "<name>" because the synthesis attribute's pin assignment list contains <number> assignment(s), which does not match port width of <number> bit(s)
ID:13249 Can't use "<name>" as a pragma trigger for a synthesis attribute or directive when running in <name> mode
ID:13250 Can't use synthesis directive or attribute "<name>" when running in <name> mode
ID:13251 Can't use Verilog-2001 attribute syntax for synthesis attributes such as "<name>" when running in Conformal LEC mode
ID:13252 Can't generate symbol/include/instantiation/component files for both "<name>" and "<name>" because they differ only in case; the symbol/include/instantiation/component file for "<name>" will overwrite the symbol/include/instantiation/component file for "<name>"
ID:13253 Invalid value "<name>" for synthesis attribute "<name>" at <location>
ID:13254 Unrecognized synthesis attribute "<name>" at <location>
ID:13255 The following parameters' default values are not included in the symbol/instantiation/component file created.
ID:13256 Can't create default value string in symbol/instantiation/component file for parameter "<name>" because its default value is not a literal.
ID:13257 Can't find standard library file "<filename>"
ID:13258 Invalid -hdl_version argument specified for <name>
ID:13259 Cannot create path: <name> for XML interface output
ID:13260 Module <name> has no parameters
ID:13261 Syntax error in HDL interface instance parameters near text <text>
ID:13262 HDL Instance Interface error: "<name>" is not a parameter or generic on the target entity
ID:13263 Can't elaborate Greybox netlist for module or entity "<name>" at <location> - Integrated Synthesis requires the actual module or entity
ID:13264 Can't resolve multiple constant drivers for net "<name>" at <location>
ID:13265 Constant driver at <location>
ID:13266 Net "<text>" at <location> is already driven by input port "<text>", and cannot be driven by another signal
ID:13267 The port was declared at <location>
ID:13268 Port "<name>" on instance "<name>" at <location> has multiple connections
ID:13279 Verilog HDL or VHDL information at <location>: object "<name>" declared but not used
ID:13280 Verilog HDL or VHDL warning at <location>: object "<name>" assigned a value but never read
ID:13281 Verilog HDL or VHDL warning at <location>: conditional expression evaluates to a constant
ID:13282 Verilog HDL or VHDL warning at <location>: combinational loop detected on net "<name>"
ID:13284 Verilog HDL or VHDL arithmetic warning at <location>: loss of carry in addition or borrow in subtraction
ID:13286 Verilog HDL or VHDL Synthesis Directive error at <location>: can't use message_on and message_off to disable or enable error message <number>
ID:13287 Verilog HDL or VHDL Synthesis Directive error at <location>: message-related synthesis directives are not allowed inside a scope
ID:13288 Verilog HDL or VHDL Synthesis Directive error at <location>: "<name>" is not a legal value for the message_level synthesis directive
ID:13289 Verilog HDL or VHDL warning at the <location>: index expression is not wide enough to address all of the elements in the array
ID:13290 Verilog HDL or VHDL error -- the message ID <id> was specified as both turned on and off in project settings.
ID:13291 Verilog HDL or VHDL error -- the message ID <id> is invalid.
ID:13292 Verilog HDL or VHDL error at <location>: the message ID <id> specified in the HDL source is invalid.
ID:13293 Verilog HDL or VHDL error at <location>: the message ID string <id> specified in the HDL source is not a valid number format.
ID:13295 Verilog HDL error at <location>: ports in concatenation have different directions
ID:13296 Verilog HDL unsupported feature error at <location>: Procedural Continuous Assignment to register is not supported
ID:13297 Verilog HDL error at <location>: expression cannot reference entire array "<name>"
ID:13298 Verilog HDL error at <location>: value cannot be assigned to constant
ID:13299 Verilog HDL error at <location>: generated variable "<name>" cannot have assignment
ID:13300 Verilog HDL error at <location>: indexed object "<name>" cannot have assigned value
ID:13301 Verilog HDL error at <location>: values cannot be assigned directly to all or part of array "<name>" - assignments must be made to individual elements only
ID:13302 Verilog HDL error at <location>: value must not be assigned to nonvariable "<name>"
ID:13303 Verilog HDL error at <location>: object "<name>" cannot have assigned value
ID:13304 Verilog HDL error at <location>: sliced object "<name>" cannot have assigned value
ID:13305 Verilog HDL error at <location>: can't find port "<name>"
ID:13306 Verilog HDL error at <location>: can't index into non-array type <name> for <name>
ID:13307 Verilog HDL File I/O error at <location>: can't open Verilog Design File "<name>"
ID:13308 Verilog HDL error at <location>: variable "<name>" cannot be part-selected because it is not declared as an array
ID:13309 Verilog HDL Compiler Directive error at <location>: text macro "<name>" is same as predefined text macro
ID:13310 Register "<name>" is converted into an equivalent circuit using register "<name>" and latch "<name>"
ID:13311 Verilog HDL Function Declaration error at <location>: Function Declaration cannot specify both range and type
ID:13312 Verilog HDL Compiler Directive error at <location>: predefined text macro "<name>" cannot be undefined
ID:13313 Verilog HDL Case Statement warning at <location>: case item expression never matches the case expression because it contains an 'x' or 'z' value
ID:13314 Verilog HDL unsupported feature error at <location>: Deassign Statement is not supported
ID:13315 Verilog HDL Case Statement error at <location>: cannot specify more than one default case item
ID:13316 Verilog HDL unsupported feature warning at <location>: Disable Statement is not supported, and is ignored in compilation
ID:13317 Verilog HDL User-Defined Primitive (UDP) Declaration error at <location>: rising or falling edge is not allowed in combinational UDP "<name>"
ID:13318 Verilog HDL Compiler Directive error at <location>: must use `ifdef directive with `else directive
ID:13319 Verilog HDL Compiler Directive error at <location>: must use `ifdef directive with `elsif directive
ID:13320 Verilog HDL User-Defined Primitive (UDP) Declaration warning at <location>: UDP table is empty
ID:13321 Verilog HDL Compiler Directive error at <location>: must use `ifdef directive with `endif directive
ID:13322 Verilog HDL Generate error at <location>: loop condition must be a constant expression
ID:13323 Verilog HDL Event Control error at <location>: Event Control must be inside of Always Construct or Initial Construct
ID:13324 Verilog HDL unsupported feature error at <location>: event triggers are not supported for synthesis
ID:13325 Verilog HDL User-Defined Primitive error at <location>: UDP port must be scalar
ID:13326 Verilog HDL Always Construct error at <location>: Force Statement is not supported for processing with Quartus Prime Integrated Synthesis
ID:13327 Verilog HDL Always Construct error at <location>: Forever Statement is not supported in Always Construct
ID:13328 Verilog HDL error at <location>: function "<name>" is used but is not declared
ID:13329 Verilog HDL Case Statement error at <location>: generated case expression is not constant
ID:13330 Verilog HDL Case Statement error: generated case item expression at <location> is not constant
ID:13331 Verilog HDL Conditional Statement error at <location>: generated if condition is not constant
ID:13332 Verilog HDL error at <location>: hierarchical name "<name>" cannot reference signal in another hierarchy
ID:13333 Verilog HDL syntax error at <location>: invalid character <character> in binary number <bin>.
ID:13334 Verilog HDL syntax error at <location>: invalid character <character> in decimal number <dec>.
ID:13335 Verilog HDL syntax error at <location>: invalid character <character> in octal number <oct>.
ID:13336 Verilog HDL syntax error at <location>: invalid character '<character>' in UDP table
ID:13337 Verilog HDL error at <location>: assignment to invalid expression
ID:13338 Verilog HDL syntax error at <location>: invalid character <character> hexadecimal number <hex>
ID:13339 Verilog HDL error at <location>: invalid operation on real number
ID:13340 Verilog HDL error at <location>: invalid bit-wise unary operation on real number
ID:13341 Verilog HDL error at <location>: invalid binary operation on integers
ID:13342 Verilog HDL error at <location>: invalid binary operation on real numbers
ID:13343 Verilog HDL error at <location>: ports are defined with expressions -- must use standard Verilog HDL statements to instantiate modules
ID:13344 Verilog HDL syntax warning at <location>: extra block comment delimiter characters /* within block comment
ID:13345 Verilog HDL Function Call error at <location>: incorrect number of arguments passed to function
ID:13346 Verilog HDL Task Enable Statement error at <location>: incorrect number of arguments for Task Enable Statement
ID:13347 Verilog HDL User-Defined Primitive (UDP) Declaration error at <location>: incorrect number of inputs for UDP table entry "<text>"
ID:13348 Verilog HDL Compiler Directive error at <location>: the number of actual arguments <value> differs from the number of formal arguments <value> for macro <string>
ID:13349 Verilog HDL User-Defined Primitive (UDP) Declaration error at <location>: incorrect output field length in UDP table "<name>"
ID:13350 Duplicate register "<name>" merged to single register "<name>"
ID:13351 Verilog HDL Compiler Directive error at <location>: incorrect use of predefined text macro "<name>" -- expected macro field "<text>"
ID:13352 Verilog HDL error at <location>: variable index to array "<name>" is not within range
ID:13353 Verilog HDL unsupported feature warning at <location>: Initial Construct is not supported and will be ignored
ID:13354 Verilog HDL User-Defined Primitive (UDP) Declaration error at <location>: UDPs cannot have inout ports
ID:13355 Verilog HDL Module Instantiation warning at <location>: instantiated undefined module "<name>"
ID:13356 Verilog HDL Loop error at <location>: loop must terminate within <number> iterations
ID:13357 Verilog HDL Compiler Directive error at <location>: missing arguments for text macro "<name>"
ID:13358 Verilog HDL Compiler Directive error at <location>: missing Compiler Directive
ID:13359 Verilog HDL User-Defined Primitive (UDP) Declaration error at <location>: UDP table entry "<text>" has no current state field
ID:13360 Duplicate register "<name>" merged to single register "<name>", power-up level changed
ID:13361 Verilog HDL error at <location>: variable "<name>" has mixed blocking and nonblocking Procedural Assignments -- must be all blocking or all nonblocking assignments
ID:13362 Verilog HDL Module Instantiation error at <location>: cannot override parameters -- module <name> does not expect any parameters
ID:13363 Verilog HDL error at <location>: <name> "<name>" ignored due to previous errors
ID:13364 Verilog HDL Gate Instantiation error at <location>: name-based port connection is not allowed in Gate Instantiation
ID:13365 Verilog HDL Macro Definition syntax error at <location>: invalid character in macro parameter near "<name>"
ID:13366 Verilog HDL Macro Definition error at <location>: invalid macro parameters near "<name>"
ID:13367 Verilog HDL Gate Instantiation error at <location>: gate requires at least one input and one output port
ID:13368 Verilog HDL Gate Instantiation error at <location>: gate requires <number> inputs and outputs
ID:13369 Verilog HDL Loop Statement error at <location>: loop with non-constant loop condition not supported for <loop type>
ID:13370 Verilog HDL Module Instantiation error at <location>: arrays of Module Instantiations are not supported
ID:13371 Verilog HDL Unsupported Feature error at <location>: bidirectional pass switch gate primitive "<name>" is not supported
ID:13372 Verilog HDL Event Control error at <location>: mixed single- and double-edge expressions are not supported
ID:13373 Verilog HDL Gate Instantiation error at <location>: multiple terminals on pull-up or pull-down sources are not supported
ID:13374 Verilog HDL error at <location>: must use only constant operands for this operator
ID:13376 Verilog HDL unsupported feature error at <location>: real numbers are not supported
ID:13377 Verilog HDL Function Declaration error at <location>: must not use output or inout ports in Verilog HDL functions
ID:13378 Verilog HDL unsupported feature warning at <location>: Parallel (Fork-Join) Block is not supported
ID:13379 Verilog HDL error at <location>: parameter "<name>" is not a formal parameter of instantiated module
ID:13380 Verilog HDL error at <location>: parameter "<name>" depends on an uninitialized variable
ID:13381 Verilog HDL error at <location>: part-select has negative or zero size, but must use one or more bits
ID:13382 Verilog HDL Expression error at <location>: invalid part select of unpacked array "<name>"
ID:13383 Verilog HDL Module Declaration error at <location>: port "<name>" is declared more than once
ID:13384 Verilog HDL Module Declaration error at <location>: explicit port identifier "<name>" cannot be used more than once
ID:13385 Verilog HDL Module Declaration warning at <location>: port "<name>" already exists in the list of ports
ID:13386 Verilog HDL Procedural Assignment error at <location>: object "<name>" on left-hand side of assignment must have a variable data type
ID:13387 Verilog HDL error at <location>: range index cannot be a real number
ID:13388 Verilog HDL error at <location>: range index cannot contain X or Z
ID:13389 Verilog HDL error at <location>: range index is not constant
ID:13390 Verilog HDL unsupported feature error at <location>: Release Statement not supported for processing with Quartus Prime Integrated Synthesis
ID:13391 Verilog HDL error at <location>: replication multiplier contains X
ID:13392 Verilog HDL error at <location>: replication multiplier is not constant
ID:13393 Verilog HDL error at <location>: replication multiplier must be positive
ID:13394 Verilog HDL error at <location>: identifier "<name>" cannot be used in expression
ID:13395 Verilog HDL User-Defined Primitive (UDP) Declaration error at <location>: sequential table entry "<text>" found in combinational table
ID:13396 Verilog HDL Declaration error at <location>: identifier "<name>" is already declared in the present scope
ID:13397 Verilog HDL Variable Declaration error at <location>: variable name "<name>" is already used
ID:13398 Verilog HDL Function Call or Function Declaration error at <location>: identifier "<name>" is not a function
ID:13399 Verilog HDL Generate Statement error at <location>: variable "<name>" is not declared as genvar
ID:13400 Verilog HDL error at <location>: identifier "<name>" is not a memory
ID:13401 Verilog HDL error at <location>: variable "<name>" is not an array of vectors
ID:13402 Verilog HDL Event Control error at <location>: name "<name>" is not an event
ID:13403 Verilog HDL Module Declaration error at <location>: port "<name>" is not declared as port
ID:13404 Verilog HDL error at <location>: "<name>" is not a task or void function
ID:13405 Verilog HDL error at <location>: "<name>" is not a task or block
ID:13406 Verilog HDL error at <location>: object "<name>" is not declared
ID:13407 Verilog HDL error at <location>: invalid name "<name>" used in expression
ID:13408 Verilog HDL error at <location>: array "<name>" should be indexed by <number> dimensions
ID:13409 Verilog HDL warning at <location>: the port and data declarations for array port "<name>" do not specify the same range for each dimension
ID:13410 Pin "<name>" is stuck at <value>
ID:13411 Verilog HDL syntax error at <location> near text <text>
ID:13412 Verilog HDL syntax error at <location> near end of file
ID:13413 Verilog HDL unsupported feature error at <location>: real variable data type values are not supported
ID:13414 Verilog HDL error at <location>: system call "<name>" must have exactly one argument
ID:13415 Verilog HDL Unsupported Feature error at <location>: system function "<name>" is not supported for synthesis
ID:13416 Verilog HDL warning at <location>: ignoring unsupported system task "<name>"
ID:13417 Verilog HDL unsupported feature warning at <location>: <name> ignored
ID:13418 Verilog HDL syntax error at <location>: table entry is missing colon ':' I/O separator : "<string>"
ID:13419 Verilog HDL error at <location>: Task Enable Statement must not be used outside sequential constructs
ID:13420 Verilog HDL error at <location>: task "<name>" is not declared
ID:13421 Verilog HDL unsupported feature warning at <location>: Module Item Declaration is ignored
ID:13422 Verilog HDL Module Instantiation error at <location>: too many ports used in Module Instantiation
ID:13423 Verilog HDL Compiler Directive error at <location>: too many arguments in text macro
ID:13424 Verilog HDL Module Instantiation error at <location>: too many parameter values for "<name>" instance of "<name>" module
ID:13425 Verilog HDL User-Defined Primitive (UDP) Declaration error at <location>: the first UDP port must be an output
ID:13426 Verilog HDL User-Defined Primitive (UDP) Declaration error at <location>: UDP must have exactly one output port
ID:13427 Verilog HDL Gate Instantiation error at <location>: unconnected terminal in instantiation of this gate
ID:13428 Verilog HDL syntax error at <location>: unexpected end of file in If Statement
ID:13429 Verilog HDL Net Declaration or Register Declaration error at <location>: vector of multibit values is not supported
ID:13430 Verilog HDL Net Declaration or Register Declaration error at <location>: array of vectors of multibit values is not supported
ID:13431 Verilog HDL unsupported feature error at <location>: references to named events are not supported for synthesis
ID:13432 Verilog HDL Compiler Directive warning at <location>: text macro "<name>" is undefined
ID:13433 Verilog HDL Defparam Statement error at <location>: value for parameter "<name>" must be constant expression
ID:13434 Verilog HDL unsupported feature warning at <location>: Wait Statement is not supported and is ignored
ID:13435 Verilog HDL unsupported feature warning at <location>: ignoring unsupported net type <name>
ID:13436 Verilog HDL Compiler Directive warning at <location>: ignoring invalid value "<name>" for unconnected_drive directive
ID:13437 Verilog HDL error at <location>: part-select direction is opposite from prefix index direction
ID:13438 Verilog HDL Case Statement warning at <location>: case item expression never matches the case expression
ID:13439 Verilog HDL Conditional Statement error at <location>: cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
ID:13440 Verilog HDL Module Instantiation error at <location>: ignoring trailing ordered association
ID:13441 Verilog HDL Declaration warning at <location>: vector has more than 2**<number> bits
ID:13442 Verilog HDL Declaration error at <location>: vector has more than 2**<number> bits
ID:13443 Verilog HDL Declaration warning at <location>: array has more than 2**<number> bits
ID:13444 Verilog HDL Declaration error at <location>: array has more than 2**<number> bits
ID:13445 Verilog HDL Module Declaration error at <location>: top module port "<name>" is not found in the port list
ID:13446 Verilog HDL error at <location>: can't resolve reference to object "<name>"
ID:13447 Verilog HDL Case Statement warning at <location>: honored full_case synthesis attribute - differences between design synthesis and simulation may occur
ID:13448 Verilog HDL Case Statement warning at <location>: honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur
ID:13449 Verilog HDL unsupported feature error at <location>: recursive Function Call in Function Declaration is not supported
ID:13450 Verilog HDL unsupported feature error at <location>: recursive Task Enable Statement in Task Declarations is not supported
ID:13451 Verilog HDL error at <location>: function or task "<text>" must have <number> arguments
ID:13452 Verilog HDL Module Instantiation error at <location>: <text> "<text>" has no parameter named "<text>"
ID:13453 Verilog HDL Module Instantiation error at <location>: module "<text>" "<text>" does not have <number> parameters
ID:13454 Verilog HDL syntax error at <location>: comment block must have beginning comment delimiter (slash and asterisk)
ID:13455 Verilog HDL warning at <location>: expression attempts to divide or modulo by zero. Treated expression value as Don't Care (X) during synthesis.
ID:13456 Verilog HDL Function Declaration error at <location>: function must have at least one input
ID:13457 Verilog HDL warning at <location>: Can't extract state machine for state register "<text>" because register is too small to store all possible states
ID:13458 Verilog HDL Continuous Assignment error at <location>: object "<text>" on left-hand side of assignment must have a net type
ID:13459 Verilog HDL error at <location>: ports in module "<text>" cannot be declared using both a formal port declaration list and internal port declarations
ID:13460 Verilog HDL Generate Statement error at <location>: generate loop cannot contain Function Declarations or Task Declarations
ID:13461 Verilog HDL Parameter Declaration warning at <location>: Parameter Declaration '<name>' in module '<name>' behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
ID:13462 Verilog HDL Compiler Directive error at <location>: nested 'ifdef or 'ifndef block exceeds nesting limit of <number>
ID:13463 Verilog HDL syntax error at <location>: experienced unexpected end-of-file -- translate_off synthesis directive "<name>" must have matching translate_on synthesis directive
ID:13464 Verilog HDL syntax error at <location>: experienced unexpected end-of-file while processing comment block -- comment block must have ending comment delimiter (asterisk and slash)
ID:13465 Verilog HDL Port Declaration warning at <location>: port declaration for "<name>" declares dimensions but the data type declaration does not
ID:13466 Verilog HDL Port Declaration warning at <location>: data type declaration for "<name>" declares dimensions but the port declaration declaration does not
ID:13467 Verilog HDL error at <location>: <name> "<name>" cannot be declared more than once
ID:13468 Verilog HDL Expression warning at <location>: literal value "<name>" truncated literal to match <number> bits
ID:13469 Verilog HDL assignment warning at <location>: truncated value with size <number> to match size of target (<number>)
ID:13470 Verilog HDL error at <location>: this block requires a name
ID:13471 Verilog HDL warning at <location>: value assigned to input "<name>"
ID:13473 Verilog HDL Defparam Statement error at <location>: Defparam Statement within generate scope cannot change parameter value outside generate scope or hierarchy instantiated within generate scope
ID:13474 Verilog HDL Defparam Statement error at <location>: parameter "<name>" cannot be assigned to its own value -- can't resolve self-referential loop
ID:13475 Verilog HDL Always Construct warning at <location>: variable "<name>" is read inside the Always Construct but isn't in the Always Construct's Event Control
ID:13476 Verilog HDL Event Control warning at <location>: posedge or negedge of vector "<name>" depends solely on its least-significant bit
ID:13477 Verilog HDL Implicit Net warning at <location>: created implicit net for "<name>"
ID:13478 Verilog HDL warning at <location>: can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead
ID:13479 Verilog Module Declaration warning at <location>: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "<name>"
ID:13480 Verilog HDL Always Construct error at <location>: event control cannot test for both positive and negative edges of variable "<name>"
ID:13481 Verilog HDL Always Construct warning at <location>: inferring latch(es) for variable "<name>", which holds its previous value in one or more paths through the always construct
ID:13482 Verilog HDL Function Declaration warning at <location>: function "<name>" may return a Don't Care value because its output register may not be assigned a value in every possible path through the function
ID:13483 Verilog HDL Function Declaration warning at <location>: variable "<name>" may have a Don't Care value because it may not be assigned a value in every possible path through the statements preceding its use
ID:13484 Verilog HDL error at <location>: non-constant index always falls outside the declared range [<number>:<number>] for dimension <number> of array "<name>"
ID:13485 Verilog Defparam Statement error at <location>: Quartus Prime Integrated Synthesis cannot resolve defparam identifier "<name>" to a parameter on a specific instance in the current module
ID:13486 Verilog HDL Unsupported Feature error at <location>: can't synthesize cross-hierarchy defparam "<name>" on instance "<name>"
ID:13487 Verilog HDL Module Instantiation error at <location>: Module Instance Parameter Value Assignment list cannot assign parameter values by both name and order
ID:13488 Verilog HDL Module Instantiation error at <location>: Module Instance Parameter Value Assignment list contains more than one assignment for parameter "<name>"
ID:13489 Verilog HDL unsupported feature error at <location>: unsupported use of both Defparam Statement(s) and an ordered Module Instance Parameter Value Assignment list to specify parameter values for instance "<name>"
ID:13490 Verilog HDL Declaration error at <location>: objects with <type name> type cannot be declared with a range
ID:13491 Verilog HDL Declaration error at <signed type>: objects with <type name> type cannot be declared as <location>
ID:13492 Verilog HDL error at <location>: index <number> cannot fall outside the declared range [<left bound>:<right bound>] for dimension <number> of array "<name>"
ID:13493 Verilog HDL Module Instantiation error at <location>: invalid connection to port "<port name>" in array of instances - the actual bit length (<number>) does not equal either the formal port width (<number>) or the product of the formal port width and the number of instances (<number>)
ID:13494 Verilog HDL Module Instantiation error at <location>: cannot elaborate array of instances because the declaration for the instantiated module has not been analyzed
ID:13495 Verilog HDL Module Instantiation error at <location>: cannot elaborate array of instances because the instances do not have a consistent width for port "<port name>"
ID:13496 Verilog HDL Module Instantiation error at <location>: port "<port name>" on instance "<instance name>" has width <number>, but the same port on prior instances in the array had width <number>
ID:13497 Verilog HDL error at <location>: exponentiation is not supported for specified operands, <additional details>
ID:13498 Verilog HDL error at <location>: unsized constants are not allowed in concatenations
ID:13499 Verilog HDL error at <location>: unsupported type for Verilog parameter <param_name>
ID:13500 Verilog HDL error at <location>: constant value overflow
ID:13501 Verilog HDL literal error at <location>: a sized number cannot have zero size
ID:13502 Verilog HDL Event Control warning at <location>: Event Control contains a complex event expression
ID:13503 Verilog HDL Event Control warning at <location>: event expression is a constant
ID:13504 Verilog HDL Event Control warning at <location>: event expression contains "|" or "||"
ID:13505 Verilog HDL Case Statement information at <location>: all case item expressions in this case statement are onehot
ID:13506 Verilog HDL Module Instantiation information at <location>: instance "<name>" connects port "<name>" to an empty expression
ID:13507 Verilog HDL Module Instantiation information at <location>: instance "<name>" connects port <number> to an empty expression
ID:13508 Verilog HDL Module Instantiation error at <location>: cannot connect instance ports both by order and by name
ID:13509 Verilog HDL information at <location>: always construct contains both blocking and non-blocking assignments
ID:13510 Verilog HDL conditional expression warning at <location>: expression is wider than one bit
ID:13511 Verilog HDL Case Statement warning at <location>: incomplete case statement has no default case item
ID:13512 Verilog HDL Case Statement warning at <location>: size of case item expression (<number>) exceeds the size of the case expression (<number>)
ID:13513 Verilog HDL Case Statement warning at <location>: case item expression covers a value already covered by a previous case item
ID:13514 Verilog HDL warning at <location>: extended using "x" or "z"
ID:13515 Verilog HDL macro warning at <location2>: overriding existing definition for macro "<name>", which was defined in "<filename>", line <location1>
ID:13516 Verilog HDL Module Instantiation warning at <location>: ignored dangling comma in List of Port Connections
ID:13517 Verilog HDL sensitivity list warning at <location>: sensitivity list contains multiple entries for "<name>"
ID:13518 Verilog HDL warning at <location>: the variable "<name>" should be initialized before being referenced
ID:13519 Verilog HDL Port Declaration error at <location>: <direction> port "<name>" cannot be declared with type "<type>"
ID:13520 Verilog HDL Port Declaration error at <location>: <direction> port(s) cannot be declared with type "<type>"
ID:13521 Verilog HDL Port Declaration error at <location>: cannot redeclare port "<name>" because it is already fully declared
ID:13522 Verilog HDL Declaration information at <location>: object "<name>" differs only in case from object "<name>" in the same scope
ID:13523 Verilog HDL port connection warning at <location>: formal port "<name>" with size <number> connected to expression with size <number>
ID:13524 Verilog HDL Module Instantiation warning at <location>: instance "<name>" does not specify a connection for port "<name>"
ID:13525 Verilog HDL Module Instantiation error at <location>: port "<name>" is not declared by module "<name>"
ID:13526 Verilog HDL Module Instantiation error at <location>: instance "<name>" specifies <number> actual port connections but module "<name>" only expects <number>
ID:13527 Verilog HDL Defparam error at <location>: can't override parameters on primitive instance "<name>"
ID:13528 Verilog HDL Primitive Instantiation error at <location>: primitive "<name>" has no named parameters
ID:13529 Verilog HDL Display System Task info at <location>: <text>
ID:13530 Verilog HDL Display System Task warning at <location>: <text>
ID:13531 Verilog HDL Display System Task at <location>: <text>
ID:13532 Verilog HDL Object Declaration error at <location>: can't declare implicit net "<name>" because the current value of 'default_nettype is "none"
ID:13533 Verilog HDL Port Connection error at <location>: output or inout port "<name>" must be connected to a structural net expression
ID:13534 Verilog HDL Assignment information at <location>: truncated unsized constant literal with size <number> to size <number> with no loss of information
ID:13535 Verilog HDL Expression error at <location>: indexed name does not fully index unpacked array "<number>"
ID:13536 Verilog HDL Expression error at <location>: indexed name specifies too many indices for array "<number>"
ID:13537 Verilog HDL Unsupported Feature error at <location>: Integrated Synthesis does not support <text>
ID:13538 Verilog HDL Casex/Casez warning at <location>: casex/casez item expression overlaps with a previous casex/casez item expression
ID:13539 Verilog HDL Case Statement warning at <location>: can't check case statement for completeness because the case expression has too many possible states
ID:13540 Verilog HDL warning at <location>: case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
ID:13541 Verilog HDL Declaration warning at <location>: "<name>" is Verilog-2001 keyword
ID:13542 Verilog HDL Declaration warning at <location>: "<name>" is SystemVerilog-2005 keyword
ID:13543 Verilog HDL Synthesis Attribute warning at <location>: ignoring full_case attribute on case statement with explicit default case item
ID:13544 Verilog HDL error at <location>: <string> is a SystemVerilog feature
ID:13545 Verilog HDL Instantiation warning at <location>: instance has no name
ID:13546 Verilog HDL Macro Definition syntax error: invalid character "<character>" in macro name "<name>"
ID:13547 Verilog HDL Macro Definition error: invalid macro parameters "<text>" for macro "<name>"
ID:13548 Verilog HDL Attribute warning at <location>: synthesis attribute "<name>" with value "<text>" has no object and is ignored
ID:13549 Verilog HDL macro warning at <location>: overriding existing definition for macro "<name>", which was defined in the Quartus Prime Settings File (.qsf) or on the command line
ID:13550 Verilog HDL Attribute warning at <location>: overriding existing value for attribute "<string>"
ID:13551 Verilog HDL error at <location>: value for <string> must be <string>
ID:13552 Verilog HDL error at <location>: "<string>" is not a "<string>"
ID:13553 Verilog HDL error at <location>: parameter "<name>" has no initial or actual value
ID:13554 Verilog HDL error at <location>: failed to elaborate task or function "<name>"
ID:13555 SystemVerilog RTL Coding error at <location>: always_latch construct does not infer latched logic
ID:13556 SystemVerilog RTL Coding error at <location>: always_comb construct does not infer purely combinational logic.
ID:13557 SystemVerilog RTL Coding error at <location>: always_comb or always_latch cannot have a sensitivity list.
ID:13558 SystemVerilog Declaration error at <location>: prefix for packed array type does not refer to a packable type
ID:13559 SystemVerilog Operator error at <location>: can't use operator "<name>" outside a procedural statement
ID:13560 SystemVerilog Type Name error at <location>: "<name>" is not a type
ID:13561 SystemVerilog Enumeration Type Declaration error at <location>: enumeration element range cannot contain negative numbers
ID:13562 SystemVerilog Enumeration Type Declaration error at <location>: can't assign encoded value with x or z to enumeration element "<name>" with a 2-state data type
ID:13563 SystemVerilog Enumeration Type Declaration error at <location>: unassigned enumeration element "<name>" cannot follow an enumeration element with an 'x' or 'z' assignment
ID:13564 SystemVerilog Enumeration Type Declaration error at <location>: can't encode value for enumeration element "<name>" because the enumeration base type does not have enough bits
ID:13565 SystemVerilog Enumeration Type Declaration error at <location>: encoded value for element "<name>" has width <number>, which does not match the width of the enumeration's base type (<number>)
ID:13566 SystemVerilog Enumeration Type Declaration error at <location>: encoded value for element "<name>" already assigned to element "<name>"
ID:13567 Verilog HDL Unsupported Feature error at <location>: support for multiple packed dimensions available only in SystemVerilog mode
ID:13568 SystemVerilog warning at <location>: unique case statement has overlapping case items
ID:13569 SystemVerilog error at <location>: can't connect expression with incompatible data type to formal "<name>"
ID:13570 SystemVerilog error at <location>: can't resolve aggregate expression in connection to port <number> on instance "<string>" because the instance has no module binding
ID:13571 SystemVerilog error at <location>: can't declare packed array dimension with a single-valued range
ID:13572 SystemVerilog typedef error at <location>: reference to type "<string>" creates a recursive type
ID:13573 SystemVerilog Array Querying warning at <location>: argument to <name> does not denote an object or type with array dimensions, returning 'x
ID:13574 SystemVerilog Array Querying warning at <location>: second argument (<number>) to <name> is not a valid dimension for object or type with <number> dimensions, returning 'x
ID:13575 SystemVerilog Unsupported Feature error at <location>: Integrated Synthesis does not support <text>
ID:13576 SystemVerilog Type Cast error at <location>: the source and destination types must have the same number of bits when casting to or from an unpacked bitstream type
ID:13577 SystemVerilog error at <location>: closing label "<string>" must match the original label "<string>"
ID:13578 SystemVerilog Enumeration Type Declaration error at <location>: enum range must contain only positive integral numbers
ID:13579 SystemVerilog warning at <location>: unique or priority keyword makes case statement complete
ID:13580 SystemVerilog error at <location>: can't resolve implicit port connection(s) to instance "<name>" without a module declaration or an extern equivalent
ID:13581 SystemVerilog error at <location>: can't implicitly connect port "<name>" on instance "<name>" of module "<name>" - <text>
ID:13582 SystemVerilog error at <location>: instance "<name>" has more than one .* connection
ID:13583 SystemVerilog error at <location>: actual modport specification "<string>" does not match formal modport specification "<string>"
ID:13584 SystemVerilog error at <location>: can't bind output argument "<name>" to an empty expression
ID:13585 SystemVerilog error at <location>: argument "<name>" is already bound
ID:13586 SystemVerilog error at <location>: positional arguments cannot follow named arguments
ID:13587 SystemVerilog error at <location>: <name> type and <name> type do not match - <string>
ID:13588 SystemVerilog error at <location>: <name> type and <name> type are not equivalent - <string>
ID:13589 SystemVerilog error at <location>: <name> type cannot be assigned to <name> type - <string>
ID:13590 SystemVerilog error at <location>: const variable "<name>" has no value
ID:13591 SystemVerilog warning at <location>: index undefined for "<name>"
ID:13592 The interface array port '<name>' of size <number> at location <location> must be passed an identical array and not one of size <number>
ID:13593 SystemVerilog warning at <location>: index <number> falls outside the bounds [<number>:<number>] of array "<name>"
ID:13594 SystemVerilog error at <location>: named block "<name>" cannot have a statement label or vice-versa.
ID:13595 SystemVerilog error at <location>: can't pass values between formal ref "<name>" and actual with non-equivalent types
ID:13596 SystemVerilog error at <location>: invalid assignment pattern - <string>
ID:13597 SystemVerilog error at <location>: invalid assignment - <string>
ID:13598 SystemVerilog error at <location>: const-qualified variable "<name>" is not legal in constant expressions
ID:13599 SystemVerilog $fatal at <name>: <text>
ID:13600 SystemVerilog $error at <location>: <string>
ID:13601 SystemVerilog $warning at <name>: <text>
ID:13602 SystemVerilog critical $warning at <name>: <text>
ID:13603 SystemVerilog $info at <name>: <text>
ID:13604 VHDL Subtype Indication error at <location>: access type or file type cannot have resolution function
ID:13605 VHDL error at <location>: access type <name> is assigned to object, but type of elements in access type must be the same as <name> type of object
ID:13606 VHDL Aggregate Error at <location>: array aggregate already has a choice in this range
ID:13607 VHDL Subprogram Specification error at <location>: subprogram "<name>" is a homograph of another object in the same declarative region
ID:13608 VHDL Alias Declaration error at <location>: alias target name does not have the same number of elements as the alias subtype
ID:13609 VHDL error at <location>: allocators are not synthesizable
ID:13610 VHDL Selected Name error at <location>: name matches more than one object in a context that requires a unique match
ID:13611 VHDL error at <location>: architecture "<name>" does not exist for entity "<name>"
ID:13612 VHDL Type Declaration error at <location>: element type for array type cannot be unconstrained
ID:13613 VHDL Indexed Name error at <location>: array type "<name>" expects <number> index arguments
ID:13614 VHDL warning at <location>: ignored assignment of value to null range
ID:13615 VHDL error at <location>: attempt to divide by 0
ID:13616 VHDL attribute error at <location>: return value type of attribute "<name>" must match object type <type>
ID:13617 VHDL attribute error at <location>: predefined attribute "<name>" must have an argument
ID:13618 VHDL attribute error at <location>: predefined attribute "<name>" cannot be used in an expression
ID:13619 VHDL attribute error at <location>: predefined attribute "<name>" must have an integer argument
ID:13620 VHDL attribute error at <location>: attribute "<name>" that is used for multiple bits is not synthesizable
ID:13621 VHDL error at <location>: value cannot be assigned to constant "<name>"
ID:13622 VHDL Assignment error at <location>: cannot assign value to non-object "<name>"
ID:13623 VHDL Type Conversion error at <location>: cannot convert type "<name>" to type "<name>"
ID:13624 VHDL error at <location>: can't execute unsupported pragma for function "<name>"
ID:13625 VHDL Component Declaration error at <location>: port "<name>" is listed for component, but not listed for entity "<name>"
ID:13626 VHDL Interface Declaration error in <location>: interface object "<name>" of mode out cannot be read. Change object mode to buffer.
ID:13627 VHDL error at <location>: can't synthesize magnitude comparator for user-defined types
ID:13628 VHDL Case Statement error at <location>: elements of array type Case Statement expression has <type> type, but must have character type
ID:13629 VHDL Case Statement error at <location>: Case Statement expression has <type> type, but must have discrete type or one-dimensional array type with character type elements
ID:13630 VHDL Case Statement error at <location>: <string> statement choices must cover all possible values of expression. 'Others' clause is needed.
ID:13631 VHDL Case Statement error at <location>: Case Statement cannot be used as Register Inference because Case Statement cannot contain an edge-triggered or event-triggered condition for the statement's execution. Use If Statement.
ID:13632 VHDL syntax error at <location>: object with <type> type cannot contain character '<character>'
ID:13633 VHDL error at <location>: character '<character>' used but not declared for type "<name>"
ID:13634 VHDL warning at <location>: ignored choice that is null range
ID:13635 VHDL aggregate error at <location>: choice must be constant
ID:13636 VHDL aggregate error at <location>: choice must be discrete range
ID:13637 VHDL aggregate error at <location>: choice "<name>" must belong to index subtype of array aggregate
ID:13638 VHDL error at <location>: choice "<text>" overlaps with a previous choice
ID:13639 VHDL aggregate error at <location>: choice "<text>" must belong to range "<text>" for the index subtype of array aggregate
ID:13640 VHDL Expression error at <location>: expression "<text>" is expected to have <number> elements.
ID:13641 VHDL Choice warning at <location>: ignored choice containing meta-value "<text>"
ID:13642 VHDL Choice warning at <location>: ignored choice containing meta-value
ID:13643 VHDL error at <location>: can't determine definition of operator "<name>" -- found <number> possible definitions
ID:13644 VHDL error at <location>: digit '<character>' in based literal "<text>" must be smaller than base
ID:13645 VHDL Exit Statement, Next Statement, or Return Statement error at <location>: edge-triggered or event-triggered condition cannot be used in Exit Statement, Next Statement, or Return Statement
ID:13646 VHDL error at <location>: record type "<name>" does not contain element "<name>"
ID:13647 VHDL error at <location>: entity aspect "<name>" does not denote an entity or configuration
ID:13648 VHDL error at <location>: entity must be in current project's work library
ID:13649 VHDL error at <location>: entity "<name>" is used but not declared
ID:13650 VHDL Attribute warning in <location>: ENUM_ENCODING or SYN_ENCODING attribute for enumeration type "<name>" does not specify a valid encoding for every enumeration literal -- ignored all encodings
ID:13651 VHDL Attribute warning at <location>: encodings in ENUM_ENCODING or SYN_ENCODING attribute must have the same length
ID:13652 VHDL Enumeration Type Declaration error at <location>: enumeration type "<name>" already contains enumeration literal "<name>"
ID:13653 VHDL error at <location>: exit must be used inside a loop
ID:13654 VHDL error at <location>: value must be constant integer
ID:13655 VHDL error at <location>: exponentiation with negative exponent must be used only for real type objects
ID:13656 VHDL error at <location>: integer literal cannot have negative exponent
ID:13657 VHDL expression error at <location>: expression has <number> elements, but must have <number> elements
ID:13658 VHDL error at <location>: formal port or parameter "<name>" must have actual or default value
ID:13659 VHDL error at <location>: formal parameter "<name>" is already associated
ID:13660 VHDL type mismatch error at <location>: type of formal parameter "<name>" does not match <type> type of value
ID:13661 VHDL Association List error at <location>: formal "<name>" does not exist
ID:13662 VHDL warning at <location>: ignored VHDL standard library NOW function, which is not supported for synthesis
ID:13663 VHDL Subprogram Body error at <location>: function "<name>" does not always return a value
ID:13664 VHDL type mismatch error at <location>: function "<name>" does not accept type <type>
ID:13665 VHDL Generate Statement error at <location>: condition must be constant
ID:13666 VHDL Default Binding error at <location>: component generic "<name>" does not exist on entity "<name>"
ID:13667 VHDL warning at <location>: ignored unknown or unsupported pragma "<name>"
ID:13668 VHDL Block Configuration error at <location>: invalid block specification name
ID:13669 VHDL Type Declaration error at <location>: invalid constrained element in unconstrained array declaration
ID:13670 VHDL error at <location>: invalid formal parameter
ID:13671 VHDL error at <location>: invalid function call in assignment
ID:13672 VHDL error at <location>: invalid <> in expression
ID:13673 VHDL error at <location>: invalid named association in array index
ID:13674 VHDL error at <location>: invalid named association in index constraint
ID:13675 VHDL error at <location>: invalid named association in type conversion
ID:13676 VHDL Selected Name error at <location>: prefix does not denote an object that declares a named scope
ID:13677 VHDL error at <location>: invalid name on sensitivity list
ID:13678 VHDL error at <location>: invalid range constraint in expression
ID:13679 VHDL error at <location>: invalid range in expression
ID:13680 VHDL Assignment error at <location>: name cannot be assigned a value
ID:13681 VHDL error at <location>: item cannot be assigned value
ID:13682 VHDL Type Declaration error at <location>: constrained array type contains unconstrained element type, but must contain constrained element type
ID:13683 VHDL error at <location>: unit name is invalid
ID:13684 VHDL error at <location>: attribute "<name>" cannot be used in constraint
ID:13685 VHDL error at <location>: subtype indication cannot contain <>
ID:13686 VHDL error at <location>: incorrect number of elements in target aggregate
ID:13687 VHDL error at <location>: invalid index constraint in expression
ID:13688 VHDL error at <location>: index constraint (<range>) is not compatible with range (<range>) of "<name>"
ID:13689 VHDL error at <location>: <type> type is used but not declared as an array type
ID:13690 VHDL Type Mismatch error at <location>: indexed name returns a value whose type does not match "<type>", the type of the target expression
ID:13691 VHDL error at <location>: index of object of array type <type> must have <number> dimensions
ID:13692 VHDL error at <location>: object cannot be indexed because it has <type> type rather than array type
ID:13693 VHDL assignment error at <location>: index <number> is outside the range (<range>) of object "<name>"
ID:13694 VHDL error at <location>: index value <number> is out of range (<range>)
ID:13695 VHDL error at <location>: non-constant index is always outside the range (<range>) of object "<name>"
ID:13696 VHDL Loop Statement error at <location>: infinite loops are not supported for synthesis
ID:13697 VHDL Type Declaration error at <location>: array type has index range of <type> type, but must have index range of discrete type
ID:13698 VHDL Constant Declaration error at <location>: initial value for constant must be a constant
ID:13699 VHDL Signal Declaration warning at <location>: ignored default value for the signal
ID:13700 VHDL Variable Declaration warning at <location>: ignored initial value expression for the variable
ID:13701 VHDL Block Specification error at <location>: cannot find "<name>"
ID:13702 VHDL error at <location>: left bound of slice is outside its index type range
ID:13703 VHDL error at <location>: left bound of range must be a constant
ID:13704 VHDL Conditional Signal Assignment error at <location>: conditional waveforms must have same number of elements
ID:13705 VHDL syntax error at <location>: name used in construct must match previously specified name "<name>"
ID:13706 VHDL Event Expression error at <location>: can't form clock edge from S'EVENT by combining it with an expression that depends on a signal besides S
ID:13707 VHDL Process Statement error at <location>: Process Statement must contain only one Wait Statement
ID:13708 VHDL error at <location>: can't determine type of object at or near bit string literal "<text>" -- found <number> possible types
ID:13709 VHDL error at <location>: can't determine type of object at or near character '<character>' -- found <number> possible types
ID:13711 VHDL attribute error at <location>: object with attribute "<name>" must have correct number of dimensions
ID:13712 VHDL error at <location>: can't determine object and type associated with selected name near text "<text>" -- found <number> possible objects and types
ID:13713 VHDL error at <location>: can't determine object and type associated with indexed name or signature name near text "<text>" -- found <number> possible objects and types
ID:13714 VHDL error at <location>: can't determine type of object at or near identifier "<name>" -- found <number> possible types
ID:13715 VHDL attribute error at <location>: object with attribute "<name>" must have scalar or array type
ID:13716 VHDL error at <location>: signature profile used for attribute, entity, or alias near "<text>" must match expected parameter or result type <type>
ID:13717 VHDL error at <location>: can't determine type of object at or near string "<text>" -- found <number> possible types
ID:13718 VHDL Type Conversion error at <location>: converted type of object near text or symbol "<text>" must match <type> type of target object
ID:13719 VHDL Type Conversion error at <location>: Type Conversion near text or symbol "<text>" must have one argument
ID:13720 VHDL Type Conversion error at <location>: can't determine type of object or expression near text or symbol "<text>"
ID:13721 VHDL Next Statement error at <location>: Next Statement must be inside Loop Statement
ID:13722 VHDL error at <location>: elements in exponent operations must be constant
ID:13723 VHDL Unsupported Feature error at <location>: cannot synthesize non-constant real object or value "<name>"
ID:13724 VHDL unsupported feature error at <location>: nonobject aliases are not supported
ID:13725 VHDL attribute error at <location>: predefined attribute "<name>" is not supported
ID:13726 VHDL Association List error at <location>: unconstrained formal ports can only be associated in whole
ID:13727 VHDL Entity Declaration error at <location>: ports must be constrained
ID:13728 VHDL error at <location>: real type objects cannot be used in operations
ID:13729 VHDL expression error at <location>: <type> operator cannot be used for integer values
ID:13730 VHDL expression error at <location>: <type> operator cannot be used for real values
ID:13731 VHDL expression error at <location>: <text> operator cannot be used for non-constant values
ID:13732 VHDL error at <location>: operator "<name>" cannot be used for value
ID:13733 VHDL Case Statement or Selected Signal Assignment error at <location>: OTHERS choice must be last choice in Case Statement or Selected Signal Assignment
ID:13734 VHDL Case Statement information at <location>: OTHERS choice is never selected
ID:13735 VHDL aggregate error at <location>: OTHERS choice must be last choice in aggregate, and must contain only the OTHERS keyword
ID:13736 VHDL aggregate error at <location>: OTHERS choice used in aggregate for unconstrained record or array type is not supported
ID:13737 VHDL aggregate error at <location>: target aggregate for Variable Assignment Statement cannot contain OTHERS choice
ID:13738 VHDL Case Statement or Selected Signal Assignment error at <location>: OTHERS choice must contain only the OTHERS keyword
ID:13741 VHDL package error at <location>: package "<name>" is used but not declared
ID:13742 VHDL Type Declaration error at <location>: range constraint bounds for physical type must have integer type
ID:13743 VHDL Type Declaration error at <location>: unit used in secondary unit declaration must be a physical type
ID:13744 VHDL Type Declaration error at <location>: value for physical type must have an integer or real type
ID:13745 VHDL Association List error at <location>: positional associations must be listed before named associations
ID:13746 VHDL attribute error at <location>: prefix of 'LENGTH attribute must be an object of array type or an array subtype
ID:13747 VHDL Component Configuration error at <location>: component "<name>" must be associated only to design entities in Binding Indication
ID:13748 VHDL Process Statement error at <location>: Process Statement cannot contain both a sensitivity list and a Wait Statement
ID:13749 VHDL Process Statement error at <location>: Process Statement must contain either a sensitivity list or a Wait Statement
ID:13750 VHDL warning at <location>: ignored choice with null range bounds
ID:13751 VHDL Subtype Declaration error at <location>: subtype range must belong to range for <type> type
ID:13752 VHDL Subtype or Type Declaration warning at <location>: subtype or type has null range
ID:13753 VHDL Type Declaration error at <location>: record element cannot have an unconstrained array type
ID:13754 VHDL error at <location>: record type <type> is used but not declared
ID:13755 VHDL attribute error at <location>: result of attribute "<name>" is out of range for type <type>
ID:13756 VHDL Return Statement error at <location>: Return Statement for function in Subprogram Declaration must have expression
ID:13757 VHDL Return Statement error at <location>: Return Statement for procedure in Subprogram Declaration cannot have expression
ID:13758 VHDL Return Statement error at <location>: Return Statement must be in Subprogram Declaration
ID:13759 VHDL error at <location>: right bound of slice is outside its index type range
ID:13760 VHDL syntax error at <location>: right bound of range must be a constant
ID:13761 VHDL Component Configuration error at <location>: component "<name>" has already been bound to a design entity
ID:13762 VHDL Subtype Declaration error at <location>: subtype for constrained <type> type cannot have range
ID:13763 VHDL Subtype or Type Declaration error at <location>: bounds in range must both have integer type or floating point value type
ID:13764 VHDL Block Configuration error at <location>: Block Configuration cannot have range or index because block "<name>" does not have range
ID:13765 VHDL attribute error at <location>: user-defined attribute "<name>" used for, but not associated with, object "<name>"
ID:13766 VHDL Component Configuration error at <location>: component instance "<name>" does not instantiate component "<name>"
ID:13767 VHDL error at <location>: second actual parameter of function "<name>" must be constant
ID:13768 VHDL Unsupported Feature error at <location>: can't declare signals with unconstrained scalar or array type
ID:13769 VHDL error at <location>: name "<name>" cannot be used because it is already used for a previously declared item
ID:13770 VHDL Block Configuration error at <location>: block "<name>" is configured but not defined
ID:13771 VHDL Component Configuration or Component Instantiation Statement error at <location>: component "<name>" is used but not declared
ID:13772 VHDL Block Configuration or Component Configuration error at <location>: component instance or block "<name>" is used but not defined
ID:13773 VHDL error at <location>: name "<name>" used at end of construct must match name specified at beginning of construct
ID:13774 VHDL Exit Statement or Next Statement error at <location>: loop name "<name>" is used in Exit Statement or Next Statement, but not specified in Loop Statement
ID:13775 VHDL attribute error at <location>: attribute "<name>" is used but not declared
ID:13776 VHDL error at <location>: entity "<name>" is used in Architecture Body, Configuration Specification, or Component Configuration, but is not defined
ID:13777 VHDL attribute error at <location>: name "<name>" was used but not declared as an object
ID:13778 VHDL package error at <location>: package "<name>" is used but not declared
ID:13779 VHDL error at <location>: resolution function "<name>" is used but not declared
ID:13780 VHDL error at <location>: type of identifier "<name>" does not agree with its usage as "<name>" type
ID:13781 VHDL error at <location>: name "<name>" must represent signal
ID:13782 VHDL error at <location>: item "<name>" cannot be used as subprogram
ID:13783 VHDL error at <location>: <name> type is used but not declared
ID:13784 VHDL Resolution Function error at <location>: return value or input parameter elements of Resolution Function "<name>" have <type> type, but must have same type as resolved signal
ID:13785 VHDL Use Clause error at <location>: design library "<name>" does not contain primary unit "<name>"
ID:13786 VHDL error at <location>: object "<name>" is used but not declared
ID:13787 VHDL error at <location>: "<name>" is not synthesizable since "<name>" does not hold its value under NOT(clock-edge) condition
ID:13788 VHDL error at <location>: range direction of object slice must be same as range direction of object
ID:13789 VHDL error at <location>: range direction of object slice must be same as range direction of object
ID:13790 VHDL error at <location>: slice of object cannot be specified for object that has an array type of more than one dimension
ID:13791 VHDL aggregate error at <location>: aggregate for array type or record type object must cover all elements of object
ID:13792 VHDL Default Binding Indication error at <location>: actual generic <name> in Generic Map Aspect must have same type as formal generic with same name in entity "<name>"
ID:13793 VHDL Default Binding Indication error at <location>: formal generic "<name>" in named Association List in Generic Map Aspect must have corresponding formal generic in entity "<name>"
ID:13794 VHDL warning at <location>: ignored pragma "<name>" for constant net
ID:13795 VHDL Component Configuration warning at <location>: treated component "<name>" as black box because Binding Indication associated component to design entity that is not in any defined library
ID:13796 VHDL Process Statement warning at <location>: signal "<name>" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
ID:13797 VHDL Function Call or Procedure Call Statement error at <location>: calls to function or procedure "<name>" caused stack overflow, limit of <number> has exceeded
ID:13798 VHDL Selected Signal Assignment warning at <location>: Selected Signal Assignment choices do not cover all possible values of expression
ID:13799 VHDL Subprogram Declaration error at <location>: declaration of function or procedure "<name>" must have corresponding Subprogram Body
ID:13800 VHDL Alias Declaration error at <location>: subtype of alias "<name>" for object must have same bounds and direction as object subtype
ID:13801 VHDL Case Statement warning at <location>: subtype of expression is not locally static
ID:13802 VHDL error at <location>: all elements of record type object cannot be accessed with suffix .all
ID:13803 HDL info at <location>: see declaration for object "<name>"
ID:13804 HDL warning at <location>: see declaration for object "<name>"
ID:13805 HDL error at <location>: see declaration for object "<name>"
ID:13806 VHDL syntax error at <location> near text <text>
ID:13807 VHDL warning at <location>: ignored synthesis attribute "<name>" because number of bits in <type> type does not match number of enumeration values in Type Declaration
ID:13808 VHDL Signal Assignment Statement warning at <location>: ignored all but the first waveform in Signal Assignment Statement
ID:13809 VHDL error at <location>: allocator with NEW keyword used for <type> type, but must be used for access type
ID:13810 VHDL error at <location>: slice that is assigned to target slice has <number> elements, but must have same number of elements as target slice (<number>)
ID:13811 VHDL error at <location>: NOT unary operator cannot be applied to enumeration value "<text>" for enumeration type <type> because value contains non-bit elements
ID:13812 VHDL error at <location>: can't access enumeration literal to the left of enumeration literal "<name>" in enumeration type <name>
ID:13813 VHDL error at <location>: can't access enumeration literal to the right of enumeration literal "<name>" in enumeration type <name>
ID:13814 VHDL error at <location>: discrete range has <type> type, but must have discrete type
ID:13815 VHDL Qualified Expression error at <location>: <type> type specified in Qualified Expression must match <type> type that is implied for expression by context
ID:13816 VHDL type mismatch at <location>: object(s) associated with operator "<name>" must have <type> type
ID:13817 VHDL aggregate error at <location>: aggregate contains one value for two or more elements, but elements must have same type
ID:13818 VHDL aggregate error at <location>: can't determine type of aggregate -- found <number> possible types
ID:13819 VHDL type mismatch error at <location>: <type> type does not match string literal
ID:13820 VHDL type mismatch error at <location>: type <type> used with bit string literal must be BIT type
ID:13821 VHDL type mismatch error at <location>: <type> type does not match integer literal
ID:13822 VHDL type mismatch error at <location>: <type> type does not match real literal
ID:13823 VHDL Type or Variable Declaration error at <location>: bounds of type or variable range must have same type
ID:13824 VHDL Conditional Signal Assignment error at <location>: waveform that contains UNAFFECTED keyword cannot contain any waveform elements
ID:13825 VHDL expression error at <location>: operands for operator "<text>" must have equal length
ID:13826 VHDL Syntax error at <location>: experienced unexpected end-of-file
ID:13827 Ignored construct <name> at <location> due to previous errors
ID:13828 VHDL warning at <location>: used 'X' for unrecognized character '<character>' in enumerated type
ID:13829 VHDL warning at <location>: Exemplar attribute or directive <name> is not supported in Quartus Prime software version 2.1 and earlier -- only translate_off and translate_on are supported
ID:13830 VHDL Signal Assignment Statement error at <location>: Signal Assignment Statement must use <= to assign value to signal "<name>"
ID:13831 VHDL Variable Assignment Statement error at <location>: Variable Assignment Statement must use := to assign value to variable "<name>"
ID:13832 VHDL error at <location>: value "<text>" is outside the target constraint range (<text>)
ID:13833 VHDL error at <location>: variable must be constrained
ID:13834 VHDL Variable Declaration error at <location>: variable declared in subprogram or process cannot be a shared variable
ID:13835 VHDL Variable Declaration error at <location>: variable declared outside subprogram or process must be a shared variable
ID:13836 VHDL Subprogram Body error at <location>: Subprogram Body cannot contain Wait Statement
ID:13837 VHDL Wait Statement error at <location>: Wait Statement must contain condition clause with UNTIL keyword
ID:13838 VHDL Wait Statement error at <location>: condition clause uses 'EVENT predefined attribute to wait on an arbitrary signal event -- Wait Statement must test for signal edge
ID:13839 VHDL Loop Statement error at <location>: WHILE iteration scheme condition cannot contain signals, non-constant loop limit of <number> exceeded
ID:13840 VHDL Loop Statement error at <location>: loop must terminate within <number> iterations
ID:13841 VHDL Signal Assignment Statement error at <location>: guarded Signal Assignment Statement must be in guarded Block Statement
ID:13842 VHDL information at <location>: object "<name>" is never used
ID:13843 VHDL information at <location>: object "<name>" is never assigned
ID:13844 VHDL Signal Declaration warning at <location>: used explicit default value for signal "<name>" because signal was never assigned a value
ID:13845 VHDL Signal Declaration warning at <location>: used implicit default value for signal "<name>" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
ID:13847 VHDL Variable Declaration warning at <location>: used default initial value for variable "<name>" because variable was never assigned a value or an initial value expression. Use of default initial value may introduce unintended design optimizations.
ID:13848 VHDL Assertion Statement at <location>: assertion is false - report <text> (NOTE)
ID:13849 VHDL Assertion Statement at <location>: assertion is false - report <text> (WARNING)
ID:13850 VHDL Assertion Statement at <location>: assertion is false - report <text> (FAILURE or ERROR)
ID:13851 VHDL Constant Declaration error at <location>: constant "<name>" must have initial value
ID:13852 VHDL Subprogram Body error at <location>: Subprogram Body cannot contain Signal Declaration
ID:13853 VHDL Subprogram Declaration error at <location>: mode for formal parameter of function cannot be <name>
ID:13854 VHDL Subprogram Declaration error at <location>: mode for formal parameter cannot be <name>
ID:13855 VHDL Subprogram Declaration error at <location>: object class for formal parameter of function cannot be <name>
ID:13856 VHDL Subprogram Declaration error at <location>: object class for formal parameter cannot be <name>
ID:13857 VHDL Function Call or Procedure Call Statement error at <location>: call to function or procedure "<name>" must specify exactly <number> actual parameter(s)
ID:13858 VHDL expression error at <location>: invalid <text> in expression
ID:13859 VHDL attribute error at <location>: Attribute Specification cannot contain both ALL or OTHERS keyword and list of entities
ID:13860 VHDL Exit Statement error at <location>: exit must be inside loop "<name>"
ID:13861 VHDL Next Statement error at <location>: next must be inside loop "<name>"
ID:13862 VHDL error at <location>: generic "<name>" cannot be used in its own interface list
ID:13863 VHDL Function Call or Component Instantiation error at <location>: recursive function or recursive design entity "<name>" is not supported
ID:13864 VHDL error at <location>: cannot associate formal port "<name>" of mode "<text>" with an expression
ID:13865 VHDL Subprogram Call error at <location>: actual "<name>" for formal parameter "<name>" must be a "<object class or type>"
ID:13866 VHDL attribute error at <location>: predefined attribute "<name>" cannot be used in an expression
ID:13867 VHDL attribute error at <location>: predefined attribute "<name>" cannot be used in Signal Assignment Statement or Variable Assignment Statement
ID:13868 VHDL Attribute error at <location>: predefined attribute "<name>" does not denote a range
ID:13869 VHDL Binding Indication error at <location>: design entity "<name>" does not contain generic "<name>" specified in associated component
ID:13870 VHDL Binding Indication error at <location>: design entity "<name>" does not contain port "<name>" specified in associated component
ID:13871 VHDL Block Configuration error at <location>: OPEN keyword cannot be used as index
ID:13872 VHDL error at <location>: can't read or update value of interface object "<name>" of mode LINKAGE
ID:13873 VHDL error at <location>: can't write to interface object "<name>" of mode IN
ID:13874 VHDL Aggregate error at <location>: OTHERS choice in record aggregate must specify at least one element
ID:13875 VHDL Constant Declaration error at <location>: constant cannot be file type or access type
ID:13876 VHDL Interface Declaration error at <location>: constant "<name>" must be of mode IN in Interface Declaration
ID:13877 VHDL Component Instantiation Statement error at <location>: argument for conversion function cannot be OPEN keyword
ID:13878 VHDL Component Instantiation Statement error at <location>: conversion function for formal parameter must contain only one argument
ID:13879 VHDL Binding Indication error at <location>: generic "<name>" in design entity does not have <type> type that is specified for the same generic in the associated component
ID:13880 VHDL Binding Indication error at <location>: port "<name>" in design entity does not have <type> type that is specified for the same generic in the associated component
ID:13881 VHDL Interface Declaration error at <location>: subtype indication of formal <name> in Interface File Declaration must denote file subtype
ID:13882 VHDL error at <location>: actual port "<name>" of mode "<text>" cannot be associated with formal port "<name>" of mode "<text>"
ID:13883 VHDL Interface Declaration error at <location>: constant or signal "<name>" in Interface Constant or Signal Declaration cannot be subtype <type> of file type or access type
ID:13884 VHDL Signal Declaration error at <location>: guarded signal with scalar type must be a resolved signal or a subelement of a resolved signal
ID:13885 VHDL Unsupported Feature error at <location>: incremental binding indications are not supported
ID:13886 VHDL Association List error at <location>: formal <name> of mode IN cannot be a Type Conversion or Function Call in named Association List
ID:13887 VHDL Interface Declaration error at <location>: interface object "<text>" of mode LINKAGE cannot have default expression
ID:13888 VHDL Interface Declaration error at <location>: Interface File Declaration cannot contain mode or default expression
ID:13889 VHDL Block Configuration error at <location>: block "<name>" is configured more than once
ID:13890 VHDL Component Instantiation Statement error at <location>: argument for conversion function cannot contain a formal parameter
ID:13891 VHDL Association List error at <location>: actual associated with formal <name> of mode OUT or BUFFER cannot be in the form of a type conversion
ID:13892 VHDL Association List error at <location>: formal <name> that is associated individually cannot be associated with actual of OPEN
ID:13893 VHDL Generic Map Aspect error at <location>: too many actuals for block "<name>" with only <number> formals
ID:13894 VHDL Port Map Aspect error at <location>: too many actuals for block "<name>" with only <number> formals
ID:13895 VHDL Signal Declaration error at <location>: signal cannot have file type or access type
ID:13896 VHDL error at <location>: item "<name>" must be a correctly specified range
ID:13897 VHDL error at <location>: construct <name> is used but not defined as a record element
ID:13898 VHDL Variable Assignment Statement error at <location>: target object "<name>" must be variable or aggregate
ID:13899 VHDL Selected Name error at <location>: object "<name>" isn't declared in scope "<name>" or library name "<name>" collides with an object name in the design.
ID:13900 VHDL error at <location>: <BUS or REGISTER> signal kind must be in Signal Declaration or Interface Signal Declaration
ID:13901 VHDL Interface Declaration error at <location>: formal <signal> parameter "<name>" in Interface Signal Declaration cannot have default expression
ID:13902 VHDL Interface List error at <location>: identifier "<name>" must be a <constant or signal>
ID:13903 VHDL Interface Declaration error at <location>: formal variable parameter "<name>" of mode "<text>" in Interface Variable Declaration cannot have default expression
ID:13904 VHDL error at <location>: can't update value of interface object "<name>" of mode IN
ID:13905 VHDL error at <location>: can't read value of interface object "<name>" of mode OUT
ID:13906 VHDL Variable Declaration error at <location>: Variable Declaration cannot have a file subtype indication
ID:13907 VHDL Generic Map Aspect error at <location>: formal generic "<name>" in named Association List must have corresponding generic in block "<name>"
ID:13908 VHDL Generic Map Aspect error at <location>: positional Association List contains <number> actual generics for block "<name>", but block has <number> formal generics
ID:13909 VHDL Generic Map Aspect error at <location>: ignored invalid actual generic literal value "<name>" that is associated with formal generic "<name>"
ID:13910 VHDL Aggregate error at <location>: record aggregate "<name>" contains <number> record elements, but must contain the same number of elements as the record type
ID:13911 VHDL Aggregate error at <location>: record aggregate must assign values to every element of record type <name>
ID:13912 VHDL Aggregate error at <location>: choice is not element of record type "<name>"
ID:13913 VHDL Component Instantiation Statement error at <location>: value for generic "<name>" must be a constant
ID:13914 VHDL error at <location>: another match is here
ID:13915 VHDL attribute error at <location>: attribute "<name>" must target block label or architecture
ID:13916 VHDL attribute error at <location>: attribute "<name>" already specified for "<name>"
ID:13917 VHDL attribute error at <location>: Attribute Specification contains invalid name
ID:13918 VHDL syntax error at <location>: experienced unexpected end-of-file -- translate_off synthesis directive "<name>" must have matching translate_on synthesis directive
ID:13919 VHDL attribute error at <location>: prefix for "<name>" attribute must denote a scalar type
ID:13920 VHDL synthesis attribute or directive warning at <location>: ignored synthesis attribute or directive "<name>" because it is not applied to function
ID:13921 VHDL synthesis attribute or directive warning at <location>: ignored synthesis attribute or directive "<name>" because it is applied to object of <name> type
ID:13922 VHDL synthesis attribute or directive warning at <location>: ignored synthesis attribute or directive "<name>" because it does not have only one argument
ID:13923 VHDL synthesis attribute or directive warning at <location>: ignored synthesis attribute or directive "<name>" because it does not have only two arguments
ID:13924 VHDL synthesis attribute or directive warning at <location>: ignored synthesis attribute or directive "<name>" applied to function "<name>"
ID:13925 VHDL warning at <location>: comparison between unequal length operands always returns <string>, left argument length <value> is different from right argument length <value>
ID:13926 VHDL Use Clause error at <location>: more than one Use Clause imports a declaration of simple name "<name>" -- none of the declarations are directly visible
ID:13927 VHDL syntax error at <location>: <text> is an invalid identifier in VHDL
ID:13928 VHDL type inferencing error at <location>: type of expression is ambiguous - "<type1>" or "<type2>" are two possible matches
ID:13929 VHDL syntax error at <location>: can't recognize character string <text>
ID:13930 VHDL Package Declaration error at <location>: package "<name>" already exists in the work library
ID:13931 VHDL Binding Indication error at <location>: can't bind component port "<name>" with mode "<text>" to design entity port "<name>" with incompatible mode "<text>"
ID:13932 VHDL error at <location>: can't implement clock enable condition specified using binary operator "<name>"
ID:13933 VHDL error at <location>: can't implement clock enable condition because clock enable signals are combined using binary operator "<name>"
ID:13934 VHDL error at <location>: can't implement register for two clock edges combined with a binary operator
ID:13935 VHDL error at <location>: can't synthesize logic for statement with conditions that test for the edges of multiple clocks
ID:13936 VHDL attribute warning at <location>: attribute "<name>" cannot be specified for multidimensional port "<name>" -- attribute is valid only for single-bit or one-dimensional ports
ID:13937 VHDL Process Statement warning at <location>: inferring latch(es) for signal or variable "<name>", which holds its previous value in one or more paths through the process
ID:13938 VHDL Subprogram Body warning at <location>: value of variable "<name>" used in Subprogram Body expression may depend on variable's default initial value because variable may not be assigned a value in the statements preceding the variable's use in the expression
ID:13939 VHDL Case Statement or If Statement error at <location>: can't synthesize condition that contains an isolated 'EVENT predefined attribute
ID:13940 VHDL Wait Statement error at <location>: Condition Clause for Wait Statement should not evaluate to a constant TRUE or FALSE
ID:13941 VHDL Report Statement at <location>: <report message> (NOTE)
ID:13942 VHDL Report Statement at <location>: <report message> (WARNING)
ID:13943 VHDL Report Statement at <location>: <report message> (FAILURE or ERROR)
ID:13944 VHDL exponentiation error at <location>: operator not supported for the specified operands, <text>
ID:13945 VHDL warning at <location>: constant value overflow
ID:13946 VHDL Based Literal error at <location>: base of literal must be between 2 and 16, inclusive
ID:13947 VHDL Port Association information at <location>: port "<name>" was associated with "open".
ID:13948 VHDL type inferencing warning at <location>: two visible identifiers match "<identifier>" because the actual at position <number> has an ambiguous type - it could be "<type>" or "<type>", assuming "<type>"
ID:13949 VHDL Configuration error at <location>: cross-hierarchy block configurations are not supported
ID:13950 VHDL Message Directive error at <location>: message directives cannot precede a design unit other than an entity or architecture
ID:13951 VHDL Unconstrained Array error at <location>: formal "<name>" must be constrained
ID:13952 VHDL Subprogram error at <location>: failed to elaborate call to subprogram "<name>"
ID:13953 VHDL Operator error at <location>: failed to evaluate call to operator "<name>"
ID:13954 VHDL Operator error at <location>: cannot generate symbol for entity, whose interface contains reference to constant ID "<name>"
ID:13955 VHDL Scope error at <location>: design unit "<name>" is not visible in the present scope - you must refer to it with an expanded name such as "work.<name>"
ID:13956 VHDL Binding Indication error at <location>: binding indication with OPEN entity aspect cannot contain generic or port bindings
ID:13957 VHDL Binding Indication error at <location>: binding indication in configuration specification must have an entity aspect
ID:13958 VHDL Binding Indication error at <location>: binding indication in component configuration for instance "<name>" must have an entity aspect
ID:13959 VHDL Binding Indication error at <location>: primary binding for incrementally bound component instance "<name>" cannot have an OPEN entity aspect
ID:13960 VHDL Binding Indication error at <location>: entity aspect in incremental binding for component instance "<name>" must match the entity aspect in the primary binding
ID:13961 VHDL Binding Indication error at <location>: can't incrementally bind port "<name>" because it was already bound in the primary binding
ID:13962 VHDL Binding Indication error at <location>: primary binding indication first associates port "<name>" here
ID:13963 VHDL Default Binding Indication error at <location>: can't bind component formal "<name>" to corresponding formal on entity "<name>" using default binding rules
ID:13964 VHDL Component Instantiation error at <location>: failed to elaborate instance "<name>" of component "<name>", which was bound to primary unit "<name>" - check the primary and/or incremental bindings
ID:13965 VHDL Binding Indication error at <location>: see <string> binding for component instance "<name>"
ID:13966 VHDL Incomplete Partial Association warning at <location>: port or argument "<name>" has <number>/<number> unassociated elements
ID:13967 VHDL Incomplete Partial Association error at <location>: generic "<name>" has <number>/<number> unassociated elements
ID:13968 VHDL Partial Association error at <location>: partial association of formal "<name>" overlaps with a previous association
ID:13969 VHDL Binding Indication error at <location>: incremental binding for component instance "<name>" must have an entity aspect if the primary binding has an OPEN entity aspect
ID:13970 VHDL Binding Indication error at <location>: incremental binding for component instance "<name>" cannot have an OPEN entity aspect
ID:13971 VHDL syntax error at <location>: comment block must have the beginning comment delimiter (slash and asterisk).
ID:13972 VHDL warning at <location>: block comments cannot be nested.
ID:13973 VHDL syntax error at <location>: experienced unexpected end-of-file while processing comment block. The comment block must have the ending comment delimiter (asterisk and slash).
ID:13974 VHDL error at <location>: block comments are not supported in <name>
ID:13975 VHDL error at <location>: <name> is not supported in <name>, and is only supported for VHDL 2008
ID:13976 VHDL error at <location>: closing alternative label (<name>) is specified without the corresponding opening alternative label.
ID:13977 VHDL error at <location>: the expression in a case generate statement must be static.
ID:13978 VHDL error at <location>: a matching case statement must have a '?' in the beginning as well at the end of the case statement.
ID:13979 VHDL error at <location>: Unsupported case expression type in a matching case statement.
ID:13980 Invalid bit string literal "<name>" at <name>: a decimal bit string literal can only have digits
ID:13981 VHDL error at <location>: unable to truncate the bit string literal "<name>" to get the specified length
ID:13982 SystemVerilog warning at <location>: automatically converting 4-state value to 2-state by replacing X and Z with 0
ID:13983 SystemVerilog error at <location>: can't declare unpacked struct or union as signed or unsigned
ID:13984 SystemVerilog error at <location>: can't declare struct as tagged
ID:13985 SystemVerilog error at <location>: struct member cannot be unconstrained
ID:13986 SystemVerilog error at <location>: no support for unions
ID:13987 SystemVerilog error at <location>: expression has <number> elements ; expected <number>
ID:13988 SystemVerilog error at <location>: arguments with default values must be declared by ANSI style declarations
ID:13989 SystemVerilog error at <location>: outputs cannot have default values
ID:13990 SystemVerilog error at <location>: argument "<name>" associated with empty expression must have a default value
ID:13991 SystemVerilog error at <location>: expression type does not match enum target type
ID:13992 SystemVerilog error at <location>: expression type does not match struct target type
ID:13993 SystemVerilog error at <location>: can't assign aggregate expression to a scalar or vector target
ID:13994 SystemVerilog error at <location>: assignments to unpacked arrays must be aggregate expressions
ID:13995 SystemVerilog error at <location>: can't assign aggregate expression to unpacked array with incompatible element type
ID:13996 SystemVerilog error at <location>: aggregate expression has <number> unpacked dimensions but the target expects <number>
ID:13997 SystemVerilog error at <location>: can't assign aggregate expression to a packed struct
ID:13998 SystemVerilog error at <location>: can't assign indexed name to target with incompatible type
ID:13999 SystemVerilog error at <location>: type of indexed name does not match the expected type
ID:14000 WYSIWYG RAM primitive "<name>" in operation mode "<name>" uses an unsupported value for parameter "<name>"
ID:14001 WYSIWYG RAM Primitive "<name>" has set the parameter ENABLE_ECC to TRUE, but the ECC feature is not supported by the RAM Primitive.
ID:14002 WYSIWYG primitive "<name>" has illegal value for <name> parameter
ID:14003 WYSIWYG primitive "<name>" has illegal value for <name> parameter -- value must be a number
ID:14004 Value for <name> parameter in WYSIWYG primitive "<name>" must be TRUE or FALSE
ID:14005 Value for <name> parameter in WYSIWYG primitive "<name>" must be YES or NO
ID:14006 Value for <name> parameter in WYSIWYG primitive "<name>" must be greater than or equal to <number>
ID:14007 Value for <name> parameter in WYSIWYG primitive "<name>" must be less than or equal to <number>
ID:14008 WYSIWYG primitive "<name>" is missing required <name> parameter
ID:14009 WYSIWYG primitive "<name>" has <name> parameter set to <text> value, but is missing value for required <name> parameter
ID:14010 WYSIWYG primitive "<name>" cannot have value for <name> parameter unless <name> parameter is not set to <text> value
ID:14011 WYSIWYG primitive "<name>" cannot have value for <name> parameter unless <name> parameter is set to <text> value
ID:14012 WYSIWYG primitive "<name>" has <name> port that cannot be connected <text>
ID:14013 WYSIWYG primitive "<name>" has <name> port that must be connected <text>
ID:14014 WYSIWYG primitive "<name>" has <name> port that should be connected <text>
ID:14015 WYSIWYG primitive "<name>" has <name> port with specified width of <number>, but only <number> bits are connected
ID:14016 WYSIWYG primitive "<name>" has <name> port with a specified width of <number>, but has <number> more bits connected than the specified width
ID:14017 WYSIWYG primitive "<name>" has illegal value <name> for parameter <name>. <text>
ID:14018 WYSIWYG primitive "<name>" has illegal size <number> for string parameter <name>. <text>
ID:14019 WYSIWYG primitive "<name>" uses test-only parameter <name>, but parameter can be used only in test mode
ID:14020 WYSIWYG primitive "<name>" uses ports that must be connected
ID:14021 Port <name>[<number>] of WYSIWYG primitive "<name>" is not connected, but the port must be connected
ID:14022 WYSIWYG primitive "<name>" uses ports that require an INI, but the INI is not enabled
ID:14023 WYSIWYG primitive "<name>" uses the INI protected port <name>[<number>], but the port can only be used when the INI is enabled
ID:14024 Parameter "<text>" of instance "<name>" has illegal value "<text>" assigned to it. <text>.
ID:14025 LATCH primitive "<name>" is permanently disabled
ID:14026 LATCH primitive "<name>" is permanently enabled
ID:14027 WYSIWYG LCELL primitive "<name>" must have LUT_MASK parameter
ID:14028 WYSIWYG LCELL primitive "<name>" has illegal value for LUT_MASK parameter
ID:14029 WYSIWYG LCELL primitive "<name>" cannot use cout port when in normal mode
ID:14030 WYSIWYG LCELL primitive "<name>" must use cout port when in arithmetic mode
ID:14031 WYSIWYG LCELL primitive "<name>" cannot use datad port when in arithmetic mode
ID:14032 WYSIWYG LCELL primitive "<name>" must use sdata port when sload port is used
ID:14033 WYSIWYG LCELL primitive "<name>" is dependent on unconnected inputs
ID:14034 WYSIWYG LCELL primitive "<name>" cin0, cin1, cout0, and cout1 ports cannot be used in design entry
ID:14035 WYSIWYG LCELL COMB primitive "<name>" has illegal format for LUT_MASK parameter value -- value must be 16-digit hexadecimal number or 64-digit binary number format
ID:14036 WYSIWYG LCELL COMB primitive "<name>" has illegal value for LUT_MASK parameter -- value must be 4-digit hexadecimal number or 16-digit binary number
ID:14037 WYSIWYG LCELL COMB primitive "<name>" must use LUT_MASK parameter
ID:14038 WYSIWYG LCELL COMB primitive "<name>" has LUT_MASK parameter that is dependent on one or more unconnected input ports
ID:14039 WYSIWYG LCELL COMB primitive "<name>" must use sharein port when in shared arithmetic mode
ID:14040 WYSIWYG LCELL COMB primitive "<name>" must use all LUT input ports when in extended LUT mode
ID:14041 WYSIWYG LCELL COMB primitive "<name>" cannot use datag port -- datag port must be used only in extended LUT mode
ID:14042 WYSIWYG LCELL flipflop primitive "<name>" must use <name> port if it uses <name> port
ID:14043 WYSIWYG LCELL flipflop primitive "<name>" must use <name> port if it uses <name> port
ID:14044 WYSIWYG LCELL flipflop primitive "<name>" must use sdata port if sload port is used
ID:14045 WYSIWYG LCELL flipflop primitive "<name>" must use <name> port or <name> port if <name> port is used
ID:14046 WYSIWYG LCELL flipflop primitive "<name>" must use sload port if sdata port is used
ID:14047 WYSIWYG LCELL COMB primitive "<name>" cannot use sumout port and combout port at the same time
ID:14048 WYSIWYG flipflop primitive "<name>" must have <name> port fed by VCC if <name> port is used
ID:14049 WYSIWYG flipflop primitive "<name>" cannot use <name> port and <name> port at the same time
ID:14050 WYSIWYG flipflop primitive "<name>" cannot use <name> port and <name> port at the same time
ID:14051 WYSIWYG flipflop primitive "<name>" must have <name> port specified
ID:14052 WYSIWYG flipflop primitive "<name>" cannot use <name> port and power-up low
ID:14053 WYSIWYG flipflop primitive "<name>" cannot use <name> port and power-up high
ID:14054 WYSIWYG I/O primitive "<name>" is in unsupported mode
ID:14055 WYSIWYG I/O primitive "<name>" must have padio port
ID:14056 WYSIWYG I/O primitive "<name>" has illegal OPERATION_MODE parameter value <name>
ID:14057 WYSIWYG I/O primitive "<name>" cannot have both a clear signal and power-up high, or both a preset signal and power-up low
ID:14058 WYSIWYG DDIO primitive "<name>" cannot have both a clear signal and power-up high, or both a preset signal and power-up low
ID:14059 WYSIWYG I/O primitive "<name>" has OPERATION_MODE parameter value set to BIDIR, but does not have oe port
ID:14060 WYSIWYG I/O primitive "<name>" is DQS I/O pin, but its OPERATION_MODE parameter is not set to INPUT or BIDIR.
ID:14061 WYSIWYG primitive "<name>" has illegal value for OUTPUT_MODE parameter
ID:14062 WYSIWYG primitive "<name>" cannot use clk port when its OUTPUT_MODE parameter is set to COMB
ID:14063 WYSIWYG primitive "<name>" cannot have pexpout port when its OPERATION_MODE parameter is not set to PTERM_EXP or PACKED_PTERM_EXP
ID:14064 WYSIWYG primitive "<name>" must not use pxor port in non-XOR mode
ID:14065 WYSIWYG primitive "<name>" uses pterm5 port, but pterm5 port is not supported for non-parallel expander or VCC modes
ID:14066 WYSIWYG MCELL primitive "<name>" cannot use both clk and pclk ports
ID:14067 WYSIWYG MCELL primitive "<name>" cannot use both aclr and paclr ports
ID:14068 WYSIWYG primitive "<name>" must use either clk or pclk port for registered output
ID:14069 WYSIWYG primitive "<name>" cannot use dataout port when OPERATION_MODE parameter is set to PTERM_EXP
ID:14070 WYSIWYG primitive "<name>" has illegal pexpin port -- cannot be VCC, GND, inverted, direct from pin, or from non-parallel expander output port on another WYSIWYG primitive
ID:14071 WYSIWYG primitive "<name>" must use pxor port when in XOR mode
ID:14072 WYSIWYG primitive "<name>" must use pterm5 port when in XOR mode and in DFF mode, and when using the pexpout port
ID:14073 WYSIWYG primitive "<name>" must use all pterm (pterm0 - pterm4) ports when in XOR mode and when pexpout port is not used
ID:14074 WYSIWYG primitive "<name>" cannot use pterm5 port when in XOR mode and when pexpout port is not used
ID:14075 WYSIWYG primitive "<name>" uses pexpout port that must feed pexpin port
ID:14076 WYSIWYG primitive "<name>" must use pexpin port or at least one pterm port if pexpout port is used
ID:14077 WYSIWYG primitive "<name>" uses fpin fast input port that does not feed register port -- it must feed register port. In addition, WYSIWYG primitive must not use pterm5 and pxor ports, and, if PEXP_MODE parameter is set to OFF, it must not use the pterm0 - pterm4 ports.
ID:14078 WYSIWYG primitive "<name>" clock port must be fed by input pin, and must not be fed by any logic gates
ID:14079 WYSIWYG MCELL primitive "<name>" register must use fpin fast input port if it is in register mode, DFF mode, and VCC mode
ID:14080 WYSIWYG MCELL primitive "<name>" has illegal value for REGISTER_MODE parameter -- value must be DFF or TFF
ID:14081 WYSIWYG MCELL primitive "<name>" has illegal value for PEXP_MODE parameter -- value must be ON or OFF
ID:14082 WYSIWYG MCELL primitive "<name>" has illegal value for POWER_UP parameter -- value must be HIGH or LOW
ID:14083 WYSIWYG MCELL primitive "<name>" has illegal combination of mode parameter values -- cannot be in VCC mode and combinational mode when parallel expander mode is turned off
ID:14084 WYSIWYG MCELL primitive "<name>" has illegal combination of mode parameters -- cannot be in XOR or XNOR mode, TFF mode, and parallel expander mode
ID:14086 ROM name is "<name>"
ID:14087 Memory Initialization File or Hexadecimal (Intel-Format) File for ROM is not specified
ID:14088 WYSIWYG CAM primitive "<name>" has actual ADDRESS_WIDTH <number>, which is different from declared ADDRESS_WIDTH <number>
ID:14089 WYSIWYG CAM primitive "<name>" has actual literal width <number>, which is different from literal width <number> declared in parameter
ID:14090 In current operating mode, WYSIWYG RAM primitive "<name>" cannot have <name> port or parameter connected
ID:14091 WYSIWYG RAM primitive "<name>" must have the <name> port connected
ID:14092 WYSIWYG RAM primitive "<name>" has the use of <name> port declared, but the port is unconnected
ID:14093 Can't recognize value for <name> parameter for WYSIWYG RAM primitive "<name>"
ID:14094 When in its current operating mode, WYSIWYG RAM primitive "<name>" cannot have <name> parameter
ID:14095 WYSIWYG RAM primitive "<name>" must have <name> parameter
ID:14096 WYSIWYG RAM primitive "<name>" has mismatched <names> parameters for <name> port and <name> port
ID:14097 WYSIWYG RAM primitive "<name>" has too many bits
ID:14098 WYSIWYG primitive "<name>" must use clk0 port.
ID:14099 WYSIWYG primitive "<name>" must use clk1 port if ena1 port is used
ID:14100 WYSIWYG primitive "<name>" must use clk1 port if ena3 port is used
ID:14101 WYSIWYG primitive "<name>" uses portabyteenamasks port, but PORT_A_DATA_WIDTH parameter is not a byte multiple of width of portabyteenamasks port, or portadatain port is not used
ID:14102 WYSIWYG primitive "<name>" uses portbbyteenamasks port, but PORT_B_DATA_WIDTH parameter is not a byte multiple of width of portbbyteenamasks port, or portbdatain port is not used
ID:14103 WYSIWYG primitive "<name>" cannot have RAM_BLOCK_TYPE parameter set to <name> when in <name> operation mode
ID:14104 WYSIWYG primitive "<name>" cannot have RAM_BLOCK_TYPE parameter set to <name> when in read-only operation mode
ID:14105 WYSIWYG primitive "<name>" cannot have a Memory Initialization File specified when RAM_BLOCK_TYPE parameter is set to <name>
ID:14106 WYSIWYG primitive "<name>" has inconsistent parameter values <name> and <name>
ID:14107 WYSIWYG RAM primitive "<name>" uses <name> port, which is inconsistent with <name> parameter value
ID:14109 WYSIWYG RAM primitive "<name>" has different clock signals feeding bits of <name> input bus port
ID:14110 No clock transition on "<name>" register due to stuck clock or clock enable
ID:14111 WYSIWYG RAM primitive "<name>" has different clear signals feeding bits of <name> input bus port
ID:14112 Block type <name> for WYSIWYG RAM primitive "<name>" is not supported in target device family
ID:14113 Memory block type M512 for WYSIWYG RAM primitive "<name>" converted to block type AUTO
ID:14114 WYSIWYG RAM primitive "<name>" has inconsistent values for <name> and <name> parameters. The parameters must have the same values when the ports for port A and port B use the same <name> clock.
ID:14115 WYSIWYG RAM primitive "<name>" has inconsistent values for <name>, <name>, <name>, and <name> parameters
ID:14116 WYSIWYG RAM primitive "<name>" has inconsistent values for <name> and <name> parameters -- parameters must have same values because <text>
ID:14117 WYSIWYG RAM primitive "<name>" cannot have "<name>" port connected because parameter "<name>" is not set.
ID:14118 WYSIWYG RAM Primitive "<name>" enables the ECC feature, which only can be implemented in 512 (depth) by 32 (width) in simple dual-port mode.
ID:14119 WYSIWYG RAM Primitive "<name>" uses ECC feature but it can't be implemented in 2Kx64 simple dual-port mode. To use the ECC feature, the RAM must have the depth no more than 2K and data width no more than 64 and in simple dual-port mode without mixed-width.
ID:14120 WYSIWYG RAM Primitive "<name>" cannot use ECC and byte-mask features at the same time.
ID:14121 WYSIWYG RAM Primitive "<name>" uses ECC feature and the mixed-port read-during-write mode is set to old memory content. These two features cannot be used together.
ID:14122 WYSIWYG RAM Primitive "<name>" uses ECC feature and the block type is set to M9K. M9K does not support the ECC feature.
ID:14123 Value for the INPUT_FREQUENCY parameter of the PLL "<name>" is not specified
ID:14124 Value for the CLOCK1_BOOST or CLOCK2_BOOST parameter of the PLL "<name>" is not specified
ID:14125 Parameter <name> is not supported for WYSIWYG primitive "<name>"
ID:14126 PLL "<name>" uses advanced parameter "<name>", but the "<name>" parameter is unspecified or set to "<name>"
ID:14127 PLL "<name>" has the parameter <name> with an illegal value of "<number>" -- value must be one of the <number> legal values
ID:14128 Parameter <name> has legal values of <text>
ID:14129 PLL parameter value <name> is not in range allowed for parameter
ID:14130 Reduced register "<name>" with stuck <name> port to stuck value <number>
ID:14131 Reduced register "<name>" with stuck <name> port to stuck value <number> -- power-up level has changed
ID:14132 OPERATION_MODE parameter for PLL "<name>" has unsupported value <text>
ID:14133 PLL_TYPE parameter for PLL <name> has unsupported value <text>
ID:14134 PLL "<name>" of type <type> cannot be in <mode>
ID:14135 COMPENSATE_CLOCK parameter for PLL "<name>" has unsupported value <name> for <mode>
ID:14136 Can't recognize "<name>" <signal or parameter> for <PLL type or PLL mode> PLL "<name>"
ID:14137 Ignored <name> parameter in PLL "<name>" because counter is set to bypass mode
ID:14138 PLL "<name>" must contain <name> <signal or parameter>
ID:14139 Can't recognize <name> value for <name> parameter in PLL "<name>"
ID:14140 WYSIWYG primitive "<name>" has illegal value <name> for parameter <name>
ID:14141 PLL "<name>" has illegal or non-numeric value <text> for <name> parameter
ID:14142 PLL "<name>" must use <inclk0 or inclk1> port because it is specified in PRIMARY_CLOCK parameter
ID:14143 PLL "<name>" must use <fbin port or FEEDBACK_SOURCE parameter> because it is in EXTERNAL_FEEDBACK mode
ID:14144 PLL "<name>" has <number> time delay for <name> parameter, but time delay must be between <number> ps and <number> ps, with a resolution of 250 ps
ID:14145 PLL "<name>" has illegal or non-numeric value <number> for <name> parameter
ID:14146 PLL "<name>" has <CLKn_COUNTER or EXTCLKn_COUNTER> parameter with value <text>, but that value is already specified by another <CLKn_COUNTER or EXTCLKn_COUNTER> parameter
ID:14147 PLL "<name>" has illegal unit <text> for <name> parameter -- legal unit should be <text>
ID:14148 PLL "<name>" cannot be in <mode> because SCAN_CHAIN parameter is set to SHORT
ID:14149 Can't implement <name> signal or parameter for PLL "<name>" because SCAN_CHAIN parameter is set to SHORT
ID:14150 Can't recognize value <name> for EXTCLK0_COUNTER parameter in PLL "<name>" because SCAN_CHAN parameter is set to SHORT -- EXTCLK0_COUNTER parameter must be set to G0
ID:14151 Can't implement <name> parameter in PLL "<name>" because counter is set to bypass mode
ID:14152 PLL "<name>" must have OPERATION_MODE parameter set to NORMAL when PLL_TYPE parameter is set to CDR
ID:14153 PLL "<name>" must have BANDWIDTH_TYPE parameter set to LOW or HIGH when PLL_TYPE parameter is set to CDR
ID:14154 PLL "<name>" cannot have value for <name> parameter
ID:14155 GXB transmitter PLL "<name>" cannot have TRUE value for USE_DC_COUPLING parameter
ID:14156 PLL "<name>" has PLL_TYPE parameter set to <name> value, but uses other parameter values and ports that are incompatible with PLL type
ID:14157 PLL "<name>" uses test-only parameter <name>, but parameter must be used only in test mode
ID:14158 PLL "<name>" uses the parameter <name>, but the parameter is not supported
ID:14161 Can't remap output port <name> of PLL "<name>" for target device family
ID:14164 Can't remap output clock port clk[<number>] of PLL "<name>" for target device family because PLLs in target device can have only output clock ports clk[<number>] to clk[<number>]
ID:14169 Can't remap SCLK port of PLL "<name>" to CLK port for target device family because LVDS PLLs in target device must have a <name> value of greater than 0
ID:14170 Can't remap PLL "<name>" using zero delay buffer mode for target device family because PLLs in target device using zero delay buffer mode requires a bidirectional I/O in the feedback path
ID:14174 WYSIWYG LVDS transmitter or receiver primitive "<name>" uses loopback ports, but loopback features have not been enabled
ID:14175 WYSIWYG LVDS receiver primitive "<name>" has DPA_DEBUG parameter set to ON, but DPA_DEBUG parameter has not been enabled
ID:14176 "<name>" can take only ON/OFF or TRUE/FALSE Boolean values!
ID:14177 Value for <name> parameter in WYSIWYG primitive "<name>" must be ON or OFF
ID:14178 WYSIWYG LVDS receiver primitive "<name>" has illegal value for CHANNEL_WIDTH parameter
ID:14179 WYSIWYG LVDS transmitter primitive "<name>" has illegal value for CHANNEL_WIDTH parameter
ID:14180 WYSIWYG LVDS receiver primitive "<name>" has illegal value for DPLL_LOCKCNT parameter
ID:14181 WYSIWYG LVDS receiver primitive "<name>" has illegal value for DPLL_LOCKWIN parameter
ID:14182 WYSIWYG LVDS receiver primitive "<name>" has illegal value for ENABLE_DPA parameter for target device family.
ID:14183 WYSIWYG GXB receiver channel primitive "<name>" must have CHANNEL_WIDTH parameter
ID:14184 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for CHANNEL_WIDTH parameter -- value must be 16 or 20 when in Double Data Rate mode
ID:14185 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for CHANNEL_WIDTH parameter -- value must be 16 or 20 when in Double Data Rate mode or Deserializer Double Data Rate mode
ID:14186 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for CHANNEL_WIDTH parameter -- value must be 8 or 10 when not in Double Data Rate mode
ID:14187 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for CHANNEL_WIDTH parameter -- value must be 8 or 16 when in 8B10B mode
ID:14188 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for CHANNEL_WIDTH parameter -- value must be 32 or 40 when in Double Data Rate mode and Deserializer Double Data mode
ID:14189 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for CHANNEL_WIDTH parameter -- value must be 8, 16 or 32 when in 8B10B mode
ID:14190 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for CHANNEL_NUM parameter -- value must be a number between 0 and 3
ID:14191 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for RUN_LENGTH parameter -- value must be between 4 and 128 when 8B10B mode is off and CHANNEL_WIDTH parameter is set to 8 or 16
ID:14192 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for RUN_LENGTH parameter -- value must be between 5 and 160 when 8B10B mode is on or CHANNEL_WIDTH parameter is set to 10 or 20
ID:14193 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for RUN_LENGTH parameter -- value must be a multiple of 4 when not in 8B10B mode and CHANNEL_WIDTH parameter is set to 8 or 16
ID:14194 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for RUN_LENGTH parameter -- value must be a multiple of 5 when in 8B10B mode or when CHANNEL_WIDTH parameter is set to 10 or 20
ID:14195 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for ALIGN_PATTERN_LENGTH parameter -- value must be 7, 10, or 16 when using symbol alignment
ID:14196 WYSIWYG GXB receiver channel primitive "<name>" has unsupported value for BANDWIDTH_TYPE parameter -- changed value to NEW_LOW value
ID:14197 WYSIWYG GXB receiver channel primitive "<name>" has unsupported value false for FORCE_SIGNAL_DETECT parameter -- changed value to true
ID:14198 WYSIWYG GXB receiver channel primitive "<name>" has unsupported value <number> mV for SIGNAL_THRESHOLD_SELECT parameter -- changed value to <number> mV
ID:14199 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for ALIGN_PATTERN_LENGTH parameter -- value must be 7 or 10 when J deserialization factor value is 10
ID:14200 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for ALIGN_PATTERN_LENGTH parameter -- value must be 16 when J deserialization factor value is 8
ID:14201 WYSIWYG GXB receiver channel primitive "<name>" has symbol alignment pattern specified that has different length from pattern specified in ALIGN_PATTERN_LENGTH parameter
ID:14202 WYSIWYG GXB receiver channel primitive "<name>" has illegal value or is missing value for CRUCLK_MULTIPLIER parameter -- value must be 4, 5, 8, or 10
ID:14203 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for CRUCLK_MULTIPLIER parameter -- value must be 4 or 5 when the USE_CRUCLK_DIVIDER parameter is turned on
ID:14204 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for INFINIBAND_INVALID_CODE parameter -- value must be 0, 1, 2 or 3
ID:14205 WYSIWYG GXB receiver channel primitive "<name>" has illegal value or is missing value for "<name>" parameter -- value must be GIGE, XAUI, or NONE
ID:14206 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for "<name>" parameter -- value must be <name> when in <XAUI or GIGE> synchronization mode
ID:14207 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for "<name>" parameter -- value must be <name> or <name> when in <XAUI or GIGE> synchronization mode
ID:14208 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for EQUALIZER_CTRL_SETTING parameter -- value must be <number>, <number>, <number>, <number>, or <number>
ID:14209 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for SIGNAL_THRESHOLD_SELECT parameter -- value must be <number>, <number>, <number>, or <number>
ID:14210 WYSIWYG GXB receiver channel primitive "<name>" cannot have value for <name> parameter
ID:14211 WYSIWYG GXB receiver channel primitive "<name>" cannot have USE_SYMBOL_ALIGN parameter set to FALSE
ID:14212 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for SELF_TEST_MODE parameter -- value must be between <number> and <number>
ID:14213 WYSIWYG GXB receiver channel primitive "<name>" has more than one feedback mode specified
ID:14214 WYSIWYG GXB receiver channel primitive "<name>" cannot be in PRBS self-test mode when in post-8B/10B feedback mode
ID:14215 WYSIWYG GXB receiver channel primitive "<name>" has CLK_OUT_MODE_REFERENCE parameter set to OFF, but does not use USE_RATE_MATCH_FIFO parameter
ID:14216 WYSIWYG GXB receiver channel primitive "<name>" has CLK_OUT_MODE_REFERENCE parameter set to OFF, but has CHANNEL_WIDTH parameter set to <number> -- CHANNEL_WIDTH parameter must be set to 8 or 10 when CLK_OUT_MODE_REFERENCE parameter is set to OFF
ID:14217 WYSIWYG GXB receiver channel primitive "<name>" has CLK_OUT_MODE_REFERENCE parameter set to ON, but parameter must be set to OFF when in Generic FIFO mode
ID:14218 WYSIWYG GXB receiver channel primitive "<name>" cannot be in self-test mode when sending reverse parallel feedback
ID:14219 WYSIWYG GXB receiver channel primitive "<name>" must have 8B10B mode enabled when in self-test mode
ID:14220 WYSIWYG GXB receiver channel primitive "<name>" must use align pattern 0101111100(K28.5+) or 1010000011(K28.5-) when in self-test mode
ID:14221 10-bit alignment pattern on WYSIWYG GXB receiver channel primitive "<name>" in PRBS self-test mode changed from <name> to <name>
ID:14222 16-bit alignment pattern on WYSIWYG GXB receiver channel primitive "<name>" in PRBS self-test mode changed from <name> to <name>
ID:14223 8B/10B decoder on WYSIWYG GXB receiver channel primitive "<name>" in PRBS self-test mode has been turned off
ID:14224 Channel width parameter on WYSIWYG GXB receiver channel primitive "<name>" in PRBS self-test mode has been changed from <number> to <number>
ID:14225 WYSIWYG GXB receiver channel primitive "<name>" in self-test mode cannot use the rate matching FIFO
ID:14226 WYSIWYG GXB transmitter channel primitive "<name>" must have CHANNEL_WIDTH parameter
ID:14227 WYSIWYG GXB transmitter channel primitive "<name>" has illegal value <number> for CHANNEL_WIDTH parameter -- value must be <text> <text>
ID:14228 WYSIWYG GXB transmitter channel primitive "<name>" has illegal value for CHANNEL_WIDTH parameter -- value must be 16 or 20 when in Double Data Rate mode
ID:14229 WYSIWYG GXB transmitter channel primitive "<name>" has illegal value for CHANNEL_WIDTH parameter -- value must be 8 or 10 when not in Double Data Rate mode
ID:14230 WYSIWYG GXB transmitter channel primitive "<name>" has illegal value for CHANNEL_WIDTH parameter -- value must be 8 or 16 when in 8B10B mode
ID:14231 WYSIWYG GXB transmitter channel primitive "<name>" has illegal value for CHANNEL_NUM parameter -- value must be a number between 0 and 3
ID:14232 WYSIWYG GXB transmitter channel primitive "<name>" has illegal value for FORCE_DISPARITY_MODE parameter -- value must be FALSE when in 8B10B mode
ID:14233 WYSIWYG GXB transmitter channel primitive "<name>" has illegal value or is missing value for <name> parameter -- value must be GIGE, XAUI, or NONE
ID:14234 WYSIWYG GXB transmitter channel primitive "<name>" must have TRUE value for USE_FIFO_MODE parameter
ID:14235 WYSIWYG GXB transmitter channel primitive "<name>" has illegal value for VOD_CTRL_SETTING parameter -- value must be <number>, <number>, <number>, <number>, <number>, or <number>
ID:14236 WYSIWYG GXB receiver channel primitive "<name>" has illegal value for PREEMPHASIS_CTRL_SETTING parameter -- value must be <number>, <number>, <number>, <number>, <number>, or <number>
ID:14237 WYSIWYG GXB transmitter channel primitive "<name>" has illegal value for SELF_TEST_MODE parameter -- value must be between <number> and <number>
ID:14238 WYSIWYG GXB transmitter channel primitive "<name>" must have FORCE_DISPARITY_MODE parameter turned off when USE_REVERSE_PARALLEL_FEEDBACK parameter is turned on
ID:14239 WYSIWYG GXB transmitter channel primitive "<name>" has illegal value <number> for TERMINATION parameter -- value must be between <number> and <number>
ID:14240 WYSIWYG GXB transmitter channel primitive "<name>" must have FORCE_DISPARITY_MODE parameter turned off when USE_SELF_TEST_MODE parameter is turned on
ID:14241 WYSIWYG GXB transmitter channel primitive "<name>" cannot be in self-test mode when using reverse parallel feedback
ID:14242 WYSIWYG GXB transmitter channel primitive "<name>" must enable 8B10B mode when in self-test mode
ID:14243 8B/10B decoder on WYSIWYG GXB transmitter channel primitive "<name>" in PRBS self-test mode has been turned off
ID:14244 Channel width parameter on WYSIWYG GXB transmitter channel primitive "<name>" in PRBS self-test mode has been changed from <number> to <number>
ID:14245 WYSIWYG XGMII primitive "<name>" has illegal value for <name> parameter -- value must be between <number> and <number>
ID:14246 WYSIWYG XGMII primitive "<name>" has illegal value for <name> parameter -- value must be <number>, <number>, <number>, or <number>
ID:14247 WYSIWYG primitive "<name>" has illegal value for OPERATION_MODE parameter
ID:14248 WYSIWYG primitive "<name>" must have OPERATION_MODE parameter
ID:14249 WYSIWYG primitive "<name>" has aclr port, but does not use its register
ID:14250 WYSIWYG primitive "<name>" has apre port, but does not use its register
ID:14251 WYSIWYG primitive "<name>" has ena port, but does not use its register
ID:14252 Value for SYNCH_MODE parameter in WYSIWYG primitive "<name>" must be ON or OFF
ID:14253 Value for REGISTER_CASCADE_MODE parameter in WYSIWYG primitive "<name>" must be ON or OFF
ID:14254 Value for SUM_LUTC_INPUT parameter in WYSIWYG primitive "<name>" must be DATAC, CIN, or QFBK
ID:14255 Value for SUM_LUTC_INPUT parameter in WYSIWYG LCELL COMB primitive "<name>" must be DATAC or CIN
ID:14256 WYSIWYG primitive "<name>" must use cin port or cout port if inverta port is used
ID:14257 WYSIWYG primitive "<name>" must not use regcascin port when not in register cascade mode
ID:14258 WYSIWYG primitive "<name>" must use regcascin port when in register cascade mode
ID:14259 WYSIWYG primitive "<name>" sclr or sload port must be used when in synchronous mode
ID:14260 WYSIWYG primitive "<name>" has <name> clear parameter, but it is specified for an unregistered port
ID:14261 WYSIWYG primitive "<name>" has <name> clear parameter, but it is not specified for a registered port
ID:14262 WYSIWYG primitive "<name>" has <name>[<bit number>] port that must be connected <text>
ID:14263 WYSIWYG primitive "<name>" cannot have <name> clock parameter set to NONE because associated port must be registered
ID:14264 WYSIWYG primitive "<name>" has inconsistent data widths for 36_BIT_MULTIPLY mode
ID:14265 DSP block output WYSIWYG primitive "<name>" uses inverted outputs, but inverted outputs are not supported in the target family
ID:14266 DSP block multiplier WYSIWYG primitive "<name>" uses port <name>, but port <name> is not supported in the target family
ID:14267 DSP block WYSIWYG primitive "<name>" uses <name> mode, but <name> mode is not supported in the target family
ID:14268 DSP block WYSIWYG primitive "<name>" uses dynamic signals for port <name> in <name> mode, but dynamic signals for port <name> is not supported for <name> mode in the target family
ID:14269 DSP block output WYSIWYG primitive "<name>" uses port <name>, but port <name> is not supported in the target family
ID:14270 DSP block WYSIWYG primitive "<name>" uses <name> mode with am output width of <number>, but <name> mode with an output width of greater than <number> is not supported in the target family
ID:14271 Illegal value <text> for <name> parameter in WYSIWYG primitive "<name>" -- value must be <text>
ID:14272 WYSIWYG primitive "<name>" is missing value for <name> parameter. Legal values for <name> parameter are <values>.
ID:14273 WYSIWYG primitive "<name>" cannot have <name> parameter set to <text> value <text>
ID:14274 WYSIWYG primitive "<name>" must have <name> parameter set to <text> value <text>
ID:14275 Ignoring <name> parameter in LVDS transmitter "<name>" because LVDS transmitter is not in bypass mode
ID:14276 WYSIWYG CRC block primitive "<name>" has <number> fan-outs from output port <name> -- must use no more than <number> fan-outs
ID:14277 WYSIWYG CRC block or remote update block primitive "<name>" must use <name> port
ID:14278 WYSIWYG OTP block primitive "<name>" must use <name> port
ID:14279 WYSIWYG primitive "<name>" must use <name> port
ID:14280 Port "<name>" does not exist in primitive "<name>" of instance "<name>"
ID:14281 Failed to convert primitive "<name>" of instance "<name>" to primitive "<name>" because port "<name>" does not exist in the converted primitive
ID:14282 WYSIWYG DLL primitive "<name>" must have value specified for <name> parameter when <name> parameter is specified for DQS.
ID:14283 WYSIWYG <name> primitive "<name>" for <name> device family cannot be converted to WYSIWYG <name> primitive for <name> target device family because operating input frequency of <text> is outside range of supported frequencies
ID:14284 Synthesized away the following node(s):
ID:14285 Synthesized away the following node(s) of type <type>:
ID:14286 WYSIWYG "<name>" primitive has illegal value <text> for <name> parameter -- used default value of <number>
ID:14287 WYSIWYG "<name>" primitive has illegal value <text> for <name> parameter -- used value <number> and ignored other values
ID:14288 WYSIWYG "<name>" primitive has obsolete parameter <name> -- ignored value
ID:14289 WYSIWYG "<name>" primitive has <name> parameter set to <text> value -- ignored value because <name> parameter is set to <text> value and not to <text> value
ID:14290 Can't convert WYSIWYG primitive "<name>" to equivalent WYSIWYG primitive for target device family -- target device family does not support the following parameters
ID:14291 WYSIWYG primitive parameter "<name>" is not supported by target device family
ID:14292 Unable to convert WYSIWYG primitive "<name>" to equivalent WYSIWYG primitive for target device family -- target device family does not support the following ports
ID:14293 WYSIWYG primitive port "<name>" is not supported by target device family
ID:14294 WYSIWYG User Flash Memory (UFM) primitive "<name>" has illegal value for ADDRESS_WIDTH parameter -- value must be 7, 8, or 9
ID:14296 WYSIWYG Clock Delay Control primitive "<name>" has USES_CALIBRATION parameter set to TRUE, but USES_CALIBRATION parameter is not supported in current version of Quartus Prime software
ID:14297 WYSIWYG Clock Delay Control primitive "<name>" has DELAY_CHAIN_MODE parameter set to DYNAMIC, but DYNAMIC value is not supported in current version of Quartus Prime software
ID:14298 WYSIWYG Clock Control Block primitive "<name>" has illegal value <number> for DELAY_CHAIN parameter -- value must be between <number> and <number>
ID:14299 WYSIWYG Clock Delay Control primitive "<name>" has illegal DELAY_CHAIN value of <name>
ID:14300 WYSIWYG Clock Delay Control primitive "<name>" has illegal value <name> for <name> parameter
ID:14301 WYSIWYG Clock Delay Control Calibration primitive "<name>" has illegal value <name> for <name> parameter
ID:14302 WYSIWYG Clock Delay Control primitive "<name>" is in Dynamic Delay Chain mode, but does not have all DELAY_CTRL_SIM_DELAY parameters (DELAY_CTRL_SIM_DELAY_15_0, DELAY_CTRL_SIM_DELAY_31_16, DELAY_CTRL_SIM_DELAY_47_32, and DELAY_CTRL_SIM_DELAY_63_48) specified
ID:14303 WYSIWYG Clock Delay Control Calibration primitive "<name>" does not have all DELAY_CTRL_SIM_DELAY parameters (DELAY_CTRL_SIM_DELAY_15_0, DELAY_CTRL_SIM_DELAY_31_16, DELAY_CTRL_SIM_DELAY_47_32, and DELAY_CTRL_SIM_DELAY_63_48) specified
ID:14304 WYSIWYG Clock Delay Control primitive "<name>" is in Dynamic Delay Chain mode, but has illegal BEHAVIORAL_SIM_DELAY value of <number>
ID:14305 WYSIWYG Clock Delay Control primitive "<name>" is in Dynamic Delay Chain mode, but does not have TAN_DELAY_UNDER_DELAY_CTRL_SIGNAL parameter specified
ID:14306 WYSIWYG Clock Delay Control Calibration primitive "<name>" does not have TAN_DELAY_UNDER_DELAY_CTRL_SIGNAL parameter specified
ID:14307 WYSIWYG Clock Delay Control primitive "<name>" is in Static Delay Chain mode or has no Delay Chain mode, but has illegal TAN_DELAY_UNDER_DELAY_CTRL_SIGNAL value of <number>
ID:14308 WYSIWYG Clock Delay Control primitive "<name>" has <name> parameter <name> of length <number>, but parameter must be of length <number>
ID:14309 WYSIWYG Clock Delay Control Calibration primitive "<name>" has <name> parameter <name> of length <number>, but parameter must be of length <number>
ID:14310 WYSIWYG Clock Delay Control primitive "<name>" is in Static Delay Chain mode or has no Delay Chain mode, but has USES_CALIBRATION parameter set to TRUE -- USES_CALIBRATION parameter must be set to FALSE in Static Delay Chain mode or when there is no Delay Chain mode
ID:14311 WYSIWYG Clock Delay Control Calibration primitive "<name>" cannot be used in current version of Quartus Prime software
ID:14312 WYSIWYG primitive "<name>" has more input connections than WIDTH parameter value allows -- disconnecting extra signals
ID:14313 GXB REFCLK divider WYSIWYG primitive "<name>" has illegal value <name> for REFCLK_COUPLING_TERMINATION parameter
ID:14314 WYSIWYG ALM640 primitive "<name>" has too many address lines on <name> port
ID:14315 WYSIWYG ALM640 primitive "<name>" is driven by combinational sources on <name> port
ID:14316 WYSIWYG ALM640 primitive "<name>" is driven by registered sources on <name> port, but these registers use a different clock source
ID:14317 WYSIWYG ALM640 primitive "<name>" is driven by registered sources on <name> port, but these registers use asynchronous clear
ID:14318 WYSIWYG ALM640 primitive "<name>" is driven by registered sources on <name> port, but these registers use asynchronous load
ID:14319 Can't convert WYSIWYG RAM primitive "<name>" to equivalent WYSIWYG RAM primitive for target device family -- The depth of the RAM is too deep for the target device family.
ID:14320 Synthesized away node "<name>"
ID:14321 Can't convert WYSIWYG RAM primitive "<name>" to equivalent WYSIWYG RAM primitive for target device family -- The width of the RAM is too wide for the target device family.
ID:14322 Memory size (<number>) in design file differs from memory size (<number>) in MEM_INIT parameter -- truncated remaining initial content value to fit RAM
ID:14323 Memory size (<number>) in design file differs from memory size (<number>) in MEM_INIT parameter -- setting initial value for remaining addresses to 0
ID:14324 Memory Initialization File or Hexadecimal (Intel-Format) File for RAM is not specified but MEM_INIT parameter exists -- setting initial value from the content of mem_init parameter
ID:14325 RAM name is "<name>"
ID:14326 One or more don't care state values in FSM "<name>" are being recorded for formal verification as '0' instead of 'X'.
ID:14327 WYSIWYG RAM Primitive "<name>" has set the parameter ECC_PIPELINE_STAGE_ENABLED to TRUE, but does not use the output registers of the RAM primitive.
ID:14328 SystemVerilog error at <location>: can't assign "<string>" to target with incompatible type
ID:14329 SystemVerilog error at <location>: type of "<string>" does not match the expected type
ID:14330 SystemVerilog error at <location>: can't assign constant literal to target with incompatible type
ID:14331 SystemVerilog error at <location>: type of constant literal doesn't match the expected type
ID:14332 SystemVerilog error at <location>: dimension <number> of unpacked array has <number> elements, expected <number>
ID:14333 SystemVerilog error at <location>: dimension <number> of unpacked array has range [<number>:<number>], expected range [<number>:<number>]
ID:14334 SystemVerilog error at <location>: unpacked array type has <number> unpacked dimensions, expected <number>
ID:14335 SystemVerilog error at <location>: <string> has an aggregate value
ID:14336 SystemVerilog error at <location>: indexing <string> returns an aggregate value
ID:14337 SystemVerilog error at <location>: failed to evaluate comparison between aggregate values
ID:14338 SystemVerilog error at <location>: unpacked port <string> must be declared in a single declaration
ID:14339 SystemVerilog error at <location>: invalid redeclaration of unpacked array object <string>
ID:14340 SystemVerilog error at <location>: can't redeclare a packed array port <string> as an unpacked array
ID:14341 SystemVerilog error at <location>: invalid operator on aggregate value
ID:14342 SystemVerilog error at <location>: can't compare aggregate expression with <number> dimensions against an aggregate expression with <number> dimensions
ID:14343 SystemVerilog error at <location>: can't compare aggregate expression with <number> elements against aggregate expression with <number>
ID:14344 SystemVerilog error at <location>: invalid comparison to unpacked array or struct
ID:14345 SystemVerilog error at <location>: can't compare unpacked array to packed array
ID:14346 SystemVerilog error at <location>: no support for indexing unpacked array or struct port <string> in a list of ports
ID:14347 SystemVerilog error at <location>: can't connect inout port to a variable data type
ID:14348 SystemVerilog error at <location>: can't resolve assignment pattern in connection to port <number> on instance <string> because the instance has no module binding
ID:14349 SystemVerilog error at <location>: can't resolve assignment pattern in connection to port <number> on instance <string> because the port has an unknown formal type
ID:14350 SystemVerilog error at <location>: can't resolve aggregate expression in connection to port <number> on instance <string> because the port has an unknown formal type
ID:14351 SystemVerilog error at <location>: assignment pattern requires an assignment-like context
ID:14352 SystemVerilog error at <location>: can't assign concatenation to target with incompatible type
ID:14353 SystemVerilog error at <location>: type of concatenation does not match the expected type
ID:14354 SystemVerilog error at <location>: parameter with complex/aggregate value must have a type
ID:14355 SystemVerilog error at <location>: cannot assign or compare packed values to unpacked values or vice versa
ID:14356 SystemVerilog error at <location>: can't connect terminal on a gate to an aggregate expression
ID:14357 SystemVerilog error at <location>: assignments to unpacked structs must be aggregate expressions
ID:14358 SystemVerilog error at <location>: can't pass value from actual to argument <string>
ID:14359 SystemVerilog error at <location>: can't pass value from argument <string> to actual
ID:14360 SystemVerilog error at <location>: can't pass values between formal inout <string> and actual with incompatible types
ID:14361 SystemVerilog error at <location>: can't pass value from formal output <string> to actual with incompatible type
ID:14362 SystemVerilog error at <location>: can't pass value from actual to formal input "<string>" with incompatible type
ID:14363 SystemVerilog error at <location>: can't call function "<string>" with inout/output arguments outside a sequential statement
ID:14364 SystemVerilog error at <location>: no support for packed array types with more than one packed dimension
ID:14365 SystemVerilog error at <location>: no support for instantiating array of instances with aggregate port connections
ID:14366 SystemVerilog error at <location>: type of assignment pattern doesn't match the expected type
ID:14367 SystemVerilog error at <location>: <string> assignment operator does not support targets with enumeration data types
ID:14368 SystemVerilog error at <location>: can't compare unpacked struct to packed struct
ID:14369 SystemVerilog error at <location>: invalid comparison to a struct
ID:14370 SystemVerilog error at <location>: can't declare an unpacked member inside a packed struct
ID:14371 SystemVerilog error at <location>: assignment patterns on both sides of an assignment is not supported
ID:14372 SystemVerilog error at <location>: enum <string> is not a member of the target constraint
ID:14373 SystemVerilog warning at <location>: ignored extern module declaration with list of ports
ID:14374 SystemVerilog error at <location>: <string> was imported from multiple packages with ::* - none of the imported declarations are visible
ID:14375 SystemVerilog warning at <location>: "<name>" was redeclared with a different number of <string> dimensions
ID:14376 SystemVerilog error at <location>: modport port "<name>" does not correspond to an object in the enclosing interface
ID:14377 SystemVerilog error at <location>: can't declare object <string> with interface type
ID:14378 SystemVerilog error at <location>: can't declare unpacked array with an unpacked element type
ID:14379 SystemVerilog error at <location>: can't declared unpacked array of interfaces
ID:14380 SystemVerilog error at <location>: can't declare interface port with a direction
ID:14381 SystemVerilog error at <location>: interface ports can't have initial values
ID:14382 SystemVerilog error at <location>: task or void function <string> can't return an actual value
ID:14383 SystemVerilog error at <location>: return statement must be inside a task or function
ID:14384 SystemVerilog error at <location>: break or continue statement must be inside a loop
ID:14385 SystemVerilog error at <location>: non-void function <string> must return a value
ID:14386 Verilog HDL error at <location>: block comments cannot be nested
ID:14387 Verilog HDL error at <location>: instantiating unknown module <string>
ID:14388 Verilog HDL error at <location>: present state ':' output field separator misplaced : <string>
ID:14389 Verilog HDL warning at <location>: repetition multiplier must be positive
ID:14390 Verilog HDL error at <location>: <string> in port-expression is not a port
ID:14391 Verilog HDL error at <location>: constant is not allowed here
ID:14392 Verilog HDL error at <location>: function call <string> is not allowed here
ID:14393 Verilog HDL error at <location>: system function call <string> is not allowed here
ID:14394 Verilog HDL error at <location>: <string> is not declared under the prefix "<string>"
ID:14395 Verilog HDL error at <location>: <string> is not a constant
ID:14396 Verilog HDL error at <location>: edge descriptors are invalid here
ID:14397 Verilog HDL error at <location>: <string> <string> cannot be overwritten
ID:14398 Verilog HDL error at <location>: previous syntax error may be due to incorrect attribute placement
ID:14399 Verilog HDL warning at <location>: instantiating unknown empty module <string>
ID:14400 Verilog HDL warning at <location>: actual bit length <number> differs from formal bit length <number>
ID:14401 Verilog HDL warning at <location>: value for attribute <string> is not constant
ID:14402 Verilog HDL warning at <location>: assignment to constant <string>
ID:14403 Verilog HDL error at <location>: constant expression cannot contain a hierarchical identifier
ID:14404 Verilog HDL error at <location>: functions can't contain non-blocking assignments
ID:14405 Verilog HDL error at <location>: functions can't enable tasks
ID:14406 Verilog HDL error at <location>: functions can't contain time-controlled statements
ID:14407 Verilog HDL error at <location>: macro <string> causes infinite loop
ID:14408 Verilog HDL error at <location>: stack overflow on recursion via <string>, limit of <number> has exceeded
ID:14409 Verilog HDL error at <location>: <string> is not a parameter
ID:14410 Verilog HDL error at <location>: multiple event control statements not supported for synthesis
ID:14411 Verilog HDL warning at <location>: external disable constructs not supported for synthesis
ID:14412 Verilog HDL error at <location>: multiple configuration default clauses are not allowed
ID:14413 Verilog HDL error at <location>: loop count limit of <number> exceeded; forever loop never ends
ID:14414 Verilog HDL error at <location>: external reference '<string>' not supported for static elaboration
ID:14415 Verilog HDL error at <location>: checker <string> cannot instantiate <string>, which is not a checker
ID:14416 Verilog HDL error at <location>: instance of checker <string> must have an instance name
ID:14417 Verilog HDL error at <location>: defparam containing interface instance reference '<string>' is not supported for synthesis
ID:14418 Verilog HDL error at <location>: unknown system function call <string> not supported
ID:14420 Verilog HDL error at <location>: range width is larger than 2**<number> bits
ID:14421 Verilog HDL error at <location>: incorrect hierarchical reference within package <string>
ID:14424 Verilog HDL error at <location>: cannot instantiate extern <string> <string>
ID:14425 Verilog HDL error at <location>: <string> is declared as extern and is not fully defined
ID:14426 Verilog HDL error at <location>: instantiating <string> through configuration is not supported
ID:14427 Verilog HDL warning at <location>: mixed blocking and nonblocking assignments on <string>
ID:14429 Verilog HDL error at <location>: body of <string> was not found in the scope where export DPI is declared
ID:14431 Verilog HDL error at <location>: invalid target, bind not done
ID:14432 Verilog HDL error at <location>: parameter with unpacked dimension is only allowed in SystemVerilog
ID:14435 Verilog HDL error at <location>: <string> with non-constant argument is not supported for synthesis
ID:14436 Verilog HDL error at <location>: type must be specified for array parameter <string>
ID:14437 Verilog HDL error at <location>: only assignment pattern can be used to specify valid/invalid values of string parameter '<string>'
ID:14441 Verilog HDL warning at <location>: hierarchical assignment of a variable from another scope or module is not allowed in analog block
ID:14444 Verilog HDL error at <location>: branch terminal should belong to a continuous discipline
ID:14445 Verilog HDL error at <location>: paramset shall not use <string>
ID:14447 VHDL error at <location>: expected an architecture identifier in index
ID:14448 VHDL error at <location>: expected exactly one index specification
ID:14449 VHDL error at <location>: expression is not constant
ID:14450 VHDL error at <location>: no support for selected name assignments to out-of-scope objects
ID:14451 VHDL warning at <location>: pragma <string> not supported ; function ignored
ID:14452 VHDL error at <location>: prefix of attribute <string> should be a discrete or physical (sub)type
ID:14453 VHDL error at <location>: range choice is invalid in assignment target aggregate
ID:14454 VHDL warning at <location>: synthesis ignores all but the first waveform
ID:14455 VHDL error at <location>: partial association in subprogram calls not supported
ID:14456 VHDL error at <location>: signature may not appear in a declaration of an object alias
ID:14457 VHDL error at <location>: base type of object alias declaration must be the same of subtype indication's type mark
ID:14458 VHDL error at <location>: base type of object alias declaration must not be a multi-dimensional array type
ID:14459 VHDL error at <location>: invalid nonobject alias declaration target
ID:14460 VHDL error at <location>: subtype indication may not appear in a nonobject alias declaration
ID:14461 VHDL error at <location>: signature is required if the nonobject alias name denotes a subprogram or enumeration literal
ID:14462 VHDL error at <location>: entity <string> does not have an architecture
ID:14463 VHDL error at <location>: <string> designator <string> cannot contain an actual type-conversion
ID:14464 VHDL error at <location>: actual expression for generic <string> cannot reference a signal
ID:14465 VHDL error at <location>: subprogram type at end of subprogram body does not match specification type '<string>'
ID:14466 VHDL info at <location>: <string> match for '<string>' found here
ID:14467 VHDL error at <location>: cannot access '<string>' from inside pure function '<string>'.
ID:14468 VHDL error at <location>: cannot change working library inside a scope
ID:14469 VHDL warning at <location>: two visible identifiers match <string> because the expected return type is ambiguous; it could be <string> or <string> - assuming <string>
ID:14470 VHDL error at <location>: selected name in use clause is not an expanded name
ID:14471 VHDL error at <location>: prefix <string> for selected name in use clause must refer to a library or package when the selected name's suffix is ALL
ID:14472 VHDL error at <location>: <string> is not a subprogram, a type, or an array object
ID:14473 VHDL warning at <location>: assignments to <string> create a combinational loop
ID:14474 VHDL error at <location>: attribute <string> has an invalid value - <string>
ID:14475 VHDL error at <location>: range in generation scheme must be static
ID:14476 VHDL error at <location>: condition in generation scheme must be a static expression
ID:14477 VHDL error at <location>: unsupported reference to global signal or variable <string>
ID:14478 VHDL error at <location>: prefix for attribute <string> must denote a constrained array type
ID:14479 VHDL error at <location>: cannot synthesize logic for <string> because its value changes on both rising and falling clock edges
ID:14480 VHDL error at <location>: cannot associate a constant with a formal port of mode "<string>"
ID:14481 VHDL warning at <location>: sensitivity list already contains <string>
ID:14482 VHDL error at <location>: can't switch VHDL_INPUT_VERSION inside a scope
ID:14483 VHDL error at <location>: <string> is an invalid value for the VHDL_INPUT_VERSION synthesis directive
ID:14484 Netlist error at <location>: connection from "<name>" to external net "<name>" is not allowed
ID:14485 Netlist error at <location>: connection to external net <string> is not allowed
ID:14486 Can't infer register for "<name>" at <location> because it does not hold its value outside the clock edge
ID:14487 Netlist error at <location>: can't infer register for <string> because it changes value on both rising and falling edges of the clock
ID:14488 Netlist error at <location>: can't infer register for <string> because its behavior depends on the edges of multiple distinct clocks
ID:14489 HDL error at <location>: couldn't implement registers for assignments on this clock edge
ID:14490 <text> port "<name>" at <location> has no fan-out
ID:14491 <text> port "<name>" at <location> has no fan-in
ID:14492 HDL synthesis attribute warning at <location>: the message ID "<id>" specified with the "<name>" attribute is invalid.
ID:14493 HDL synthesis attribute warning at <location>: the "<name>" attribute cannot process the HDL message ID <id>.
ID:14494 Verilog HDL or VHDL warning at <location>: MESSAGE_ON or MESSAGE_OFF directive cannot process the non-HDL message ID <id>.
ID:14495 Can't process assignment. Parameter "<name>" and "<name>" differ only in case in module "<name>".
ID:14496 Verilog HDL warning at <location>: can't infer memory for variable '<name>'. <string>.
ID:14498 Intel Arria 10 devices have specific voltage requirements for <text> pins. Refer to the Intel Arria 10 Device Family Pin Connection Guidelines on the Intel website for detailed information and to find the correct voltage requirements for your pins. Your design contains an illegal voltage assignment of <text> for the <text> pin for HSSI block instance <text>.
ID:14499 HSSI Power Supply value <text> is not allowed for <text> devices. Valid voltage setting is <text> for data rate <text>.
ID:14500 You are in the Incremental Route lock-mode and have attempted to add more nodes than likely allocated with the current compile. Do you wish to continue anyways?
ID:14503 You are currently in the Trigger Only lock-mode and have attempted to add more nodes. This is not allowed, and therefore no nodes will be added.
ID:14504 You are in the Incremental Route lock-mode and have attempted to add one or more Pre-Synthesis nodes. This is not allowed, and therefore no nodes will be added
ID:14505 Node "<name>" of type <name> is part of a DSP chain and has the following incorrect or inconsistent location constraint: <name>
ID:14506 Node "<name>" and "<name>" of type <name> are assigned to the same location <name>.
ID:14507 Design uses <number> DSP blocks, but only <number> DSP blocks are available in the device
ID:14508 Cannot find a common voltage setting for the <text> power supply on transceiver channel(s) using xN routing in the following <number> tiles
ID:14509 Transceiver tile <number> (<text>) allows these voltages after placement: <text>
ID:14510 Transceiver channel <name> placed at <text> (<text>) allows these voltages: <text>
ID:14511 Transceiver xN routing spans tile(s) <number> to <number> with source <name> at <text>
ID:14512 Strictly preserved pin "<name>" is dangling.
ID:14521 WYSIWYG LCELL primitive "<name>" feeds more than one logic cell via carry or cascade chains
ID:14528 Routing resource type "<name>" was listed in RCF "<name>" line <number>, however, this type does not exist on the selected device. The RCF constraint will attempt to match any resource type instead.
ID:14530 <text> is locked to a non-HIP location. The HIP locations are <text>.
ID:14538 Error is not injected - the specified frame location exceeds device <number> total frame count (<number>).
ID:14539 Error is not injected - the specified bit location exceeds device <number> total frame bit count (<number>).
ID:14540 Error is not injected - device <number> currently does not support fault injection to the specified frame location.
ID:14541 Error is not injected - the specified bit location is a phantom bit in device <number>.
ID:14542 The design contains at least 1 block of type "<name>" but the selected device: <name> does not support hard processor system (HPS).
ID:14545 More than one <name> option specified
ID:14546 <name> specified are more than the specified SOF(s)
ID:14547 <name> index specified does not match any SOF(s) index
ID:14550 Can not locate the SFL sof file: <name>
ID:14552 Multiple Partial Reconfiguration regions occupy the <name> region (<number>, <number>) to (<number>, <number>). The combination of these regions uses <number> global signals, but only <number> are available.
ID:14557 File extension (<name>) is not supported for the variation file of the IP megafunction
ID:14558 File '<file name>' already exists. Do you want to overwrite the existing file?
ID:14559 Variation file (<file name>) of the IP megafunction cannot be created
ID:14561 IP Catalog (<text>) failed to launch
ID:14562 Physical Synthesis optimizations will be skipped because the timing analyzer could not be initialized.
ID:14563 The MSF file "<name>" from the static revision compile cannot be located. Partial Reconfiguration region verification will be skipped for <name>
ID:14564 The static MSF file "<name>" cannot be located. Static logic verification will be skipped.
ID:14565 Cannot connect to the Intel FPGA website to check for updates.
ID:14566 The Fitter cannot place <number of failed cells> periphery component(s) due to conflicts with existing constraints <failed cell summary>. Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.
ID:14567 Your design targets the "<family name>" device family. The specified family is not supported in this version of Quartus Prime Software. To find the latest software version that supports specific device families, refer to the <device support list url> on the Intel FPGA website.
ID:14569 Your design targets the "<family name>" device family. The specified family is not supported in this version of Quartus Prime Software. If you restored a project from an archived version, your project was successfully restored, but you still must specify or install a supported device family. To find the latest software version that supports specific device families, refer to the Device Support List (https://fpgasoftware.intel.com/devices) on the Intel FPGA website.
ID:14570 File <file name> does not contain key <key id>.
ID:14573 File name "<name>" does not exist
ID:14574 Failed to setup encryption keys. See the System tab of the Messages window for more details.
ID:14575 I/O "<name>" with "<name>" I/O standard and requiring termination, should connect to an OCT block in POD calibration mode
ID:14576 Cannot make connection because output term is observable output term
ID:14580 The HPS user clock, Cannot connect to the "<name>" clock select
ID:14581 PLL(s) placed in location <name> have multiple different output clock types - the PLL can compensate for only one of these types
ID:14596 Information about the failing component(s):
ID:14598 Locate the messages above in Chip Planner to highlight the affected locations
ID:14600 <name>
ID:14601 <name>
ID:14602 You must successfully run a Full Compilation before running Rapid Recompile
ID:14603 Rapid Recompile could not locate some required database from a previous compilation on disk. Please run a successful Full Compilation before requesting Rapid Recompile Analysis & Synthesis.
ID:14604 Please run Rapid Recompile Analysis and Synthesis (quartus_map --recompile) before running Rapid Recompile Partition Merge.
ID:14605 You have started a Rapid Recompile incremental compilation. Please run a successful Rapid Recompile Partition Merge (quartus_cdb --merge --recompile) to proceed, or start a Full Compilation to abort the Rapid Recompile incremental compilation.
ID:14606 Please run a successful Rapid Recompile Partition Merge (quartus_cdb --merge --recompile) before running Rapid Recompile Fitter.
ID:14607 You have started a Rapid Recompile incremental compilation. Please run a successful Rapid Recompile Fitter (quartus_fit --recompile) to proceed or start a Full Compilation to abort the Rapid Recompile incremental compilation.
ID:14608 You have completed a Rapid Recompile incremental compilation. Please run the Rapid Recompile Fitter to re-iterate your Rapid Recompile incremental compilation, or run Analysis & Synthesis (quartus_map) to start a Full Compilation.
ID:14609 You have attempted to run Rapid Recompile Fitter (quartus_fit --recompile) while in a Full Compilation. Please run the Full Compilation Fitter or start a Rapid Recompile incremental compilation.
ID:14610 IP Variation Editor (<text>) failed to launch
ID:14611 File extension (<name>) is not supported for the IP variation files
ID:14612 File '<file name>' already exists. Do you want to overwrite the existing file?
ID:14614 Variation file (<file name>) of the IP megafunction cannot be created
ID:14615 The Intel FPGA server is currently unable to service the update request. Please request an update again later. If available, previously cached information will be used.
ID:14616 The Clock Control Block <name> of type "Periphery Clock" cannot have its enable port connected
ID:14619 The Clock Control Block <name> of clock type "<text>" cannot have its enable port connected
ID:14620 Platform Designer is not installed or could not be found
ID:14621 Platform Designer (<text>) failed to launch
ID:14622 File extension (<name>) is not supported by Platform Designer
ID:14623 File '<file name>' already exists. Do you want to overwrite the existing file?
ID:14624 Platform Designer file (<file name>) cannot be created
ID:14625 Platform Designer is not installed or could not be found
ID:14626 Platform Designer (<text>) failed to launch
ID:14627 File extension (<name>) is not supported by Platform Designer
ID:14628 File '<file name>' already exists. Do you want to overwrite the existing file?
ID:14629 Platform Designer file (<file name>) cannot be created
ID:14631 Unable to find a legal periphery placement
ID:14632 Output pin "<name>" driven by bidirectional pin "<name>" cannot be tri-stated
ID:14633 Can't connect TRI or OPNDRN primitive "<name>" to pin "<name>" because primitive is already connected to bidirectional pin "<name>"
ID:14638 Input buffer atom "<name>" has port "<name>" connected to a termination logic block
ID:14639 Input buffer atom "<name>" has port "<name>" connected to a termination logic block. Fitter expects this port to be disconnected.
ID:14640 Ena port of Clock Buffer Block "<name>" is connected to GND.
ID:14641 Outclk port of Clock Buffer Block "<name>" drives inclk port of <text> "<name>", but must not drive an inclk port of a <text>
ID:14642 The Clock Control Block <name> of clock type "<text>" cannot have its enable port connected
ID:14643 Illegal value "<text>" for ena_register_mode parameter in Clock Enable Block "<name>" -- value must be <text> when the ena input is used and the clock type is "<text>".
ID:14644 Inclk port of Clock Buffer Block "<name>" is driven by an illegal source, but must be driven by a PLL clock output because CLOCK_TYPE parameter is set EXTERNAL_CLOCK_OUTPUT
ID:14645 Inclk port of Clock Buffer Block "<name>" must be used
ID:14646 Clock Buffer Block "<name>" with clock_type "Auto" is automatically promoted to "Global Clock" because the ENAOUT port is connected.
ID:14647 ENAOUT port of Clock Buffer Block is not supported for clock_type "<clock type>".
ID:14648 outclk port of Clock Control Block "<name>" with CLOCK_TYPE parameter set to EXTERNAL_CLOCK_OUTPUT drives <name>, but must drive an unregistered pin
ID:14649 outclk port of External Clock Output Clock Buffer Block "<name>" must drive 1 output pin, but drives <number> output pin(s)
ID:14650 Fitter found illegal HSSI <name> data pin connection at <name>
ID:14651 inclk[<number>] port of Clock Select Block "<name>" is driven by <name>, but must be driven by <text>
ID:14652 Inclk port(s) <text> of Clock Select Block "<name>" must be used
ID:14654 <text> port(s) of Clock Select Block "<name>" can be selected but is/are not connected.
ID:14655 Can't select inclk[<number>] port of Clock Select Block "<name>"
ID:14656 Termination atom "<name>" cannot be merged. Parameter A_OCT_CAL_MODE is set to an incompatible value
ID:14657 Termination atom "<name>" cannot be merged. Parameter A_OCT_USR_MODE is set to an incompatible value
ID:14658 DSP block WYSIWYG primitive "<name>" does not have its chainout port "<name>" connected to the correct chainin port in this DSP mode
ID:14661 Generated JSON formatted report files in <report_dir>
ID:14662 The full compiler report upload to <url> has finished.
ID:14663 The full compiler reports are being uploaded to the Notification Center server ...
ID:14666 WYSIWYG primitive <name> has missing connection on input port <name>
ID:14667 Ignored following assignments for SYNTH_CRITICAL_CLOCK
ID:14668 Ignored following assignments for SYNTH_CRITICAL_CLOCK for hierarchy "<name>"
ID:14669 Ignored following assignments for SYNTH_CRITICAL_CLOCK for partition "<name>"
ID:14670 Ignored assignment for SYNTH_CRITICAL_CLOCK from clock "<name>" to clock "<name>" -- no registers were found for clock "<name>"
ID:14671 Ignored assignment for SYNTH_CRITICAL_CLOCK for clock "<name>" -- no registers were found for this clock
ID:14672 Ignored following assignments for SYNTH_CRITICAL_INPUT_TO_CLOCK
ID:14673 Ignored following assignments for SYNTH_CRITICAL_INPUT_TO_CLOCK for hierarchy "<name>"
ID:14674 Ignored following assignments for SYNTH_CRITICAL_INPUT_TO_CLOCK for partition "<name>"
ID:14675 Ignored assignment for SYNTH_CRITICAL_INPUT_TO_CLOCK for clock "<name>" -- no registers were found
ID:14676 Ignored following assignments for SYNTH_CRITICAL_CLOCK_TO_OUTPUT
ID:14677 Ignored following assignments for SYNTH_CRITICAL_CLOCK_TO_OUTPUT for hierarchy "<name>"
ID:14678 Ignored following assignments for SYNTH_CRITICAL_CLOCK_TO_OUTPUT for partition "<name>"
ID:14679 Ignored assignment for SYNTH_CRITICAL_CLOCK_TO_OUTPUT for clock "<name>" -- no registers were found
ID:14680 Ignored following assignments for SYNTH_CRITICAL_ENABLE
ID:14681 Ignored assignment for SYNTH_CRITICAL_ENABLE for register "<name>" -- register not found
ID:14682 Ignored following assignments for SYNTH_CRITICAL_PIN
ID:14683 Ignored assignment for SYNTH_CRITICAL_PIN for pin "<name>" -- pin not found
ID:14684 Cannot translate WYSIWYG DLL "<name>" in <name> mode to family <name> because it is not in normal mode
ID:14685 Cannot translate WYSIWYG DQS I/O "<name>" to family <name> because it is not in BYPASS mode nor is all of its delayctrlin inputs directly fed by a WYSIWYG DLL
ID:14686 WYSIWYG DLL "<name>" has delay chain length of <number>, but the recommended delay chain length in <name> with a <number> MHz clock is <number>. The compiler will use the recommended delay chain length.
ID:14687 DQS WYSIWYG "<name>" has delay chain length of <number>, but the recommended delay chain length in <name> is <number>. The compiler will use the recommended delay chain length to achieve a phase shift of <number> degrees.
ID:14688 Cannot translate WYSIWYG Clock Delay Control "<name>" to family <name> because it is not in static or none mode
ID:14689 Cannot translate the phase shift of DQS I/O WYSIWYG "<name>" to family <name> because it's using the custom phase shift value of <number> (expected phase shift setting of <number>)
ID:14690 WYSIWYG I/O Input Buffer primitive "<name>" uses bus hold function and is not connected properly. The Quartus Prime software will unmap the illegal buffer and ignore the bus hold property.
ID:14691 WYSIWYG I/O Output Buffer primitive "<name>" uses bus hold function and is not connected properly. The Quartus Prime software will unmap the illegal buffer and ignore the bus hold property.
ID:14692 I/O WYSIWYG "<name>" will have different synchronous clear/preset behavior after translated to family <name>.
ID:14693 Timing-Driven Synthesis is skipped because the Synthesis Effort is set to Fast
ID:14694 Timing-Driven Synthesis is running
ID:14695 Timing-Driven Synthesis is running on partition "<name>"
ID:14696 Parameter <text> set to <text>
ID:14697 Cannot find Memory Initialization File or Hexadecimal (Intel-Format) File <name> for ROM instance <name>
ID:14698 Both TX channel <text> and RX channel <text> must be a GT channel.
ID:14701 No clock path found through PLL "<name>".
ID:14702 No data path found to register "<name>" when PLL "<name>" is used in source synchronous mode.
ID:14704 The following DSP blocks form a DSP chain of length <number>. Maximum allowed DSP chain length on the current device is <number>.
ID:14709 <propagation>
ID:14710 The <type> is constrained<text>
ID:14711 Rapid Recompile is not supported in the Quartus Prime Lite Edition Software.
ID:14713 Atom "<name>" cannot have both comb_out and carry_out ports in use at the same time
ID:14714 The Fitter is having difficulty fitting the design. Try increasing the "Auto Packed Register" setting under "Advanced Fitter Settings" to minimize area.
ID:14717 Physical Synthesis optimizations will be skipped because the timing analyzer could not be initialized.
ID:14736 <received data from a launched IP wizard process>
ID:14737 <received data from a launched IP wizard process>
ID:14738 <received data from a launched IP wizard process>
ID:14739 Atom "<name>" has illegal value for MIN_VALID_ADDR and MAX_VALID_ADDR parameters.
ID:14740 <name> on atom "<name>" does not match the project setting. Update and regenerate the Platform Designer system to match the project setting.
ID:14741 Instantiation of "<name>" is incompatible with Quartus Prime. Using the megawizard to instantiate the specified atom.
ID:14744 Input register for "<name>" and "<name>" for atom "<name>" must be used and use the same clock setting when scan chain is enabled.
ID:14746 Physical PLL parameters cannot be found to satisfy the output frequency constraints of generic PLL "<name>".
ID:14747 Physical PLL parameters cannot be found to satisfy the phase shift constraints of generic PLL "<name>".
ID:14748 Physical PLL parameters cannot be found to satisfy the duty cycle constraints of generic PLL "<name>".
ID:14749 Illegal reference clock frequency on generic PLL "<name>".
ID:14752 Following EMIF/PHYLite pins have incompatible <voltage requirement> requirements.
ID:14753 Pin: <pin name>, <voltage requirement> requirement: <requirement value>
ID:14754 One or more blocks are configured incorrectly and might not have the desired functionality.
ID:14755 One or more blocks are configured incorrectly and might not have the desired functionality.
ID:14757 The PR bitstream ID is <prpof_id_hex_string>
ID:14760 Bitstream for Custom Trigger HDL module: "<name>" contains illegal characters. Remove the illegal characters or restore your Signal Tap File to its original state. The bitstream can contain only the characters: 0 and 1
ID:14761 Specifies a runtime configurable bit string that will be fed to the 'pattern_in' input of your custom trigger HDL. The length of your bit string should match the width of your 'pattern_in' input of your module, and should only contain the characters '1' and '0'. An empty bit string implies a module without a 'pattern_in' input.
ID:14762 Specifies the module name of the custom trigger HDL.
ID:14862 Custom Trigger HDL object is missing required 'Module Name' parameter. Add the module name.
ID:14863 Specify a variation file name
ID:14864 Select an available megafunction
ID:14865 Output file name cannot consist of space or tab characters
ID:14866 Found illegal characters in the output file name. File names can contain only underscore, tilde, and alphanumeric characters.
ID:14867 Found illegal characters in the output file name. File names must start with a letter, cannot end with an underscore (_), and cannot contain two underscores (_ _) in a row. No slash (/) or dash (-) is permitted.
ID:14868 Variation file name is a Quartus Prime reserved module name. Using such names may lead to unexpected or erroneous results. Do you want to change the file name?
ID:14869 Specify a valid MegaWizard-generated variation file
ID:14870 Illegal or missing filename extension. Use only filename extension .tdf, .vhd, or .v
ID:14871 MegaWizard Plug-In <name> is not supported by the selected device family
ID:14872 Directory <directory> does not exist.
ID:14873 You do not have write permission for directory <directory>.
ID:14874 The specified reference clock frequency is illegal. The legal reference clock frequency range is <min refclk frequency> MHz to <max refclk frequency> MHz.
ID:14875 The specified configuration causes Phase Frequency Detector (PFD) to go beyond the limit (<min pfd frequency> MHz to <max pfd frequency> MHz).
ID:14876 The specified configuration causes Voltage-Controlled Oscillator (VCO) to go beyond the limit (<min vco frequency> MHz to <max vco frequency> MHz).
ID:14877 Please enter legal values for output clock frequencies.
ID:14878 Please enter legal values for output clock phase shifts.
ID:14879 Please enter legal values for output clock duty cycles.
ID:14880 The second reference clock has an illegal reference clock frequency. The legal reference clock frequency range is <min refclk frequency> MHz to <max refclk frequency> MHz.
ID:14881 The second reference clock frequency generates an illegal VCO frequency. Please change the PLL settings or the 'refclk1' frequency to rectify this issue.
ID:14882 The second reference clock frequency generates an illegal PFD frequency. Please change the PLL settings or the 'refclk1' frequency to rectify this issue.
ID:14884 Verilog HDL Module Instantiation error at <location>: module instance port connections cannot be mixed -- port connections must be all by order or all by name
ID:14885 The second reference clock frequency is illegal for this PLL configuration.
ID:14886 Could not create a legal PLL from requested user settings.
ID:14887 Can't pack register into I/O input cell <name> -- the I/O input buffer fans out to multiple nodes, but the fanout must be to exactly one register node.
ID:14890 Compilation now being tracked on the Intel FPGA Notification Center. Tracking URL: <url>
ID:14891 I/O "<name>" uses dynamic termination control, but the dynamic termination control is used for bidir pins only
ID:14892 Interface Planner failed initialization.
ID:14894 This signal is currently using <string>, with the buffer placed at <string>
ID:14895 Fitter has disabled Advanced Physical Optimization due to complicated Logic Lock region settings on region: <name>.
ID:14896 Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
ID:14897 The bidirectional pin "<name>" is fed by an output buffer and regular tri-stated logic
ID:14898 Create CvP files option is enabled in the specified Conversion Setup File. However, this option will be disabled as the current SOF file loaded does not have CvP feature enabled.
ID:14899 Current design SOF does not support CvP. Unable to enable "Create CvP Files" checkbox. See the System tab of the Messages window for more details.
ID:14900 <name>
ID:14901 No legal physical settings could be found for generic PLL "<name>".
ID:14902 Failed to convert generic PLL "<name>" to physical PLL.
ID:14903 The following regions are not compatible given the current clock driver placement
ID:14904 Rapid Recompile skipped module <name> because it is not required
ID:14905 Device is not supported by this megafunction
ID:14907 <key> not found.
ID:14909 Key2 will be ignored as device only supports one encryption key.
ID:14910 <key> not found.
ID:14911 Key2 will be ignored as device only supports one encryption key.
ID:14912 Physical parameters may differ slightly between generic PLL "<name>" and its corresponding physical PLL.
ID:14913 Interface Planner failed autoplacement of all unplaced cells.
ID:14914 Interface Planner failed to unplace all cells.
ID:14915 SOPCINFO file <name> is invalid, with issue "<text>"
ID:14917 The current Interface Planner floorplan is invalid.
ID:14921 Error upgrading IP component "<file>".
ID:14922 Error upgrading "<file>" to Platform Designer file
ID:14923 Error upgrading Platform Designer file "<file>"
ID:14924 Interface Planner failed to autoplace all fixed cells.
ID:14926 You have attempted to add more than the maximum number of nodes (<width>) to the current Signal Tap instance.
ID:14943 The remote compilation farm you specified, <name>, is not a valid compute farm. Changing the compilation type to a local compilation. To run remote compilations, select a supported compute farm.
ID:14945 The exploration type you specified, <name>, is not a supported exploration type. Changing the exploration type to <default>. To perform a different type of analysis, select a supported exploration type.
ID:14946 Unable to place DM pin adjacent to a DQ pin. Constrain the DM pin and a DQ pin to I/O locations that form a differential pair
ID:14947 DM pin: <DM pin name>
ID:14949 The number of concurrent compilations you specified, <number>, is not supported. Changing the maximum number of concurrent compilations to <number>. To run a different number of concurrent compilations, select a number of concurrent compilations, up to <number>.
ID:14951 The Fitter is using Advanced Physical Optimization.
ID:14958 Invalid partition "<name>" specified for block import.
ID:14959 Device part "<name>" is invalid.
ID:14960 Family "<name>" is invalid.
ID:14961 The device "<name>" is not valid as not all the required device files are installed.
ID:14962 Use of the AUTO device part is not supported for family <family>. Ensure a valid device part is selected before running the Fitter.
ID:14963 Analysis and Synthesis (quartus_syn) must be run using the device family <name> before running the Fitter (quartus_fit) with device part <name>.
ID:14964 Analysis and Synthesis (quartus_map) must be run using device family <name> before running the Fitter (quartus_fit).
ID:14965 Interactive use of the Fitter (quartus_fit) is not supported using the device family <name>.
ID:14966 Invalid partition "<name>" specified for block implementation.
ID:14967 Warning! You are specifying that this computer perform more than one compilation simultaneously. Performing more than one compilation requires significant computing power, memory resources, and additional Quartus Prime licenses. If you experience problems exploring <num_concurrent> points simultaneously, reduce the number of concurrent compilations to free resources and improve performance.
ID:14968 The design contains an USB Interface: "<name>" but the selected device does not have an USB connection to the FPGA
ID:14981 Data rate of driving PLL PLL:< <text> > and HSSI channel < <text> > do not match. The PLL output frequency must match the HSSI channel data rate or the design may fail on the device. Change either the PLL output frequency to <number> MHz, or the HSSI channel data rate to <number> Mbps.(pll_freq == data_rate/2 * cgb_div_factor * master_div_factor)
ID:14982 Cannot generate mask for empty strictly preserved region "<name>"
ID:14983 Cannot generate mask for empty strictly preserved region "<name>"
ID:14984 Can't open Technology Map Viewer (Post-Hyper-Retiming) -- Hyper-Retiming netlist not available
ID:14986 After placing as many components as possible, the following errors remain:
ID:14987 The following components had the most difficulty being legally placed:
ID:14988 Find multiple PLLs driving <number> master CGB(s) for PMA or PMA/PCS bonding channel.
ID:14989 Can't create file (<name>) because path exceeds 260 character limit
ID:14991 Legal locations were never found for the following <number> component(s):
ID:14992 Start Rapid Recompile to continue
ID:14993 Perform normal compilation and Hyper-Retimer before opening the Technology Map Viewer (Post-Hyper-Retiming).
ID:14994 <name> does not support address beyond <name>Mb
ID:14995 <name> does not support burst read across different flash die.
ID:14996 The Fitter failed to find a legal placement for all periphery components
ID:14997 The FPGA to HPS SDRAM PLL reference clock path is not timing analyzed and could be subject to jitter.
ID:14998 EMIF/PHYLite systems connected together with the following io_aux atoms have identical interface IDs. Change the interface ID of one of the interfaces.
ID:14999 Atom: <IO_AUX atom name> (Interface ID: <interface ID>)
ID:15000 "<name>" is a legal value
ID:15001 Assignment <name> of value "<name>" conflicts with the valid values of the parameter "<name>" on instance "<name>"
ID:15002 Assignment <name> of value "<name>" conflicts with the protocol specified in the PCS instance "<name>" parameter "<name>" with a value of "<name>"
ID:15003 "<name>" parameter of RAM atom <name> cannot have value "<name>" when different read and write clocks are used.
ID:15004 Can't find the legal settings for PLL node "<name>" with reference clock frequency "<name>" and output clock frequency "<name>" because ES silicon LC 14G VCO High Gear is not currently supported.
ID:15005 Assigned value of QSF variable "<name>" on instance "<name>" is negative <number>, but this property requires a positive value.
ID:15006 RAM atom "<name>" uses different clocks for input registers on "<name>"
ID:15007 RAM atom "<name>" in operation mode "<name>" uses unsupported parameter value combination for "<name>" and "<name>"
ID:15008 MLAB "<name>" on port "<name>" has illegal width "<number>". The correct width is "<number>"
ID:15009 MLAB "<name>" has ROM connection configuration but with write related ports connected
ID:15010 MLAB "<name>" is implementing memory in a non-ROM mode, but the port "<name>" is not connected
ID:15011 <name> can have only a maximum of <number> bits
ID:15012 <name> MLAB can have only a maximum of <number> address width
ID:15013 <name> can have only a maximum of <number> data width
ID:15014 Atom <name> is using true differential input buffer without setting the <name> parameter to TRUE
ID:15015 Atom <name> has <name> parameter set to TRUE without using true differential input buffer.
ID:15016 Atom "<name>" has mismatched parameters for port "<name>"
ID:15017 Atom "<name>" has an invalid parameter width. The valid width is 2, 4, or 8.
ID:15018 Parameter width for port "<name>" and port "<name>" are not equal on atom "<name>"
ID:15019 Port "<name>" on atom "<name>" must be connected
ID:15020 Atom "<name>" has an extra clock enable connected
ID:15021 clr port on atom "<name>" must be connected
ID:15022 clr0 port on atom "<name>" must be connected
ID:15023 clr1 port on atom "<name>" must be connected
ID:15024 Input port <name> of node "<name>" is <text>
ID:15025 Can't implement CLK<number>_MULTIPLY_BY parameter with value <number> and CLK<number>_DIVIDE_BY parameter with value <number> for GXB transmitter PLL "<name>"
ID:15026 PLL "<name>" has parameter <name> with illegal value <number> -- value must be between <number> and <number>
ID:15027 PLL "<name>" has parameter <name> with illegal value <number> -- value must be an increment of <number>
ID:15028 <name> "<name>" has parameter <name> with illegal value <number> -- only value <number> is legal
ID:15029 PLL "<name>" has parameter <name> with illegal value <number> -- only value <number> is legal
ID:15030 PLL "<name>" has parameter <name> with an illegal value -- only value <number> is legal
ID:15031 PLL "<name>" has parameter <name> with illegal value <number> -- value must be one of the <number> legal values
ID:15032 Primitive <name> "<name>" has parameter <name> with illegal value <number> -- value must be one of the <number> legal values
ID:15033 PLL "<name>" has parameter <name> with an illegal value -- value must be one of the <number> legal values
ID:15034 Parameter <name> has legal values of <text>
ID:15036 PLL "<name>" is using external feedback, but none of the PLL output clocks are connected to a pin
ID:15037 PLL "<name>" uses fbin input port, but OPERATION_MODE parameter of PLL must be set to EXTERNAL_FEEDBACK
ID:15038 PLL "<name>" uses automatic switchover features, but SWITCH_OVER_TYPE parameter is set to MANUAL
ID:15039 Input clock pin "<name>" (feeds inclk port of enhanced PLL "<name>") and output pin "<name>" (the compensated clock output) have different I/O standards, <name> and <name>
ID:15040 Output clock clk[<number>], which is the compensated clock output of PLL "<name>", uses a cascaded counter, and so it is not fully compensated
ID:15041 Output of PLL "<name>" (feeds DLL only) does not require compensation
ID:15042 The input clock frequency specification of PLL "<name>" is different from the output clock frequency specification of the source PLLs that are driving it
ID:15043 Input port inclk[<number>] of PLL "<name>" and its source clk[<number>] (the output port of PLL "<name>") have different specified frequencies, <number> and <number> respectively
ID:15044 PLL "<name>" has SWITCH_OVER_TYPE parameter set to MANUAL, but clkswitch port is not connected
ID:15045 PLL "<name>" uses inclk0 and inclk1 ports, but clkswitch port is not connected
ID:15046 PLL "<name>" has clkswitch port stuck at VCC or GND
ID:15047 PLL "<name>" uses clkswitch port, but inclk[<number>] port is not used
ID:15048 Fast PLL "<name>" uses automatic switchover, but fast PLLs do not support automatic switchover
ID:15049 PLL "<name>" uses counter <name> for clk[<number>] output port and counter <name> for enable[<number>] output port, but both output ports must use the same counter
ID:15050 LVDS PLL "<name>" parameters VCO_MULTIPLY_BY and VCO_DIVIDE_BY are required but missing
ID:15051 Enhanced PLL "<name>" uses LVDS features, but enhanced PLLs do not support LVDS
ID:15052 LVDS PLL "<name>" was converted to a regular PLL because it does not feed an LVDS receiver or transmitter
ID:15053 PLL "<name>" COMPENSATE_CLOCK port <name> must feed an output pin when OPERATION_MODE is set to ZERO_DELAY_BUFFER
ID:15054 PLL "<name>" has port <name> that can only feed port <name> on an LVDS receiver or transmitter WYSIWYG
ID:15055 PLL "<name>" input clock inclk[<number>] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input
ID:15056 PLL "<name>" input clock inclk[<number>] may have reduced jitter performance because it is fed by a non-dedicated input
ID:15057 PLL "<name>" input clock inclk[<number>] may have reduced jitter performance because it is fed by a non-dedicated input
ID:15058 PLL "<name>" is in normal or source synchronous mode with output clock "<name>" set to clk[<number>] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins
ID:15059 Settings for PLL "<name>" may result in significant clock output drift over process, voltage or temperature variations
ID:15060 Can't use dynamic reconfiguration with PLL "<name>"
ID:15061 DSP block WYSIWYG primitive "<name>" scan chain feature is not supported for the current device in this DSP mode.
ID:15062 PLL "<name>" in Source Synchronous mode with compensated output clock set to clk[<number>] is not fully compensated because it does not feed an I/O input register
ID:15063 PLL "<name>" in <name> mode with <name> set to clk[<number>] is not fully compensated because it does not feed a dedicated PLL clock output pin
ID:15064 PLL "<name>" output port <name> feeds output pin "<name>" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
ID:15065 Clock input port inclk[<number>] of PLL "<name>" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block
ID:15066 Clock input port inclk[<number>] of PLL "<name>" must be driven by a non-inverted input clock pin
ID:15067 Input pin "<name>", which feeds fbin port of enhanced PLL "<name>", and output pin "<name>", which will be compensated by this PLL, have different I/O standards <name> and <name>
ID:15068 Input pin "<name>", which feeds inclk[<number>] port of enhanced PLL "<name>", and output pin "<name>", which will be compensated by this PLL, have different I/O standards <name> and <name>
ID:15069 PLL "<name>" has self-reset on loss of lock turned on. However, no value is specified for the gated lock counter.
ID:15070 PLL "<name>" uses test-only port <name>
ID:15071 Termination atom "<name>" uses test-only port <name>
ID:15072 Generated scan chain Memory Initialization File <name> for PLL "<name>"
ID:15073 Overwrote scan chain Memory Initialization File <name> for PLL "<name>"
ID:15074 Scan chain Memory Initialization File <name> for PLL "<name>" not found
ID:15075 The contents of the scan chain Memory Initialization File <name> for PLL "<name>" do not match the initial state of the scan chain for the PLL
ID:15076 The value for the <name> parameter does not match the value of the initial state of the scan chain for the PLL
ID:15077 The number of bits in the scan chain Memory Initialization File does not match the number of bits in the scan chain for the PLL node
ID:15078 The data word size of the scan chain Memory Initialization File is <number>. The expected data word size is <number>.
ID:15079 The value in the parameter value source <parameter value source>: <parameter value>
ID:15080 The number of bits in the source <source>: <number of bits>
ID:15081 Implementing parameter values for PLL "<name>"
ID:15082 Implemented clock multiplication and clock division parameter values, but can't implement phase shift parameter values for PLL "<name>"
ID:15083 Can't implement duty cycle parameter values for PLL "<name>" -- implemented clock multiplication, clock division, and clock phase shift parameter values
ID:15084 Output clock port <name> of PLL "<name>" uses time delay
ID:15085 Pin "<name>" uses I/O standard <name>, but the PCI I/O logic option is set to OFF
ID:15086 Values of parameter <name> and <name> of PLL "<name>" must both be 1 or neither should be 1
ID:15087 Can't configure PLL "<name>" because the <name> feature is not used correctly or should not be used on the PLL
ID:15088 Output of PLL "<name>" cannot be connected to its own clock input
ID:15089 QSF Assignments for tx PLLs are now ignored. The following pll will be defaulted to type 'CMU' NOT type 'LC': "<name>".
ID:15090 Changed operation mode of PLL "<name>" to <name>
ID:15091 Can't implement PLL with delay chain setting values
ID:15092 Can't achieve requested clock multiplication and clock division parameter values for PLL "<name>" -- Quartus Prime software achieved the closest possible values
ID:15093 Can't implement clock multiplication and clock division parameter values for PLL "<name>"
ID:15094 Can't implement PLL because <text>
ID:15095 Implemented <name> for PLL "<name>"
ID:15096 Can't implement PLL "<name>"
ID:15097 Can't implement PLL "<name>" of type <name> -- current design requires different PLL type
ID:15098 Can't implement PLL "<name>" with speed grade of target device -- PLL "<name>" may be implemented with faster speed grade
ID:15099 Implementing clock multiplication of <number>, clock division of <number>, and phase shift of <number> degrees (<number> ps) for <name> port
ID:15100 Implementing clock multiplication of <number> and clock division of <number> for <name> "<name>"
ID:15101 Implementing clock multiplication of <number> and clock division of <number>
ID:15102 QSF Assignments for tx plls are now ignored. The following pll will be defaulted to type 'LC' NOT type 'CMU': "<name>".
ID:15103 LC PLL in channel <number> is not supported for reconfiguration. TX PLL MIF is not created for this channel.
ID:15104 Quartus Prime software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design.
ID:15105 Atom "<name>" has a clear port connection without a clock signal
ID:15106 Atom "<name>" has a clock enable without a clock signal
ID:15107 Atom "<name>" has an extra clock connected
ID:15108 Atom "<name>" has an extra clear port connected
ID:15109 Cannot find PHY IP instance. MIF file is not generated for atom <name>.
ID:15110 clk1 port on the WYSIWYG primitive "<name>" must be connected
ID:15111 External feedback input port of PLL "<name>" must be driven by input pin
ID:15112 Hard IP for PCI Express block < <text> > uses Configuration via Protocol (CvP). The Fitter cannot find a TX PLL connected to the RXPMARSTB pins of the Hard IP for PCIe block. If you are using an ES device, disable CvP. If you are using a production device, add a hard reset controller.
ID:15113 Arria 10 DSP block WYSIWYG primitive "<name>" does not support "NEGATE" for the target device.
ID:15115 Clock buffer <name> drives another clock buffer <name>
ID:15118 datain port of HSDI receiver atom "<name>" must be fed by input pin that does not feed any other logic
ID:15119 LVDS receiver or transmitter atom "<name>" has value <number> that is not within legal range for <name> parameter
ID:15120 LVDS receiver or transmitter atom "<name>" has value <number> that is not within legal range for CHANNEL_WIDTH parameter
ID:15123 The following <src> locations cannot route to all the required <dst>s
ID:15130 User specified different group names for the same Transceiver Avalon Memory-Mapped interface "<text>".
ID:15132 Assignment "<text>" is set to Transceiver Avalon Memory-Mapped interface group "<text>".
ID:15133 Assignment "<text>" is set to Transceiver I/O Pin "<text>".
ID:15134 You specified location assignments for transceiver Avalon Memory-Mapped interface group"<text>". If the Fitter reports placement errors for the merged transceiver Avalon Memory-Mapped interface, check whether the two locations map to the same physical transceiver channel.
ID:15135 Transceiver Avalon Memory-Mapped interface group "<text>" specified for the first transceiver Avalon Memory-Mapped interface "<text>".
ID:15136 Transceiver Avalon Memory-Mapped interface group "<text>" specified for the second transceiver Avalon Memory-Mapped interface <text>.
ID:15148 GXB transmitter channel atom "<name>" must have source at input port <name>
ID:15149 GXB transmitter channel atom "<name>" must have source at input port <name>[<number>]
ID:15150 datain input port with value <number> of the GXB transmitter channel atom "<name>" must be the same width as CHANNEL_WIDTH parameter with value <number>
ID:15151 input port <name> of GXB transmitter channel atom "<name>" must be fed by CLK<number> port of GXB transmitter PLL
ID:15152 GXB transmitter channel atom "<name>" must have source at input port <name>[<number>] when in 8B/10B mode
ID:15153 GXB transmitter channel atom "<name>" cannot use input port <name>[<number>] when not in 8B/10B mode
ID:15155 GXB transmitter channel atom "<name>" cannot use input port <name>[1] when not in double data mode
ID:15156 GXB transmitter channel atom "<name>" must have source at input port <name>[<number>] when in force disparity mode
ID:15157 GXB transmitter channel atom "<name>" cannot use input port <name>[<number>] input port when not in force disparity mode
ID:15158 Input port <name> of GXB transmitter channel atom "<name>" must be fed by an input pin that also feeds the DATAIN port of a GXB receiver channel atom
ID:15159 serialdatain input port of GXB transmitter channel atom "<name>" must be fed by an input pin when slpbk input port is used
ID:15160 xgmdatain[<number>] input port of GXB transmitter channel atom "<name>" must be fed by txdataout[<number>] output port of XGMII state machine atom
ID:15161 xgmctrl input port of GXB transmitter channel atom "<name>" must be fed by txctrlout output port of XGMII state machine atom
ID:15162 dataout port of GXB transmitter channel atom "<name>" must fan out to only one output pin
ID:15163 GXB transmitter channel atom "<name>" cannot use output port <name> when in 8B/10B mode
ID:15164 GXB transmitter channel atom "<name>" cannot use output port <name>[<number>] when in 8B/10B mode
ID:15165 Output port <name> of GXB transmitter channel atom "<name>" must connect to input port <name> of XGMII state machine atom
ID:15166 output port <name>[<number>] of GXB transmitter channel atom "<name>" must connect to input port <name>[<number>] of XGMII state machine atom
ID:15167 GXB transmitter channel atom "<name>" cannot use rdenablesync output port when not in channel 0
ID:15168 output port <name>[<number>] of GXB transmitter channel atom "<name>" must connect to input port <name>[<number>] of a GXB receiver channel atom
ID:15169 GXB transmitter channel atom "<name>" must have output port <name> with size <number> when in 8B/10B mode
ID:15172 coreclk input port frequency <number> of GXB transmitter channel atom "<name>" must be in the frequency range of <number> to <number>
ID:15173 Input port <name> of GXB transmitter channel atom "<name>" must connect to output port <name>[<number>] of an XGMII state machine atom
ID:15174 Illegal port connection -- input port <name> of GXB transmitter channel atom "<name>" cannot be connected because <text>
ID:15175 GXB transmitter channel atom "<name>" cannot use input port <name> when in self test mode
ID:15176 GXB transmitter channel atom "<name>" is in reverse parallel loopback mode, but is driven by GXB receiver channel atom "<name>", which is not in reverse parallel loopback mode
ID:15177 Input port <name> of GXB transmitter channel atom "<name>" must connect to output port <name> of a GXB receiver channel atom when in reverse parallel loopback mode
ID:15178 Input port <name>[<number>] of XGMII state machine atom "<name>" must connect to output port <name>[<number>] of atom "<name>" in channel <number>
ID:15179 Output port <name>[<number>] of XGMII state machine atom "<name>" must connect to input port <name>[<number>] of atom "<name>" in channel <number>
ID:15180 Input port <name>[<number>] of XGMII state machine atom "<name>" must connect to output port <name> of atom "<name>" in channel <number>
ID:15181 Output port <name>[<number>] of XGMII state machine atom "<name>" must connect to input port <name> of atom "<name>" in channel <number>
ID:15182 Output port <name>[<number>] of XGMII state machine atom "<name>" must connect to input port <name> of atom "<name>" in channel <number> -- if the configuration was instantiated with the MegaWizard Plug-In Manager, this error can occur when no outputs of the atom "<name>" are connected in the design
ID:15183 Input port <name> of XGMII state machine atom "<name>" must connect to output port <name> of atom "<name>" in channel 0
ID:15184 Output port <name> of XGMII state machine atom "<name>" must connect to input port <name> of atom "<name>"
ID:15185 Port <name> of XGMII state machine atom "<name>" has width of <number>, but must have width of <number>
ID:15186 Port <name> of XGMII state machine atom "<name>" has a width of <number>, which exceeds the maximum allowed width of <number>
ID:15187 XGMII state machine atom "<name>" must have source at input port <name>
ID:15188 Input port <name> of XGMII state machine atom "<name>" must be fed by CLK<number> of GXB transmitter PLL
ID:15189 RESETALL input port of XGMII state machine atom "<name>" cannot be connected
ID:15190 Illegal port connection -- port <name> of XGMII state machine atom "<name>" cannot be connected
ID:15191 Input port <name> of XGMII state machine atom "<name>" must be connected only to an input pin
ID:15192 Input pin "<name>" feeds pllenable input port of XGMII state machine atom "<name>" and other logic, but input pin "<name>" can't feed other logic
ID:15193 Current design uses PLL enable input pin "<name>" and PLL enable input pin "<name>", but only one PLL enable input pin can be used in <name> device family
ID:15194 clock0 output port of GXB transmitter PLL "<name>" must connect only to fastpllclk port of GXB transmitter channel atom
ID:15195 clock1 output port of GXB transmitter PLL "<name>" must connect only to clock port of a GXB receiver channel atom, GXB transmitter channel atom, or XGMII state machine atom
ID:15196 areset input port of GXB transmitter PLL "<name>" must be driven by pllresetout output port of XGMII state machine atom
ID:15197 datain input port of GXB receiver channel atom "<name>" must be fed by input pin
ID:15198 cruclk input port of GXB receiver channel atom "<name>" must be fed by pin or PLL
ID:15199 Input port <name> of GXB receiver channel atom "<name>" must be fed by output port <name> of GXB transmitter PLL because <text>
ID:15200 Input port <name> of GXB receiver channel atom "<name>" must be fed by output port <name> of GXB transmitter PLL
ID:15201 masterclk input port of GXB receiver channel atom "<name>" must be fed by the recovclkout output port of a GXB receiver channel atom in channel 0
ID:15202 Input port <name> of GXB receiver channel atom "<name>" cannot be connected because <text>
ID:15203 Can't connect input port <name>[<number>] of GXB receiver channel atom "<name>" because <text>
ID:15204 Input port <name> of GXB receiver channel atom "<name>" has width <number>, but must have width <number>
ID:15206 coreclk input port of GXB receiver channel atom "<name>" is unconnected, but must be fed by either clock2 output port of a GXB transmitter PLL or clkout output port of GXB receiver channel atom "<name>"
ID:15207 GXB receiver channel atom "<name>" has either serialfdbk or slpbk input port connected -- both serialfdbk and slpbk input ports must be connected or disconnected
ID:15208 serialfdbk input port of GXB receiver channel atom "<name>" in channel <number> must be fed by dataout output port of a GXB transmitter channel atom in channel <number>
ID:15209 Input port <name> of GXB receiver channel atom "<name>" must be connected
ID:15210 Input port <name> of GXB receiver channel atom "<name>" must be connected because <text>
ID:15212 Input port <name>[<number>] of GXB receiver channel atom "<name>" is connected -- this connection is not supported because <text>
ID:15213 Input port <name>[<number>] of GXB receiver channel atom "<name>" is unconnected -- this is not supported because <text>
ID:15214 xgmdatain[<number>] input port of GXB receiver channel atom "<name>" must be connected to rxdataout [<number>] output port of XGMII state machine atom
ID:15215 xgmdatain[] input port of GXB receiver channel atom "<name>" must have width of 8
ID:15217 Input port <name> of GXB receiver channel atom "<name>" is connected, but this connection is not allowed because <text>
ID:15218 Input port <name> of GXB receiver channel atom "<name>" cannot be connected when GXB receiver channel atom "<name>" is not in channel alignment mode
ID:15219 Input port <name> of GXB receiver channel atom "<name>" must connect to output port <name> of an XGMII state machine atom
ID:15220 Output port <name>[<number>] of GXB receiver channel atom "<name>" must feed only output port <name>[<number>] of a GXB transmitter channel atom in the same channel because <name>
ID:15221 Input port <name>[<number>] of GXB receiver channel atom "<name>" must connect to output port <name>[<number>] of a GXB transmitter channel atom in the same channel
ID:15222 Input port <name> of GXB receiver channel atom "<name>" must connect to output port <name>[<number>] of an XGMII state machine atom
ID:15223 Input port <name> of GXB receiver channel atom "<name>" must be fed only by output port <name> of a GXB receiver channel atom in channel 0
ID:15224 Input port <name> of GXB receiver channel atom "<name>" cannot be connected when GXB receiver channel atom "<name>" is not in 8B/10B mode
ID:15225 inclk0 input frequency <number> for GXB receiver PLL of GXB receiver channel atom "<name>" must be in frequency range <number> to <number>
ID:15226 Serial clock output frequency <number> for GXB receiver PLL of GXB receiver channel atom "<name>" must be in the frequency range of <number> to <number>
ID:15227 Serial clock output frequency <number> for GXB receiver PLL of GXB receiver channel atom "<name>" must be less than <number> when coreclk is selected with the rate-matching FIFO in GIGE or XAUI protocols
ID:15228 Output port <name> of GXB receiver channel atom "<name>" must be connected to input port <name>[<number>] of XGMII state machine atom because <text>
ID:15229 Output port <name> of GXB receiver channel atom "<name>" cannot be connected because <text>
ID:15230 Output port <name>[<number>] of GXB receiver channel atom "<name>" cannot be connected because <text>
ID:15232 Output port <name> of GXB receiver channel atom "<name>" must be connected to input port <name>[<number>] of XGMII state machine atom
ID:15233 Output port <name>[<number>] of GXB receiver channel atom "<name>" must be connected only to input port <name>[<number>] of an XGMII state machine atom
ID:15234 recovclkout output port of GXB receiver channel atom "<name>" in channel 0 must be connected when GXB receiver channel atom "<name>" is in channel alignment mode
ID:15235 recovclkout output port of GXB receiver channel atom "<name>" cannot be connected when GXB receiver channel atom "<name>" is not in channel 0 or is not in channel alignment mode
ID:15236 recovclkout output port of GXB receiver channel atom "<name>" in channel 0 must be connected to either masterclk input port of GXB receiver channel atom or to recovclk input port of XGMII state machine atom
ID:15237 Output port <name> of GXB receiver channel atom "<name>" in channel 0 must be connected because <text>
ID:15238 Output port <name> of GXB receiver channel atom "<name>" in channel 0 must connect to input port <name> of a GXB receiver channel atom
ID:15239 Output port <name> of GXB receiver channel atom "<name>" must be connected because <text>
ID:15240 Output port <name>[<number>] of GXB receiver channel atom "<name>" must be connected because <text>
ID:15241 Output clock frequency <number> of GXB receiver channel atom "<name>" must be in the frequency range of <number> to <number>
ID:15244 Implemented predivider for cruclk input frequency <number> of GXB receiver channel atom "<name>"
ID:15245 Can't implement predivider for GXB transmitter PLL "<name>" because clock input does not feed from pin
ID:15246 Can't implement GXB receiver channel atom "<name>" with cruclk input frequency <number> and serial clock output frequency <number>
ID:15249 Intel Arria 10 devices have specific voltage requirements for VCCR_GXB/VCCT_GXB pins. Refer to the Intel Arria 10 Device Family Pin Connection Guidelines on the Intel website for detailed information and to find the correct voltage requirements for your pins. Based on device and data-rate, the Fitter cannot find a valid VCCR_GXB/VCCT_GXB voltage value for the following HSSI block instances:
ID:15250 data-rate: <text> instance: <text>
ID:15251 LCELL atom "<name>" uses improperly connected cin port
ID:15252 LCELL atom "<name>" uses improperly connected cin0 port
ID:15253 LCELL atom "<name>" uses improperly connected cin1 port
ID:15256 Clock buffer <name> drives another clock buffer <name>
ID:15258 LCELL atom "<name>" cannot use datad port when in arithmetic or counter mode
ID:15259 LCELL atom "<name>" is dependent on unconnected input ports
ID:15260 Compilations are still in progress. If you close the Design Space Explorer, all running processes will be stopped and results will not be preserved. Do you want to close the Design Space Explorer, losing all your compilation data?
ID:15261 The HPS EMIF Interface is connected to an unsupported primitive: <name>
ID:15262 The HPS peripheral primitive: <name> connects to an non HPS pin: <name>
ID:15263 The HPS peripheral primitive: <name> port: <name> has <number> wires when the max size is <number>
ID:15264 The HPS pin: <name> for hps primitive: <name> is placed in an location not Supported for the HPS pin MUX.
ID:15265 The Fitter cannot place all design elements. Run a full compilation so the Fitter can attempt to place all elements in your design, or reduce the amount of changed logic and run the Rapid Recompile compilation flow again.
ID:15267 Do you want to stop all running and unsubmitted compilations, losing compilation results and data?
ID:15268 I/O atom "<name>", which has its OPERATION_MODE parameter value set to either OUTPUT or BIDIR, must have data source
ID:15269 You provided an invalid user name, password, or both
ID:15270 I/O atom "<name>" cannot use the aclr port and have its POWER_UP_HIGH parameter value set to TRUE, or use the preset port and have its POWER_UP_HIGH parameter set to FALSE
ID:15271 ATX (LC) PLL: < <text> > is connected to a PCI Express Hard IP block in your design. The current location of ATX (LC) PLL on the device: <text>, is not connected to a PCIe Hard IP block. Instead, place the ATX (LC) PLL at device location: <text>.
ID:15272 Transceiver group: <text> and <text> have to share the same HCLK signal to be placed inside the same triplet channel. Use one HCLK signal from the transmitter PLL and share the signal with the other transmitter group.
ID:15273 Do you want to stop compiling this exploration point?
ID:15276 JTAG port <name> must connect to an I/O pin
ID:15277 JTAG port <name> must connect to I/O pin
ID:15278 JTAG port <name> is connected to a pin with multiple fanouts. This is not legal. The pin must only drive the JTAG port.
ID:15280 <number> additional occupied locations (details not shown).
ID:15281 LCELL atom "<name>" cannot use regcascin port that is improperly connected
ID:15282 cin and regcascin ports of LCELL atom "<name>" have different sources
ID:15283 LCELL atom "<name>" cannot feed more than one regcascin port
ID:15284 Can't implement LCELL atom "<name>" -- LCELL atom is part of cyclic register cascade chain
ID:15285 Register cascade chain that starts with LCELL atom "<name>" and that with LCELL atom "<name>" has length <number>, but exceeds maximum legal length of <number>
ID:15286 LCELL atom "<name>" has a cout port that feeds another LCELL atom's input port that is not a cin port
ID:15287 cout0 port of LCELL atom "<name>" feeds another LCELL atom's input port that is not a cin0 port
ID:15288 cout1 port of LCELL atom "<name>" feeds another LCELL atom's input port that is not a cin1 port
ID:15289 LCELL atom "<name>" has a cout port that feeds more than one input port, but LCELL atom must feed only one input port
ID:15290 LCELL atom "<name>" has a cout0 port that feeds more than one input port, but LCELL atom must feed only one input port
ID:15291 cout1 port of LCELL atom "<name>" feeds more than one input port, but LCELL atom must feed only one input port
ID:15292 LCELL atom "<name>" must use clk port when in synchronous mode
ID:15293 LCELL atom "<name>" must use clk port when in register cascade mode
ID:15294 LCELL atom "<name>" must use clk port when using aclr port
ID:15295 LCELL atom "<name>" must use clk port if aload port is used
ID:15296 LCELL atom "<name>" must use clk port if sclr port is used
ID:15297 LCELL atom "<name>" must use clk port if sload port is used
ID:15298 LCELL atom "<name>" must use clk port if ena port is used
ID:15299 LCELL atom "<name>" has an inverta port connection, but is not part of a carry chain
ID:15300 LCELL atom "<name>" uses illegal carry chain connections
ID:15301 LCELL atom "<name>" uses inconsistent inverta port connections
ID:15302 LCELL atom "<name>" must use synchronous data port if sload port is used
ID:15303 LCELL atom "<name>" must use asynchronous data port if aload port is used
ID:15304 LCELL atom "<name>" must use regout port when using clk port
ID:15305 LCELL atom "<name>" must use clk port when using regout port
ID:15306 LCELL atom "<name>" must use clk port when in QFBK mode
ID:15307 Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
ID:15308 Invalid device family in project file; close and reopen project to access Device dialog box
ID:15310 pexpin port of atom "<name>" cannot be VCC, GND, inverted, direct from pin, or from non-parallel expander output port on another atom
ID:15311 Atom "<name>" has pexpin port that contains <number> unused Pterm cell(s)
ID:15312 Atom "<name>" uses a register, but the atom has no dataout or fan-out port from the register
ID:15313 pexpout port of atom "<name>" must positively feed pexpin port
ID:15314 Invalid device family in project file; close and reopen project to access Setting dialog box
ID:15315 Maximum seed range is 1000 seeds. Use a seed range that does not exceed 1000 seeds.
ID:15316 Your Notification Center session could not be resumed. You must sign in again to access the Notification Center.
ID:15317 Node "<name>" will not be modified or duplicated because one of its fanouts is in a different partition.
ID:15318 PMA POWER MODE INFO: prot_mode:"<name>", speed_grade:"<name>", link:"<name>", data rate:"<name>"; power_mode:"<name>"
ID:15327 ATOM "<name>" has port <name> that cannot be connected <text>
ID:15328 Atom "<name>" has port <name> that should not be connected <text>
ID:15329 <name> atom "<name>" has port <name> that must be connected <text>
ID:15331 Atom "<name>" has port <name> that should be connected <text>
ID:15332 Port <name> of <name> "<name>" has <number> connections, but the maximum bus width of port <name> is <number>. Disconnect the extra connections from the specified port. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
ID:15333 DSP block WYSIWYG primitive "<name>" is using saturation but the multipliers are not 18-bit widths
ID:15334 DSP block WYSIWYG primitive "<name>" is using rounding, but the multipliers are not 18 bits wide
ID:15335 DSP block output WYSIWYG primitive "<name>" is using saturation, but it is not in accumulator or dynamic mode
ID:15336 DSP block WYSIWYG primitive "<name>" has input port <name>[<index>] that cannot be floating
ID:15337 DSP block multiplier WYSIWYG primitive "<name>" has dataout port that must drive a DSP block output WYSIWYG primitive
ID:15338 DSP block multiplier WYSIWYG primitive "<name>" has dataout port that must drive a data port of a DSP block output WYSIWYG primitive
ID:15339 DSP block multiplier WYSIWYG primitive "<name>" has dataout[<index>] port that must drive only one port
ID:15340 DSP block multiplier WYSIWYG primitive "<name>" has dataout[<index>] port that must drive the same node for all bits
ID:15341 DSP block multiplier WYSIWYG primitive "<name>" has dataout[<index>] port that must drive the same data port of a DSP block output WYSIWYG primitive
ID:15342 DSP block multiplier WYSIWYG primitive "<name>" has dataout[<index>] port that must drive the same bit index on the data port of a DSP block output WYSIWYG primitive
ID:15343 DSP block multiplier WYSIWYG primitive "<name>" has dataout[<index>] port that cannot be floating
ID:15344 DSP block output WYSIWYG primitive "<name>" has <name> port that must be driven by a DSP block multiplier WYSIWYG primitive
ID:15345 DSP block output WYSIWYG primitive "<name>" has <name> port that must be driven by the dataout port of a DSP block multiplier WYSIWYG primitive
ID:15346 DSP block output WYSIWYG primitive "<name>" has <name>[<index>] port that must be driven by the same node for all bits
ID:15347 DSP block output WYSIWYG primitive "<name>" has <name>[<index>] port that must be driven by the dataout port of a DSP block multiplier WYSIWYG primitive
ID:15348 DSP block output WYSIWYG primitive "<name>" has <name>[<index>] port that must be driven by the same bit index on the dataout port of a DSP block multiplier WYSIWYG primitive
ID:15349 WYSIWYG primitive "<name>" has <name> port that must be driven by the same signal as the other nodes of the DSP block slice
ID:15350 WYSIWYG primitive "<name>" has <name> port that must have the same CLOCK parameter as the other nodes in the DSP block slice
ID:15351 WYSIWYG primitive "<name>" has <name> port that must have the same CLEAR parameter as the other nodes in the DSP block slice
ID:15352 DSP block multiplier WYSIWYG primitive "<name>" has <name> port that cannot be used in <name> mode
ID:15353 DSP block output WYSIWYG primitive "<name>" has accoverflow port that must be used in ACCUMULATOR mode
ID:15354 DSP block output WYSIWYG primitive "<name>" has accoverflow port that must be used in ACCUMULATOR or TWO-LEVEL-ADDER mode
ID:15355 WYSIWYG primitive "<name>" has clock port <name>[<index>] that is driven by VCC or GND
ID:15356 WYSIWYG primitive "<name>" has clear port <name>[<index>] that is driven by VCC
ID:15357 WYSIWYG primitive "<name>" has clock enable port <name>[<index>] that is driven by GND
ID:15358 DSP block slice contains WYSIWYG primitive "<name>" that has <number> aclr signals -- WYSIWYG primitive "<name>" cannot have more than <number> aclr signals
ID:15359 DSP block slice contains WYSIWYG primitive "<name>" that has <number> clk and ce pairs -- WYSIWYG primitive "<name>" cannot have more than <number> clk and ce pairs
ID:15360 DSP block WYSIWYG primitive "<name>" has unconnected port <name>[<bit number>] -- port must be connected because corresponding register is used
ID:15361 DSP block input shift register starting with <name> of <name> must use same clock and clock enable signals
ID:15362 DSP block multiplier node "<name>"
ID:15363 Register for port <name> has <name> signal <name>
ID:15364 DSP block WYSIWYG primitive "<name>" has <name> port that must have width of 17 bits when in 36-bit multiplier mode
ID:15365 DSP block WYSIWYG primitive "<name>" has <name> port that must have width of 18 bits when in 36-bit multiplier mode
ID:15366 DSP block WYSIWYG primitive "<name>" is in multiply-accumulator mode, but must be in bypass-multiplier mode when driving dataa port of DSP block WYSIWYG primitive "<name>"
ID:15367 DSP block WYSIWYG primitive "<name>" is in bypass-multiplier mode, but must not be in bypass-multiplier mode when driving datab port of DSP block WYSIWYG primitive "<name>" that is in multiply-accumulator mode
ID:15368 <name> port of DSP block multiplier WYSIWYG primitive "<name>" is connected. It cannot be connected when the DSP block multiplier WYSIWYG primitive is using the loadable accumulator feature
ID:15369 DSP block multiplier WYSIWYG primitive "<name>" is in bypass-multiplier mode, but its <name> port is not connected to GND
ID:15370 Source port <name> of DSP block multiplier WYSIWYG primitive "<name>" is connected to GND, but the corresponding scanin port <name> is also connected
ID:15371 WYSIWYG DSP block multiplier primitives "<name>" and "<name>" are connected to ports <name> and <name> of the same DSP block output WYSIWYG primitive "<name>", but round ports are not connected to the same signal source
ID:15372 WYSIWYG DSP block multiplier primitive "<name>" has <name> port with width <number> and is feeding <name> port of WYSIWYG DSP block multiplier primitive "<name>", which has width <number>. WYSIWYG DSP block multiplier primitives of different widths cannot be connected by scan chain
ID:15373 DSP block multiplier WYSIWYG primitives "<name>" and "<name>" are connected to ports <name> and <name> of the same DSP block output WYSIWYG primitive "<name>"; however, port <name> of DSP block output WYSIWYG primitive is not connected to the same signal source as that of the saturate ports of the DSP block multiplier WYSIWYG primitives
ID:15374 Port <name> index <number> of DSP block multiplier WYSIWYG primitive "<name>" is not driven by <name> port of another DSP block multiplier WYSIWYG primitive
ID:15375 Port <name> of DSP block multiplier WYSIWYG primitive "<name>" is not driven by DSP block multiplier WYSIWYG primitive above it
ID:15376 DSP block multiplier WYSIWYG primitive "<name>" has <name> port that cannot be used in 36_BIT_MULTIPLY mode
ID:15377 DSP block multiplier WYSIWYG primitive "<name>" has <name> port that must be connected to GND in 36_BIT_MULTIPLY mode
ID:15378 Port <name> of DSP block output WYSIWYG primitive "<name>" is not fed by a DSP block multiplier WYSIWYG primitive; all data ports of a DSP block output WYSIWYG primitive must be connected to a DSP block multiplier WYSIWYG primitive when OPERATION_MODE is set to DYNAMIC
ID:15379 Port <name> of DSP block output WYSIWYG primitive "<name>" is not connected to a DSP block multiplier WYSIWYG primitive -- port <name> must be connected when OPERATION_MODE is set to <name>
ID:15380 Ports <name> of DSP block multiplier WYSIWYG primitives "<name>" and "<name>" and <name> port of DSP block output WYSIWYG primitive "<name>" are not fed by the same signal source
ID:15381 DSP block multiplier WYSIWYG primitive "<name>" is set to an OPERATION_MODE other than BYPASS_MULTIPLIER; DSP block multiplier WYSIWYG primitive must have OPERATION_MODE set to BYPASS_MULTIPLIER when the corresponding DSP block output WYSIWYG primitive has OPERATION_MODE set to DYNAMIC
ID:15382 DSP block multiplier WYSIWYG primitive "<name>" has OPERATION_MODE set to BYPASS_MULTIPLIER; when corresponding DSP block output WYSIWYG primitive has OPERATION_MODE set to DYNAMIC, DSP block multiplier WYSIWYG primitive must have OPERATION_MODE set to a value other than BYPASS_MULTIPLIER
ID:15383 Port <name> of DSP block multiplier WYSIWYG primitive "<name>" is connected, but OPERATION_MODE of DSP block multiplier WYSIWYG primitive "<name>" is set to a value other than DYNAMIC
ID:15384 DSP block output WYSIWYG primitive "<name>" has <name> port that must be driven by a DSP block output WYSIWYG primitive
ID:15385 DSP block output WYSIWYG primitive "<name>" has <name> port that must be driven by the dataout port of a DSP block output WYSIWYG primitive
ID:15386 DSP block output WYSIWYG primitive "<name>" has <name>[<index>] port that must be driven by the dataout port of a DSP block output WYSIWYG primitive
ID:15387 DSP block output WYSIWYG primitive "<name>" has <name>[<index>] port that must be driven by the same bit index on the dataout port of a DSP block output WYSIWYG primitive
ID:15388 DSP block output WYSIWYG primitive "<name>" has <name> port that must be driven by the dataout port of a DSP block output WYSIWYG primitive with the OPERATION_MODE value set to ACCUMULATOR_CHAIN_OUT or TWO_LEVEL_ADDER_CHAIN_OUT
ID:15389 DSP block output WYSIWYG primitive "<name>" has <name> port that must be driven by the dataout port of another DSP block output WYSIWYG primitive
ID:15390 Port <name> of DSP block output WYSIWYG primitive "<name>" is connected, but OPERATION_MODE of DSP block output WYSIWYG primitive "<name>" is set to a value other than ACCUMULATOR_CHAIN_OUT or TWO_LEVEL_ADDER_CHAIN_OUT
ID:15391 DSP block output WYSIWYG primitive "<name>" has an ACC_ADDER_OPERATION value set to SUBTRACT, but OPERATION_MODE of DSP block output WYSIWYG primitive "<name>" is set to a value other than ACCUMULATOR or ACCUMULATOR_CHAIN_OUT
ID:15392 WYSIWYG primitive "<name>" has <name> port that must have the same CLOCK parameter as the other input register nodes in the DSP block slice
ID:15393 WYSIWYG primitive "<name>" has <name> port that must have the same CLEAR parameter as the other input register nodes in the DSP block slice
ID:15394 WYSIWYG primitive "<name>" has <name> port that must have the same CLOCK parameter as the other pipeline register nodes in the DSP block slice
ID:15395 WYSIWYG primitive "<name>" has <name> port that must have the same CLEAR parameter as the other pipeline register nodes in the DSP block slice
ID:15396 WYSIWYG primitive "<name>" has <name> port that must have the same CLOCK parameter as the other output register nodes in the DSP block slice
ID:15397 WYSIWYG primitive "<name>" has <name> port that must have the same CLEAR parameter as the other output register nodes in the DSP block slice
ID:15398 DSP block WYSIWYG primitive "<name>" has <name> port that must have width of 18 bits when in loopback mode
ID:15399 Port <name> of DSP block output WYSIWYG primitive "<name>" is not connected to port <name> of the DSP block multiplier WYSIWYG primitive "<name>" -- port <name> must be connected to port <name> of the DSP block multiplier WYSIWYG primitive "<name>" when OPERATION_MODE is set to <name>
ID:15400 WYSIWYG primitive "<name>" has a port <name> that is stuck at <name>
ID:15401 DSP block multiplier WYSIWYG primitive "<name>" has <name>[<index>] port is not connected to port <name> of the DSP block output WYSIWYG primitive "<name>" -- port <name>[<index>] must be connected to port <name> of the DSP block output WYSIWYG primitive "<name>" when OPERATION_MODE is set to <name>
ID:15402 DSP block multiplier WYSIWYG primitive "<name>" has <name>[<index>] port that must be driven by the same bit index on the <name> port of DSP block output WYSIWYG primitive <name>
ID:15403 DSP block output WYSIWYG primitive "<name>" has a parameter <name> that must have the same value as <name>
ID:15404 Port <name> of DSP block output WYSIWYG primitive "<name>" is connected, but port <name> cannot be connected when OPERATION_MODE is set to <name>
ID:15409 DSP block output WYSIWYG primitive "<name>" is using rounding, but the rounding width is less than the minimum rounding width of <number>
ID:15410 DSP block output WYSIWYG primitive "<name>" is using saturation, but the saturation width is less than the minimum saturation width of <number>
ID:15411 DSP block output WYSIWYG primitive "<name>" is using rounding, but the rounding width greater than the maximum rounding width of <number>
ID:15412 DSP block output WYSIWYG primitive "<name>" is using saturation, but the saturation width is greater than the maximum saturation width of <number>
ID:15413 DSP block multiplier WYSIWYG primitive "<name>" has parameter <name> set to <name>, but parameter <name> must be set to <name> when the OPERATION_MODE is set to <name>
ID:15414 DSP block output WYSIWYG primitive "<name>" requires a register in the loopback data path when the OPERATION_MODE is set to LOOPBACK
ID:15415 DSP block multiplier WYSIWYG primitive "<name>" has <name>[<index>] port that must drive only one port
ID:15416 DSP block multiplier WYSIWYG primitive "<name>" has <name>[<index>] port that must drive DSP block multiplier WYSIWYG primitive "<name>" to form a scan chain
ID:15417 DSP block multiplier WYSIWYG primitive "<name>" has <name>[<index>] port that must drive port <name> of DSP block multiplier WYSIWYG primitive "<name>" to form a scan chain
ID:15418 DSP block multiplier WYSIWYG primitive "<name>" has <name>[<index>] port that must be driven by the same bit index on the <name> port of DSP block multiplier WYSIWYG primitive <name>
ID:15419 DSP block multiplier WYSIWYG primitive "<name>" has <name> port that drives DSP block multiplier WYSIWYG primitive "<name>", but port <name> of "<name>" is not fully connected to the <name> port of "<name>"
ID:15421 Port <name> of DSP block multiplier WYSIWYG primitive "<name>" does not have the same width as port <name> of DSP block multiplier WYSIWYG primitive "<name>"
ID:15422 Port <name> of DSP block multiplier WYSIWYG primitive "<name>" is not registered, but port <name> must be registered to form a scan chain
ID:15423 DSP block multiplier WYSIWYG primitive "<name>" forms a circular scan chain
ID:15424 DSP block multiplier WYSIWYG primitive "<name>" can only form a scan chain to the same DSP block multiplier WYSIWYG primitive
ID:15425 <name> register of DSP block multiplier WYSIWYG primitive "<name>" is used, but <name> register can only be used by DSP block multiplier WYSIWYG primitive "<name>"
ID:15426 DSP block output WYSIWYG primitive "<name>" forms a circular chain-adder connection
ID:15427 DSP block multiplier WYSIWYG primitive "<name>" forms a scan chain with DSP block multiplier WYSIWYG primitive "<name>", but "<name>" is using a different operation mode than "<name>"
ID:15428 DSP block multiplier WYSIWYG primitive "<name>" and DSP block multiplier WYSIWYG primitive "<name>" both use the SCANOUTA register, but adjacent DSP block multiplier WYSIWYG primitives cannot both use the SCANOUTA register when the operation mode is OUTPUT_ONLY
ID:15429 DSP block multiplier WYSIWYG primitive "<name>" uses the scanouta register, but a dedicated scan chain is not connected
ID:15431 Port <name> of DSP block output WYSIWYG primitive "<name>" is connected, but DSP block output WYSIWYG primitive "<name>" forms a chain adder connection with DSP block output WYSIWYG primitive "<name>"
ID:15432 WYSIWYG DSP block output primitive "<name>" has <name> port with width <number> and is feeding <name> port of WYSIWYG DSP block output primitive "<name>", which has width <number>. WYSIWYG DSP block output primitives of different widths cannot be connected by a chain adder connection
ID:15433 Port <name>[<index>] of DSP block output WYSIWYG primitive "<name>" is connected, but port <name>[<index>] cannot be connected when OPERATION_MODE is set to <name>
ID:15434 WYSIWYG DSP block output primitive "<name>" is connected to "<name>" and "<name>" chain_in ports. Only one chain_in fan-out is allowed
ID:15436 DSP block multiplier WYSIWYG primitive "<name>" feeds DSP block output WYSIWYG primitive "<name>", but it has a different width than the other DSP block multiplier WYSIWYG primitives
ID:15437 DSP block output WYSIWYG primitive "<name>" is using rounding, but the data output width is less than the minimum rounding width of <number>
ID:15438 DSP block output WYSIWYG primitive "<name>" is using saturation, but the data output width is less than the minimum saturation width of <number>
ID:15439 DSP block output WYSIWYG primitive "<name>" is using rounding, but the data output width is less than the rounding width of <number>
ID:15440 DSP block output WYSIWYG primitive "<name>" is using saturation, but the data output width is less than the saturation width of <number>
ID:15441 DSP block multiplier WYSIWYG primitive "<name>" is using the SCANOUTA register, but the SCANOUTA register is not supported in <name> mode
ID:15442 DSP block output WYSIWYG primitive "<name>" is using saturation, but saturation cannot be used with unsigned data
ID:15443 DSP block output WYSIWYG primitive "<name>" has a rounding width of <number> , but the rounding width must have a value that is between the minimum rounding width of <number> and the maximum rounding width of <number> or have a value of <number> when using symmetric saturation
ID:15444 DSP block output WYSIWYG primitive "<name>" is using symmetric saturation, but the data output width is less than the minimum rounding width of <number>
ID:15445 DSP block output WYSIWYG primitive "<name>" is using symmetric saturation, but the data output width is less than the rounding width of <number>
ID:15446 DSP block output WYSIWYG primitive "<name>" is using symmetric saturation, but the rounding width is less than the minimum rounding width of <number>
ID:15447 DSP block output WYSIWYG primitive "<name>" is using symmetric saturation, but the rounding width greater than the maximum rounding width of <number>
ID:15448 DSP block WYSIWYG primitive "<name>" is using saturation in <name> mode, but the multipliers are not 18-bit widths
ID:15449 WYSIWYG primitive "<name>" has <name> port that must have the same CLOCK_ENABLE parameter as the other input register nodes in the DSP block slice
ID:15450 WYSIWYG primitive "<name>" has <name> port that must have the same CLOCK_ENABLE parameter as the other pipeline register nodes in the DSP block slice
ID:15451 WYSIWYG primitive "<name>" has <name> port that must have the same CLOCK_ENABLE parameter as the other output register nodes in the DSP block slice
ID:15453 Port <name> of DSP block output WYSIWYG primitive "<name>" is connected, but port <name> can only be connected in test mode
ID:15454 DSP block output WYSIWYG primitive "<name>" has <name> port that must be driven by the dataout port of a DSP block output WYSIWYG primitive with the same OPERATION_MODE value
ID:15455 DSP block multiplier WYSIWYG primitive "<name>" has inverters in the scan chain, which drives DSP block multiplier WYSIWYG primitive "<name>", but dedicated scan chains cannot be inverted
ID:15456 Port <name> of DSP block output WYSIWYG primitive "<name>" is connected, but the port cannot be connected without the rounding width value of <number> when using symmetric saturation in <name> mode
ID:15457 DSP block output WYSIWYG primitive "<name>" is part of an output adder chain that uses saturation, but "<name>" is not using saturation at all possible stages
ID:15458 Port <name> of DSP block output WYSIWYG primitive "<name>" is not used, but "<name>" is part of an output adder chain that uses saturation
ID:15459 DSP block output WYSIWYG primitive "<name>" is using unsigned data in <name> mode, but <name> requires signed data when ACC_ADDER_OPERATION is set to SUBTRACT
ID:15460 The <name> parameter of the <name> register in the port <name> of WYSIWYG "<name>" is set to <number>, but the only legal values are <number>, or a positive value less than or equal to <number>
ID:15461 DSP block multiplier WYSIWYG primitive "<name>" does not have its scan chain connected, but the dedicated scan chains are used for the DSP block
ID:15462 DSP block multiplier WYSIWYG primitive "<name>" has its scan chain connected, but the dedicated scan chains are not used for the DSP block
ID:15463 WYSIWYG primitive "<name>" of "<name>" block has read-enable port that must be VCC when WYSIWYG primitive "<name>" is in M-RAM
ID:15464 WYSIWYG primitive "<name>" has mismatched parameters for port <name>
ID:15465 WYSIWYG primitive "<name>" has clk0 port that must be connected
ID:15466 WYSIWYG primitive "<name>" has port <name> that is unconnected
ID:15468 WYSIWYG primitive "<name>" has port A input registers using clk1, which is not allowed. Port A input registers can use only clock from clk0.
ID:15469 The SERDES receiver or transmitter atom "<name>" has one or more clock and enable ports that are not driven by a fast PLL
ID:15470 SERDES receiver or transmitter atom "<name>" has clock input port that must be driven by clk0 or clk1 output port of fast PLL
ID:15471 clock input port of SERDES receiver or transmitter atom "<name>" must be driven by sclkout port of fast PLL
ID:15472 clock input port of SERDES receiver or transmitter atom "<name>" must be driven by a clock output port of the fast PLL
ID:15473 enable0 and clock0 input ports of the SERDES receiver or transmitter atom "<name>" must be driven by the same indexed output ports of a fast PLL (enable0 with sclk0 OR enable1 with sclk1)
ID:15474 enable and clock input ports of the SERDES receiver atom "<name>" must be driven by output ports of the same fast PLL
ID:15475 enable0 input port of SERDES receiver or transmitter atom "<name>" must be driven by a clock output port of the fast PLL
ID:15476 clock and enable port of SERDES receiver or transmitter atom "<name>" must have their frequencies related by the deserialization factor
ID:15477 The LVDS clock and the DPA clock frequency of SERDES receiver atom "<name>" must be the same
ID:15478 DPA clock of SERDES receiver atom "<name>" is driven by PLL "<name>" with unspecified <text> and <text> parameters
ID:15479 SERDES receiver atom "<name>" is using DPA mode, but port <name> is not being driven by a dynamic signal
ID:15480 Port <name> of SERDES receiver atom "<name>" is connected, but the <name> port cannot be connected
ID:15481 enable0 input port of the SERDES receiver atom "<name>" is driven by an invalid port -- enable0 input port must be driven by a valid enable output port of a fast PLL
ID:15482 enable0 input port of the SERDES receiver atom "<name>" is driven by an invalid port -- enable0 input port must be driven by a valid enable output port of a fast PLL
ID:15483 enable1 input port of the SERDES receiver atom "<name>" is driven by an invalid port -- enable1 input port must be driven by a valid enable output port of a fast PLL
ID:15485 enable0 input port of the SERDES transmitter atom "<name>" is driven by an invalid port -- enable0 input port must be driven by a valid enable output port of a fast PLL
ID:15486 enable0 input port of the SERDES transmitter atom "<name>" is driven by an invalid port -- enable0 input port must be driven by a valid enable output port of a fast PLL
ID:15487 data input port of the SERDES transmitter atom "<name>" must have the same width value as the CHANNEL_WIDTH parameter
ID:15488 data input port of the SERDES transmitter atom "<name>" must have the same width value as the CHANNEL_WIDTH parameter
ID:15489 SERIALDATAIN and POSTDPASERIALDATAIN of atom "<name>" cannot be connected at the same time
ID:15490 SERIALFDBKOUT and POSTDPASERIALDATAIN of atom "<name>" cannot be connected at the same time, because that would form a loop
ID:15491 SERIALFDBKOUT of atom "<name>" is connected, therefore SERIALDATAIN or POSTDPASERIALDATAIN should be connected to the same RX receiver
ID:15492 SERIALDATAOUT and POSTDPASERIALDATAOUT of atom "<name>" cannot be connected at the same time
ID:15493 SERIALFBK and POSTDPASERIALDATAOUT of atom "<name>" cannot be connected at the same time because that would form a loop
ID:15494 SERIALFBK of atom "<name>" is connected, therefore SERIALDATAOUT or POSTDPASERIALDATAOUT should be connected to the same TX transmitter
ID:15495 Ignored enable1 port of LVDS receiver "<name>" because USE_ENABLE1 is set to OFF
ID:15496 LVDS receiver "<name>" is driven by PLL "<name>" which is configured for high-speed operation (datarates up to <number>), but LVDS receiver is not using DPA
ID:15497 inclk0 port of PLL "<name>" must be driven by a non-inverted input pin or, in a fast PLL, the output of a PLL
ID:15498 inclk1 port of enhanced PLL "<name>" must be driven by a non-inverted input pin
ID:15500 inclk0 and inclk1 of enhanced PLL "<name>" cannot be fed by the same source
ID:15501 Input pin "<name>" feeds <inclk0 or inclk1> of enhanced PLL "<name>" and the inclk port of a fast PLL -- routing inclk0 port of the fast PLL via global clocks
ID:15502 Port "<name>" of <type> PLL "<name>" cannot be implemented
ID:15503 Design uses enable input pin "<name>" and enable input pin "<name>", but only one enable input pin can be used in <name> device family
ID:15504 Enable input port of PLL "<name>" must be driven by input pin
ID:15505 Input pin "<name>" feeds ena input port of enhanced or fast PLL "<name>" and other logic -- input pin "<name>" should not feed other logic
ID:15506 scanclk port of enhanced PLL "<name>" is disconnected or is driven by GND or VCC -- scanclk port must be driven by a signal
ID:15507 SCAN_CHAIN parameter of enhanced PLL "<name>" must be specified when using real-time control of advanced parameters
ID:15508 Output port <name> of enhanced PLL "<name>" must feed an output pin
ID:15509 Input pin "<name>" feeds the fbin input port of enhanced PLL "<name>" and other logic
ID:15510 Port "<name>" of enhanced PLL "<name>" can only feed output pins
ID:15511 Port <name> of enhanced PLL "<name>" cannot feed more than <number> output pins
ID:15512 External clock ports of enhanced PLL "<name>" are driving <number> pairs of output pins -- external clock ports cannot feed more than four pairs of output pins
ID:15513 One or more extclk ports of enhanced PLL "<name>" must feed output pins when OPERATION_MODE parameter is set to EXTERNAL_FEEDBACK or ZERO_DELAY_BUFFER
ID:15514 enable1 output port of fast PLL "<name>" must feed only the enable1 input port of a SERDES receiver or the enable0 input port of a SERDES transmitter
ID:15515 enable0 output port of fast PLL "<name>" must feed only enable0 input port of a SERDES receiver
ID:15516 clk0 or clk1 output port of fast PLL "<name>" must drive only a clock input port of a SERDES receiver or transmitter
ID:15517 Output port <name> of <type> PLL "<name>" cannot drive a SERDES receiver or transmitter
ID:15518 PLL "<name>" must contain internal parameter <name>
ID:15519 Enhanced PLL "<name>" has the following parameter warnings
ID:15520 Can't achieve requested value <number> of parameter <name> -- achieved value of <number>
ID:15521 Pole frequency <number> MHz is smaller than the loop bandwidth <number> MHz
ID:15522 Zero frequency <number> MHz is greater than the loop bandwidth <number> MHz
ID:15523 PLL PFD frequency of <number> MHz for inclk[<number>] is less than minimum required PFD frequency of <number> MHz, which is <number> times the bandwidth value -- PFD frequency value must be at least <number> times the bandwidth value to ensure optimal PLL performance
ID:15524 PLL PFD frequency of <number> MHz is less than minimum required PFD frequency value of <number> MHz, which is ten times the bandwidth value of -- PFD frequency value must be at least ten times the bandwidth value to ensure optimal PLL performance
ID:15525 Can't achieve optimal bandwidth value for PLL "<name>" with the current set of internal parameters
ID:15526 PLL "<name>" has settings that may result in high compensation variability
ID:15527 PLL "<name>" has settings that may cause the lock circuit to fail due to high compensation variability.
ID:15528 PLL "<name>" has settings that can result in high compensation variability when operating in a military temperature range
ID:15529 PLL "<name>" has spread frequency of <number>, but must be in the frequency range of <number> to <number>
ID:15530 Down spread value <number>% is greater than <number>%
ID:15531 inclk0 input frequency of <number> for <Text> PLL must be in the frequency range of <number> to <number> for a multiplication factor of <number>
ID:15532 inclk<0 or 1> input frequency of <number> for <type> PLL "<name>" must be in the frequency range of <number> to <number>
ID:15533 Port <type> output frequency of <number> for PLL "<name>" must be in the frequency range of <number> to <number>
ID:15534 PLL clock output <name> feeding <name> has illegal output frequency of <number> that must be <text>
ID:15535 Implemented <name> "<name>" as <name> PLL type
ID:15536 Implemented <name> "<name>" as <name> PLL type, but with warnings
ID:15537 Implemented <name> "<name>" as <name> PLL type, but with critical warnings
ID:15538 Can't implement PLL "<name>" as <name> PLL type
ID:15539 VCO phase tap parameter <name> must be 0 when counter <name> uses cascade input for PLL "<name>"
ID:15540 PLL "<name>" has counter <name> that uses cascade input, but no other counter cascades into counter <name>
ID:15541 PLL "<name>" has output clock "<name>" restricted to use counter <name>, but counter requires cascaded inputs and no other counter cascades into counter <name>
ID:15542 PLL "<name>" has output clock "<name>" restricted to use counter <name>, but the counter requires cascaded inputs from counter <name>, which is already used by clock output <name>
ID:15543 PLL "<name>" has counter <name> being used by multiple clock outputs <names>
ID:15544 PLL "<name>" has output clocks forced to use specific counters
ID:15545 PLL "<name>" has output clocks forced to use specific counters, but with some assignments ignored
ID:15546 PLL output clock "<name>" has PLL_FORCE_OUTPUT_COUNTER assignment forcing use of counter "<name>" for this output clock
ID:15547 Ignored PLL_FORCE_OUTPUT_COUNTER assignment forcing use of counter "<name>" for PLL output clock "<name>"
ID:15548 Even counter mode or value control parameter <name> set to value <name>
ID:15549 PLL clock output <name> was implemented with counter that uses odd counter mode or value -- <name> parameter is not satisfied
ID:15550 Clock router will preserve the counter order because <text>
ID:15551 PRESERVE_PLL_COUNTER_ORDER assignment on PLL "<name>" is not honored because PLL_FORCE_OUTPUT_COUNTER assignment on at least one of the output clocks does not permit it
ID:15552 PLL constraints from migration devices are also being used
ID:15553 PLL constraints from migration devices are being ignored
ID:15554 PLL "<name>" has the gated lock counter value set to <number> which is less than the recommended value of <number> (when inclk[<number>] has input frequency specified as <number>)
ID:15555 PLL "<name>" has illegal LVDS data rate of <number> -- data rate must be between <number> and <number>
ID:15556 Input frequency of PLL "<name>" must be in the frequency range of <number> to <number> for locking
ID:15557 Input frequency of PLL must be in the frequency range of <number> to <number> for locking
ID:15558 PLL "<name>" has illegal value "<number>" for parameter <name>
ID:15559 Can't achieve requested value <number> for clock output <name> of parameter <name> -- achieved value of <number>
ID:15560 Can't implement port <name> for enhanced PLL "<name>" -- SCAN_CHAIN parameter of enhanced PLL "<name>" is set to SHORT
ID:15561 Value <number> of parameter <name> does not match value <number> of parameter <name> for enhanced PLL "<name>", and SCAN_CHAIN parameter of enhanced PLL "<name>" is set to SHORT
ID:15562 Enhanced PLL "<name>" uses inclk0 and inclk1 ports, but clkswitch port is unconnected, and SWITCH_OVER_ON_LOSSCLK and SWITCH_OVER_ON_GATED_LOCK parameters are set to OFF
ID:15563 Enhanced PLL "<name>" has <name> port with duty cycle value <number> -- for the lock filter to function correctly, the duty cycle value must be more than 40% or less than 60%
ID:15564 Compensate clock of PLL "<name>" has been set to <name>
ID:15565 Compensation clock for PLL "<name>" is set to <name>, but the clock is not properly connected.
ID:15566 Can't achieve requested bandwidth of <text> MHz for PLL "<name>" -- achieved bandwidth of <text> MHz
ID:15567 Can't achieve requested <name> bandwidth type; current PLL requires a bandwidth value of <text> -- achieved bandwidth of <number>
ID:15568 Output port <name> of PLL "<name>" cannot drive a SERDES receiver or transmitter when the PLL_TYPE parameter is set to FAST
ID:15569 Output port <name> of enhanced PLL "<name>" must feed an output pin
ID:15571 Compensating output pin "<name>", which is fed by <name> port of PLL "<name>"
ID:15572 PLL Compensation logic option is specified for several output pins that are fed by <name> port of PLL "<name>"
ID:15573 Can't compensate output pin "<name>"
ID:15574 Input "<name>" that is fed by the compensated output clock of PLL "<name>" in Source Synchronous mode has been set as a compensated input
ID:15575 None of the inputs fed by the compensated output clock of PLL "<name>" in Source Synchronous mode are set as the compensated input
ID:15576 PLL Compensation logic option is specified for several inputs that are fed by the compensated output clock of PLL "<name>" in Source Synchronous mode
ID:15577 Several inputs fed by the compensated output clock of PLL "<name>" in Source Synchronous mode are set as compensated input
ID:15578 PLL Compensation logic option on input "<name>" will be ignored.
ID:15579 Output port <name> of PLL "<name>" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
ID:15582 Changing unlock parameter of PLL "<name>" from <number> to <number> half clock cycles of the pre-scaler output
ID:15583 Changing lock parameter of PLL "<name>" from <number> to <number> half clock cycles of the pre-scaler output
ID:15585 Minimum frequency <number> is greater than maximum frequency <number> -- cannot lock PLL "<name>" when minimum frequency range is greater than maximum frequency range
ID:15587 pgmout port <number> of atom "<name>" has <number> fan-outs -- pgmout port must have exactly one fan-out
ID:15588 pgmout port <number> of atom "<name>" drives cell "<name>", which <name>, but pgmout port must drive an output pin
ID:15590 clock port of atom <name> is disconnected or is connected to VCC or GND, but must be connected to legal clock pin or logic cell
ID:15591 crcerror port of atom "<name>" has <number> fan-outs -- crcerror port must have only one fan-out
ID:15592 Atom "<name>" has crcerror port that must be connected
ID:15593 crcerror port of atom "<name>" drives "<name>", which <name>, but crcerror port must drive non-registered output pin or bidirectional pin with VCC output enable signal
ID:15594 CRC Block atom "<name>" has crcerror port that drives "<name>" through an inverter, but that path is dedicated and must not have inverter between CRC block and CRCERROR pin
ID:15595 CRC Block atom "<name>" has crcerror port that drives <name> port of atom "<name>", but the crcerror signal is sent through a dedicated path to <name> port of CRCERROR pin -- crcerror port must be connected to datain port of CRCERROR pin and cannot feed other ports
ID:15596 clock port of atom "<name>" is disconnected or is connected to VCC or GND, but must be connected to legal clock pin or logic cell
ID:15598 Incompatible pin pair assignment. RX pin < <text> > is assigned to pin location <text>; TX pin < <text> > is assigned to pin location <text>, but the pin locations are not compatible. To correct the incompatibility, assign the specified RX pin to pin location <text> or remove the pin assignments.
ID:15599 To compile your design, you should either run a full compilation, restore the design from an archived project, or import the database for the design from a previously exported database.
ID:15600 Can't use JTAG port <name> in current design
ID:15601 Value of DLL "<name>" parameter <name> must match parameter <name> of DQS I/O "<name>"
ID:15602 DQS I/O pin "<name>" cannot feed source clock for DLL "<name>"
ID:15603 Can't connect dqsundelayedout output port of non-DQS I/O pin "<name>" -- output port dqsundelayedout can be connected only when I/O pin is a DQS I/O pin. Remove dqsundelayedout output port connection
ID:15604 Atom "<name>" has non-inverted port <name>. <text>
ID:15605 Atom "<name>" has inconsistent inversion flag on port <name> and <name>. <text>
ID:15606 DQS/DQSn atom "<name>" has inconsistent DQ fan-outs that have different ddioinclk_input settings. All DQS fan-outs (DQ pins) should have the same ddioinclk_input setting
ID:15607 Can't use Auto Open-Drain Pins logic option with input pin "<name>"
ID:15608 DQ IO atom "<name>" has ddioinclk_input set to <name>
ID:15609 IO atom "<name>" has bad connection on output port <name>. <text>
ID:15610 No output dependent on input pin "<name>"
ID:15611 The DQS phase shift parameter has a value <number>, which differs from the native phase shift, with a value of <number>
ID:15612 IO atom "<name>" has bad connection on input port <name>. <text>
ID:15613 Input ports <name> and <name> of <name> atom "<name>" must be fed by the same <name> atom. <text>
ID:15614 Input port <name> of atom "<name>" and input port <name> of atom "<name>" must be fed by the same source. <text>
ID:15615 Atom "<name>" must use clk port when the <name> port is used and when the <name> port is not logical GND
ID:15616 Atom "<name>" must use clk port when the <name> port is used and when the <name> port is not logical VCC
ID:15617 Atom "<name>" must use sload port when <name> port is used
ID:15618 Atom "<name>" must use sdata port when sload port is used
ID:15619 Atom "<name>" must use <name> port if sload port is used
ID:15620 Atom "<name>" must use <name> port if aload port is used
ID:15621 Atom "<name>" must use aload port or sload port if <name> port is used
ID:15622 Atom "<name>" cannot have its <name> port set to VCC or inverted
ID:15623 Atom "<name>" uses improperly connected cin port
ID:15624 Atom "<name>" uses improperly connected sharein port
ID:15625 cin port of atom "<name>" must be connected when sharein port is used
ID:15626 Cin and sharein ports of atom "<name>" have different sources
ID:15627 Atom "<name>" cannot use sharein port when not in shared arithmetic mode
ID:15628 Atom "<name>" must use sharein port when in shared arithmetic mode
ID:15629 Atom "<name>" is dependent on unconnected input ports
ID:15630 Atom "<name>" has a cout port that feeds another atom's input port that is not a cin port
ID:15631 Atom "<name>" has a shareout port that feeds another atom's input port that is not a sharein port
ID:15632 Atom "<name>" has a cout port that feeds more than one input port, but atom must feed only one input port
ID:15633 Atom "<name>" has a shareout port that feeds more than one input port, but atom must feed only one input port
ID:15634 cout and shareout ports of atom "<name>" must feed the same atom
ID:15635 Atom "<name>" cannot use datae port when in arithmetic mode
ID:15636 Input port <name> of atom "<name>" cannot be inverted
ID:15637 Atom "<name>" must use all LUT input ports when in extended LUT mode
ID:15638 Atom "<name>" cannot use datag port when in a non-extended LUT mode
ID:15639 I/O atom "<name>" uses post-amble circuit -- <name> signal must be configured as <name> but is currently configured as <name>
ID:15640 IO atom "<name>" uses post-amble circuit -- <name> signal must be connected to <name>
ID:15641 I/O atom "<name>" uses complementary clocks to capture data from double data rate input pin. Contact Intel Technical Services at http://mysupport.altera.com for implementation guidelines to ensure correct data captures on QDRII interfaces
ID:15642 Can't use asynchronous clear signal in WYSIWYG RAM primitive "<name>" with input registers and with current device family
ID:15643 Can't use parameter <name> with WYSIWYG RAM primitive and current device family
ID:15647 <text> in a group of <number> components with similar legality requirements
ID:15648 Do not connect S2F_PADDRDBG[0] and S2F_PADDRDBG[1] in the twentynm_hps_interface_dbg_apb. The valid width is S2F_PADDRDBG[2:18]
ID:15649 Input port <name> of atom "<name>" has illegal width value -- width value cannot exceed <number> with atom's current configuration.
ID:15650 Output port <name> of atom "<name>" has illegal width value -- width value cannot exceed <number> with atom's current configuration.
ID:15651 Destination ports of node "<node>" have incompatible clock types. Modify your design so the clock types of the destination ports are consistent.
ID:15653 The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design.
ID:15654 WYSIWYG I/O primitive "<name>" has illegal value for ADDRESS_WIDTH parameter --value must be 7, 8, or 9
ID:15655 Port <text> of Clock Control Block "<name>" can't drive <text> port of Clock Control Block "<name>"
ID:15656 Port(s) <text> of Clock Control Block "<name>" must be used
ID:15657 clkselect port of Clock Control Block "<name>" must be 0 or cannot be used when only one input clock signal is selected
ID:15658 inclk[<number>] port of Clock Control Block "<name>" cannot be used when clkselect port is not used or is a constant
ID:15659 CLOCK_TYPE parameter of Clock Control Block "<name>" is set to <text>, but must be <text>
ID:15660 inclk[<number>] port of Clock Control Block "<name>" is driven by <name>, but must be driven by <text>
ID:15661 Signal "<name>" drives inclk[<number>] port of Clock Control Block "<name>", but cannot drive inclk[<number>] port of Clock Control Block "<name>" because the indices are different
ID:15662 inclk port of Clock Control Block "<name>" is driven by "<name>", but must be driven by a PLL clock output because CLOCK_TYPE parameter is set EXTERNAL_CLOCK_OUTPUT
ID:15663 outclk port of Clock Control Block "<name>" with CLOCK_TYPE parameter set to EXTERNAL_CLOCK_OUTPUT drives <name>, but must drive an unregistered pin
ID:15664 outclk port of External Clock Output Clock Control Block "<name>" must drive 1 output pin, but drives <number> output pin(s)
ID:15665 Clock Control Block "<name>" can select <text> ports, but only <text> is used
ID:15666 Can't select inclk[<number>] port of Clock Control Block "<name>"
ID:15667 Changed source nodes of Clock Control Block "<name>" inclk[] ports to use legal port connections and adjusted corresponding clkselect[] port connections
ID:15668 Replaced inclk[<number>] input port, which is driven by node <name>, with inclk[<number>] port
ID:15669 inclk port of Clock Control Block "<name>" must be driven by <number> PLLs but is driven by <number> PLLs
ID:15670 Clock Control Block is driven by PLL "<name>"
ID:15671 Can't use ena input port when CLOCK_TYPE parameter is set to external clock output for Clock Control Block "<name>" and is driven by node "<name>"
ID:15672 Port <name> of Clock Delay Control Block "<name>" must have a source
ID:15673 Port <name> of Clock Delay Control Block "<name>" must be driven by an I/O, but is currently driven by non-I/O <name>
ID:15674 Input port <name> of Clock Delay Control Block "<name>" cannot be connected
ID:15675 Input bus <name> of Clock Delay Control Block "<name>" cannot be connected
ID:15676 clkout port of Clock Delay Control Block "<name>" feeds at least one Clock Control Block and has more than one fan-out. This is not allowed
ID:15677 Clock Delay Control Block atom "<name>" has pllcalibrateclkdelayedin port that is driven by "<name>" -- port must be driven by pllcalibrateclkdelayedout port of Clock Delay Control Calibration Block
ID:15678 Input port <name> of Clock Delay Control Block "<name>" must be connected when calibration is used
ID:15679 Input port <name> of Clock Delay Control Block "<name>" cannot be connected when calibration is not used
ID:15680 Input port <name> of Clock Delay Control Block "<name>" cannot be connected when delay chain mode is not dynamic
ID:15681 delayctrlin input port of Clock Delay Control block "<name>" is of width <number>, but it should be <number> wide
ID:15682 delayctrlin[<number>] input port of Clock Delay Control block "<name>" does not have a source
ID:15683 delayctrlin input port of Clock Delay Control Block "<name>" is not connected. This port must be connected when the Clock Delay Control Block is in dynamic delay chain mode
ID:15687 <name> input port of Clock Delay Control Calibration block "<name>" is not sourced from the clock output port of a PLL. Source this port from the clock output port of a PLL
ID:15688 <name> input port of Clock Delay Control Calibration block "<name>" is not connected. It must be connected
ID:15689 Input port delayctrlin of Clock Delay Control Calibration block "<name>" is of width <number>, but it should be <number> wide
ID:15690 Input port delayctrlin [<number>] of Clock Delay Control Calibration block "<name>" does not have a source
ID:15691 Output port <name> of Clock Delay Control Calibration block "<name>" is not connected. It must be connected
ID:15692 Output port pllcalibrateclkdelayedout of Clock Delay Control Calibration block "<name>" feeds "<name>". The pllcalibrateclkdelayedout output port can feed only the pllcalibrateclkdelayedin input port of a Clock Delay Control Block
ID:15693 pllcalibrateclk input port of Clock Delay Control Calibration block "<name>" is fed by clock output of PLL "<name>", while its plldataclk input port is fed by clock output port of PLL "<name>"
ID:15694 Termination Block "<name>" cannot use User-Mode Calibration.
ID:15695 Termination Block "<name>" cannot have both control_probe and calibration_done connected.
ID:15696 Termination Block "<name>" has <name> parameter set to a value other than its default, but this parameter cannot be used if test-mode is not enabled
ID:15697 Termination atom "<name>" has <name> parameter, but parameter value is not within legal range of <number> and <number>
ID:15698 Termination atom "<name>" uses <name> port, which must be connected to <name> port
ID:15699 Output buffer atom "<name>" uses <name> port, which must be connected to <name> port on the corresponding termination logic block atom
ID:15700 Termination calibration block atom "<name>" uses <name> port, which must be connected to <name>
ID:15701 Termination calibration block atom "<name>" uses <name> port, which must be connected to <name> port on a Termination logic block atom
ID:15702 Termination logic block atom "<name>" uses <name> port, which must be connected to <name> port on the corresponding Termination calibration block atom
ID:15703 Termination logic block atom "<name>" uses <name> port, which must be connected to <name> port on an output buffer atom
ID:15704 Termination atom "<name>" and Termination atom "<name>" have different clock sources
ID:15705 Ignored locations or region assignments to the following nodes
ID:15706 Node "<name>" is assigned to location or region, but does not exist in design
ID:15707 Ignored locations or region assignments to the following nodes
ID:15708 Node "<name>" is assigned to location or region, but does not exist in design
ID:15709 Ignored I/O standard assignments to the following nodes
ID:15710 Ignored I/O standard assignment to node "<name>"
ID:15711 Pin <name> does not support I/O standard <name> with Termination setting <name> for location <name>
ID:15712 Pin <name> does not support I/O standard <name> with Current Strength <name> for location <name>
ID:15713 Can't place output or bidirectional pin <name> in input pin location <name>
ID:15714 Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
ID:15715 One or more pins are missing I/O standard assignments
ID:15716 Pin <pin name> is missing an I/O standard assignment
ID:15717 Design contains <number> virtual pins; timing numbers associated with paths containing virtual pins are estimates
ID:15718 Pin "<name>" is virtual input pin
ID:15719 Pin "<name>" is virtual output pin
ID:15720 Ignored Virtual Pin assignment to node "<name>"
ID:15721 Ignored Virtual Pin assignment made to bidirectional pin "<name>"
ID:15722 Virtual pin clock "<name>" for virtual pin "<name>" does not exist in the design -- auto-selecting clock
ID:15723 Can't find auto-select clock for virtual pin "<name>" -- setting clock to GND
ID:15725 clock port is fed by virtual pin "<name>"; timing analysis treats input to the clock port as a ripple clock
ID:15726 Virtual pin clock not found for <number> virtual pins -- used Auto clock
ID:15727 Ignored Virtual Pin assignment on registered pin "<name>"
ID:15728 Ignored Virtual Pin assignment on output enabled pin "<name>"
ID:15729 Virtual pins cannot be assigned to ports requiring real pins
ID:15730 Specified clocks for some virtual pins do not exist
ID:15731 Auto-select clock not found for some virtual pins
ID:15732 Ignored Virtual Pin assignment on Signal Tap output pin "<name>"
ID:15733 Ignored Virtual Pin logic option on PLL external feedback input pin "<name>" -- logic option is illegal for PLL external feedback input pins
ID:15734 Ignored Virtual Pin logic option on PLL enable pin "<name>" -- logic option is illegal for PLL enable pins
ID:15735 Ignored Virtual Pin logic option on PLL input clock pin "<name>" -- logic option is illegal for PLL input clock pins
ID:15736 Ignored Virtual Pin logic option on LVDS pin "<name>" -- logic option is illegal for LVDS pins
ID:15737 Ignored Virtual Pin logic option on LVDS deskew pin "<name>" -- logic option is illegal for LVDS deskew pins
ID:15740 Ignored Virtual Pin assignment on LVDS data in pin "<name>" -- logic option is illegal for HSSI/LVDS data in pins
ID:15741 Ignoring Virtual Pin assignment on "<name>" PLL pin "<name>"
ID:15742 Ignored Virtual Pin logic option on PLL external clock pin "<name>" -- logic option is illegal for PLL external clock pins
ID:15743 Ignored Virtual Pin logic option on LVDS data out pin "<name>" -- logic option is illegal for HSSI/LVDS data out pins
ID:15744 <name>
ID:15745 Ignored Virtual Pin assignment on differential I/O pin "<name>".
ID:15746 Ignored Virtual Pin assignment on DDIO pin "<name>".
ID:15747 Ignored Virtual Pin assignment on JTAG pin "<name>"
ID:15748 Ignored Virtual Pin assignment on CRCBLOCK pin "<name>"
ID:15749 Ignored Virtual Pin assignment on RUBLOCK pin "<name>"
ID:15750 Ignored Virtual Pin assignment on Termination Control pin "<name>".
ID:15751 Ignored Virtual Pin assignment to "<name>".
ID:15752 Ignored <number> Virtual Pin logic option assignments
ID:15753 Input port DATAIN of the GXB receiver channel PCS atom "<name>" must be connected to an GXB receiver channel PMA atom with only one fanout.
ID:15754 Input port rxpmareset of the GXB receiver channel PMA atom "<name>" must be connected to a CMU atom
ID:15755 Input port recoverdatain of the GXB receiver channel PMA atom "<name>" must be connected to a CDR atom
ID:15756 Input port dataout of the GXB receiver channel PMA atom "<name>" must be connected to a CDR atom
ID:15757 Output port dataout of the GXB receiver channel PMA atom "<name>" must be connected to only a CDR PLL atom for that channel
ID:15758 Output port dataout and input port recovereddatain of the GXB receiver channel PMA atom "<name>" must be connected to the same CDR PLL atom
ID:15759 serialloopback input port must be connected to enable the ALLOW_SERIAL_LOOPBACK setting for the GXB receiver channel atom "<name>"
ID:15760 Input port txpmareset of the GXB transmitter channel PMA atom "<name>" must be connected to a CMU atom
ID:15761 Output port dataout of the GXB transmitter channel PMA atom "<name>" must be connected to an output pin
ID:15762 Output port dataout of the GXB transmitter channel PMA atom "<name>" cannot connect to a bidir pin.
ID:15763 Input port datain of the GXB receiver channel PMA atom "<name>" must be connected to an input pin
ID:15764 <name> port <name> of GXB receiver channel atom "<name>" must be connected
ID:15765 Datain input port of GXB receiver channel atom "<name>" must be fed by an input pin with only one fanout
ID:15766 Input port <name> of GXB receiver channel atom "<name>" in channel <number> must be connected to output port <name> of the GXB receiver channel atom in channel <number>
ID:15767 Input port <name> of GXB receiver channel atom "<name>" must be connected to output port <name> of a GXB receiver channel atom in channel 0
ID:15769 Input port <name> of GXB receiver channel atom "<name>" cannot be connected because <text>
ID:15773 Output port <name> of GXB receiver channel atom "<name>" cannot be connected because <text>
ID:15774 Output port <name>[] of GXB receiver channel atom "<name>" has a width of <number> but the correct width cannot exceed <number> because the use_double_data_mode parameter is <name> and the use_deserializer_double_data_mode parameter is <name>
ID:15775 RX atom "<name>" on channel <number> and TX atom "<name>" on channel <number> use loopback, but they have different channels
ID:15776 Output port <name>[] of GXB receiver channel atom "<name>" has a width of <number>, but the correct width cannot exceed <number>
ID:15777 <name> port <name> of GXB receiver channel atom "<name>" must be connected to <name> port <name> of a <name> atom
ID:15778 Mode "<name>" TX "<name>" is using a direct connection from the PLL to the TX channel. For improved jitter, reopen this instantiation in the MegaWizard Plug-In Manager and switch the clocking scheme to use the X4 clocking lines.
ID:15779 Common mode voltage of GXB TX channel atom "<name>" must have a legal value
ID:15780 Common mode voltage of GXB RX channel atom "<name>" must have a legal value
ID:15781 Failed to launch MegaWizard Plug-In Manager<problem>
ID:15782 Parameter <name> of <name> atom "<name>" is not valid or unspecified. <text>
ID:15783 Input port <name> of <name> atom "<name>" must be connected <text>
ID:15784 Output port <name> of <name> atom "<name>" must be connected <text>
ID:15785 Input port <name> of <name> atom "<name>" cannot be connected <text>
ID:15786 Output port <name> of <name> atom "<name>" cannot be connected <text>
ID:15787 Illegal port connection -- port <name> of <name> atom "<name>" cannot be connected
ID:15788 Input port <name> of atom "<name>" must be connected to output port <name> of a <name> atom <text>
ID:15789 Input port <name> of atom "<name>" must be connected to output port <name> of a <name> atom in channel 0 <text>
ID:15790 Input port <name>[<number>] of atom "<name>" must be connected to output port <name> of a <name> atom with pll_number <number> (pll_number is currently <number>)
ID:15791 Input port <name> of atom "<name>" must be connected to the core in PMA-Direct configuration
ID:15792 Output port <name> of atom "<name>" cannot drive multiple destinations. It must drive only one <name> input port of <name> atom <text>
ID:15793 Input port <name> of GXB Central Control Unit atom "<name>" must be connected only to an input pin
ID:15794 Input pin "<name>" cannot feed node "<name>" and input port QUADENABLE of GXB Central Control Unit atom "<name>" at the same time
ID:15795 Output port reconfig_fromgxb of alt2gxb megafunction containing CMU atom "<name>" in Channel Reconfiguration mode or Channel and TX PLL Select Reconfig mode must be connected to alt2gxb_reconfig megafunction
ID:15796 Input port <name> of GXB REFCLK divider atom "<name>" must be connected only to an input pin
ID:15797 Input port <name> of GXB REFCLK divider atom "<name>" is connected to REFCLK pin "<name>". However, the REFCLK pin has fan-outs other than GXB REFCLK dividers. The REFCLK pin can only drive GXB REFCLK dividers.
ID:15798 Output port <name> of <name> atom "<name>" has illegal fan-out to input port <name> of atom "<name>". The output port can drive only <text>
ID:15799 Input port <name> of atom "<name>" can only be connected to output port <name> of a <name> atom <text>
ID:15800 Input port <name> of GXB Central clock divider atom "<name>" must be connected only to GXB Central clock divider atom in adjacent Quad
ID:15801 Input port <name> of GXB Central clock divider atom "<name>" must be connected only to GXB Central clock divider atom in its associated driver Quad
ID:15802 Parameter <name> of GXB Central clock divider atom "<name>" must be set to "<name>" <text>
ID:15803 Output port <name> of GXB transmitter channel atom "<name>" must drive to only one output pin
ID:15804 Input ports <name> of atom "<name>" must be driven by the same signal <text>
ID:15805 Input ports <name> of atom "<name>" must be driven by the same atom <text>
ID:15806 Output port <name>[<number>] of <name> atom "<name>" must connect to a <name> atom in channel <number>, but it is currently connected to channel <number>
ID:15807 <name> pin "<name>" must be locked down for GXB channel reconfiguration
ID:15808 The GXB node(s) associated with "<name>" are not in a supported configuration
ID:15809 The closest matching supported protocol is "<name>"
ID:15810 The closest matching supported protocol is "<name>" in a "<name>" configuration
ID:15811 The value of parameter "<name>" on GXB node "<name>" is not supported for this configuration
ID:15812 The current parameter value is "<name>" for this configuration
ID:15813 The parameter value "<name>" matches the closest supported protocol
ID:15814 Clock[<number>] input port of GXB Transmitter PLL <name> is fed by PLL output <name>
ID:15815 clock[<number>] input port of GXB Transmitter PLL <name> is fed by <name>. This signal can be fed only from an input pin
ID:15816 Atom "<name>" cannot use GXB reconfiguration mode because it is not supported on this device. The following GXB reconfiguration modes are not supported:
ID:15817 GXB reconfiguration mode "<name>" is not supported
ID:15818 Pin "<text>"
ID:15819 Selected device migration path implemented <number> pin(s) as tristated input(s)
ID:15820 Selected device migration path implemented <number> pin(s) as NC
ID:15821 Selected device migration path implemented <number> pin(s) as GND
ID:15825 Atom "<name>" cannot use its sumout port and its combout port at the same time
ID:15826 Atom "<name>" cannot use its "<name>" port
ID:15827 Atom "<name>" cannot use its "<name>" port
ID:15828 Atom "<name>" cannot use its "<name>" port
ID:15829 MLAB cell "<name>" is driven by combinational sources on <name> port
ID:15830 MLAB cell "<name>" is driven by registered sources on <name> port, but these registers use a different clock source
ID:15831 MLAB cell "<name>" is driven by registered sources on <name> port, but these registers use asynchronous clear
ID:15832 MLAB cell "<name>" is driven by registered sources on <name> port, but these registers use asynchronous load
ID:15833 MLAB cell "<name>" is driven by a registered source on the "Port A, Data In" port, but this register uses synchronous load
ID:15834 Inclk port(s) <text> of Clock Select Block "<name>" must be used
ID:15835 LC PLL POWER MODE INFO: vco_freq:"<name>"; power_mode:"<name>"
ID:15836 inclk[<number>] port of Clock Select Block "<name>" is driven by <name>, but must be driven by <text>
ID:15837 Can't select inclk[<number>] port of Clock Select Block "<name>"
ID:15838 <text> port(s) of Clock Select Block "<name>" can be selected but is/are not connected.
ID:15839 inclk port of Clock Buffer Block "<name>" is driven by an illegal source, but must be driven by a PLL clock output because CLOCK_TYPE parameter is set EXTERNAL_CLOCK_OUTPUT
ID:15840 outclk port of Clock Control Block "<name>" with CLOCK_TYPE parameter set to EXTERNAL_CLOCK_OUTPUT drives <name>, but must drive an unregistered pin
ID:15841 outclk port of External Clock Output Clock Buffer Block "<name>" must drive 1 output pin, but drives <number> output pin(s)
ID:15842 outclk port of the External Clock Output Clock Buffer Block "<name>" must drive output pins that share the same polarity, but the output pins <name> and <name> have different polarity
ID:15843 inclk port of Clock Buffer Block "<name>" must be used
ID:15844 outclk port of Clock Buffer Block "<name>" drives inclk port of <text> "<name>", but must not drive an inclk port of a <text>
ID:15845 Illegal value "<text>" for ena_register_mode parameter in Clock Enable Block "<name>" -- value must be <text> when the ena input is used and the clock type is "<text>".
ID:15846 ena port of Clock Buffer Block "<name>" is connected to GND.
ID:15847 Illegal value "<text>" for ena_register_mode parameter in Clock Control Block "<name>" -- value must be <text> when the ena input is used and the clock type is "<text>".
ID:15848 IO PAD "<name>" must drive an IBUF primitive when it is in input/bidir mode
ID:15849 IO PAD "<name>" must be driven by an OBUF primitive when it is in output/bidir mode
ID:15850 Input port <name> of I/O PAD "<name>" must be driven by an OBUF primitive
ID:15851 I/O PAD "<name>" must drive only one IBUF primitive and nothing else
ID:15852 Output port "<name>" of PSEUDO_DIFF_OUT primitive "<name>" must drive only one OBUF primitive on the I port and cannot drive anything else
ID:15853 Input port <name> of I/O input buffer "<name>" must be driven by a top-level pin
ID:15854 I/O input buffer "<name>" has too many "<name>" fan-outs. The maximum number allowed is <number>.
ID:15855 Output port <name> of I/O output buffer "<name>" has too many fan-outs. The I/O output buffer is allowed to drive only one top-level pin, but it has <number> fan-outs.
ID:15856 Output port <name> of I/O output buffer "<name>" must drive a top-level pin
ID:15857 Input port <name> of I/O output buffer "<name>" must be connected to a termination block
ID:15858 I/O flipflop primitive "<name>" cannot use <name> port and <name> port at the same time
ID:15859 I/O flipflop primitive "<name>" cannot use <name> port and <name> port at the same time
ID:15860 I/O flipflop primitive "<name>" must have <name> port fed by VCC if <name> port is used
ID:15861 I/O flipflop primitive "<name>" must have <name> port fed by VCC or GND if <name> port is used
ID:15862 I/O flipflop primitive "<name>" must have power_up set to high if <name> port is used
ID:15863 I/O flipflop primitive "<name>" must have power_up set to low if <name> port is used
ID:15864 Input port <name> of I/O input FF primitive "<name>" must be driven by an I/O IBUF primitive or a delay chain primitive
ID:15865 Output port <name> of I/O output FF primitive "<name>" must drive an I/O OBUF primitive, a delay chain primitive, or a pseudo-differential output primitive.
ID:15866 Output port <name> of I/O output-enable FF primitive "<name>" must drive an I/O OBUF primitive, a delay chain primitive, or a pseudo-differential output primitive.
ID:15867 Input port <name> of I/O input FF primitive "<name>" must be driven by an I/O IBUF primitive
ID:15868 Output port <name> of I/O output FF primitive "<name>" must drive an I/O OBUF primitive
ID:15869 Output port <name> of I/O output-enable FF primitive "<name>" must drive an I/O OBUF primitive
ID:15870 Input port <name> of DDIO_IN primitive "<name>" must come from an I/O IBUF primitive
ID:15871 Input port <name> of DDIO_IN primitive "<name>" must come from an I/O IBUF or DELAY_CHAIN primitive
ID:15872 Input port <name> of DDIO_IN primitive "<name>" must be driven from an I/O IBUF with no more than <number> delay chain primitives in between
ID:15873 Output port <name> of DDIO_OUT primitive "<name>" must drive input port <name> of an I/O OBUF primitive. It currently drives "<name>"
ID:15874 Output port <name> of DDIO_OUT primitive "<name>" must drive input port <name> of I/O OBUF primitive or input port <name> of DELAY_CHAIN primitive.
ID:15875 Output port <name> of DDIO_OUT primitive "<name>" must drive an I/O OBUF with no more than <number> delay chain primitives in between.
ID:15876 The ena input of DDIO_OUT primitive "<name>" with HALF_RATE_MODE set to TRUE must be unconnected or connected to VCC
ID:15877 The sreset input of DDIO_OUT primitive "<name>" with HALF_RATE_MODE set to TRUE must be unconnected or connected to GND
ID:15878 DDIO_OUT primitive "<name>" must have half-rate mode set to FALSE
ID:15879 Output port <name> of DDIO_OE primitive "<name>" must drive input port <name> of an I/O OBUF primitive
ID:15880 Output port <name> of DDIO_OE primitive "<name>" must drive input port <name> of I/O OBUF primitive or input port <name> of DELAY_CHAIN primitive
ID:15881 Output port <name> of DDIO_OUT primitive "<name>" must drive an I/O OBUF with no more than <number> delay chain primitives in between.
ID:15882 Output port <name> of DDIO_OUT primitive "<name>" driving a FF primitive must eventually drive an I/O OBUF primitive or a DQS_ENABLE primitive.
ID:15883 Signal <name> is routed on the <name> network, however there is no path to reach the specified clock network from internal logic. Modify your design so the specified signal uses a clock source of a compatible type.
ID:15884 Output port "<name>" of WYSIWYG "<name>" has real fan-out. It is a buried port used for name preservation of buried registers and should not have real fan-out.
ID:15885 Output port "<name>" of DDIO_OUT WYSIWYG "<name>" has too many fan-outs.
ID:15886 Output port "<name>" of DDIO_OE WYSIWYG "<name>" has too many fanouts.
ID:15887 Output port "<name>" of DDIO_OUT WYSIWYG "<name>" has invalid signal-splitter fan-outs.
ID:15888 Input ports "<name>", "<name>" and "<name>" of DDIO_OUT WYSIWYG primitive "<name>" must come from the same source
ID:15889 Input port "<name>" of DDIO_IN WYSIWYG "<name>" has an invalid source
ID:15890 Input port "<name>" of DDIO_IN WYSIWYG "<name>" has invalid source.
ID:15891 Output port <name> of I/O termination FF primitive "<name>" must drive the "dynamicterminationcontrol" port of an I/O OBUF primitive or the "datain" port of a delay chain primitive
ID:15892 PLL "<name>" cannot be set to "<name>" and connected to an "altpll_reconfig" megafunction
ID:15893 PLL "<name>" cannot be set to "<name>" and connected to an "altpll_reconfig" megafunction that is configured for an "<name>" PLL type
ID:15894 PLL "<name>" uses the auto-switchover feature, but the input clock frequencies are too far apart
ID:15895 PLL "<name>" uses test-only parameter <name>, but this parameter must be used only in test mode
ID:15896 DSP block WYSIWYG primitive "<name>" has incorrect port connection for <name> -- port must be "<number>" width where "<number>" is detected
ID:15897 PLL "<name>" has parameter <name> set to <name> but port <name> is not connected
ID:15898 PLL "<name>" has port <name> connected but parameters <name> and/or <name> are either unspecified or set to 0
ID:15899 PLL "<name>" has parameters <name> and <name> specified but port <name> is not connected
ID:15900 PLL "<name>" has port <name> connected but parameters <name> is either unspecified or set to <name>
ID:15901 PLL "<name>" has parameter <name> set to <name> specified but port <name> is not connected
ID:15902 PLL "<name>" has port <name> connected but parameter <name> is either unspecified or set to <name>
ID:15903 PLL "<name>" has parameter <name> set to <name>, but <name> port is disconnected or stuck at VCC/GND
ID:15904 PLL "<name>" has parameter <name> set to <name>, but has <name> port stuck at VCC
ID:15905 PLL "<name>" is not using Input Clock Switchover, but port <name> is being used
ID:15906 PLL "<name>" is using scan reconfiguration (port <name> is connected) but other required scan reconfiguration ports are not connected
ID:15907 PLL "<name>" has port <name> either disconnected or connected to VCC/GND
ID:15908 PLL "<name>" has scan reconfiguration ports connected, but PLL scan reconfiguration is not being used (since port <name> is not connected)
ID:15909 PLL "<name>" has port <name> connected when PLL scan reconfiguration is not being used
ID:15910 PLL "<name>" has parameters set requesting a VCO frequency of <number> -- the requested frequency must be between <number> and <number>
ID:15911 Input port <text> of PLL "<name>" must be driven by the <text> output of the same PLL.
ID:15912 Input port <text> and output port <text> of PLL "<name>" are not properly connected.
ID:15913 Input port <text> of PLL "<name>" must be connected to the <text> output of the same PLL.
ID:15914 Input port <text> of PLL "<name>" must be driven by a pin.
ID:15915 Output port <text> of PLL "<name>" must drive a pin.
ID:15916 Input port <text> and output port <text> of PLL "<name>" are not connected properly
ID:15917 Input port <text> of PLL "<name>" must be connected to the <text> output of the same PLL.
ID:15918 PLL "<name>" has its compensation clock type set to an LVDS clock, but the PLL does not connect to either an LVDS Receiver or an LVDS Transmitter block
ID:15919 PLL "<name>" is using external feedback mode and a high bandwidth setting, which is not supported
ID:15920 PLL "<name>" is using an external feedback mode that is not supported for the currently selected family
ID:15921 Output port <name> of <type> atom "<name>" is connected but <text>
ID:15922 MLAB primitive "<name>" uses too many addresses. The chosen device family's MLAB does not have native support for <number> addresses.
ID:15923 MLAB primitive "<name>" uses the byte-mask feature, but the feature is not supported by the chosen device family
ID:15924 RAM Primitive "<name>" cannot use the pipeline registers without enabling the ECC feature
ID:15925 RAM Primitive "<name>" uses ECC feature and it can't use the byte-mask feature at the same time
ID:15926 RAM Primitive "<name>" uses ECC feature but it can't be implemented in 2Kx64 simple dual-port mode.
ID:15927 RAM primitive "<name>" uses the ECC feature, but it can't be configured in the 512x32 simple dual-port RAM mode
ID:15928 RAM Primitive "<name>" has output port "<name>" connected but the parameter "<name>" is not set. To use ECC feature, you must specify the parameter.
ID:15929 RAM Primitive "<name>" uses the ECC feature and targets the "<name>" memory block. The "<name>" memory block does not support the ECC feature.
ID:15930 RAM primitive "<name>" uses illegal combinations of clock-enable names. The illegal combinations are input clock-enable "<name>", core clock-enable "<name>", and output clock-enable "<name>".
ID:15931 Atom "<name>" has port <name> that must be connected <text>
ID:15932 Clock input of DLL "<name>" must be fed by either an o output of an I/O input buffer or a clockout output of a PLL.
ID:15933 The offsetdelayctrlout[<number>] output of DLL "<name>" can only drive offsetdelayctrlin[<number>] input of a DLL offset control primitive
ID:15934 offsetdelayctrlout outputs of DLL "<name>" can only drive up to <number> DLL offset control primitives
ID:15935 offsetdelayctrlclkout output of DLL "<name>" can only drive clock input of a DLL offset control primitive.
ID:15936 offsetdelayctrlclkout output of DLL "<name>" can only drive up to <number> DLL offset control primitive
ID:15937 DSP block WYSIWYG primitive "<name>" has <name> port with invalid connection. The input to this port must come from another DSP block and fully connected.
ID:15938 <name> parameter of the DLL atom "<name>" has an invalid value. It can only be set to <text>.
ID:15939 <name> parameter of DLL atom "<name>" is set to <text>, but should only be set to <text>
ID:15940 Input ports <name> of the DLL offset control primitive "<name>" are fed from DLL atoms <name> respectively, but must must be fed from the same DLL atom
ID:15941 dqsin input of DQS delay chain "<name>" must be driven by an uninverted o output of I/O input buffer.
ID:15942 offsetctrlin[<number>] input of the DQS delay chain "<name>" can be driven only by the offsetctrlout[<number>] output of a DLL offset control
ID:15943 The dqsupdateen input of DQS delay chain "<name>" should not be connected to VCC or GND when DQS_CTRL_LATCHES_ENABLE parameter is set to TRUE.
ID:15944 The dqsupdateen input of DQS delay chain "<name>" may not be driven by an inverted dqsupdate output of a DLL.
ID:15945 DQS_PHASE_SHIFT parameter of DQS delay chain "<name>" is set to <number>, but should be equal to 36000*(<name>.PHASE_SETTING)/(<name>.DELAY_CHAIN_LENGTH)
ID:15946 DQS_INPUT_FREQUENCY parameter of DQS delay chain "<name>" should be equal to the INPUT_FREQUENCY parameter of DLL "<name>"
ID:15947 .phasectrlin[<number>] input port of DQS delay chain primitive "<name>" must be driven by the dqsinputphasesetting[<number>] output port of a DQS config primitive
ID:15948 The dqsin input of DQS Enable "<name>" must be driven by an uninverted dqsbusout output of a DQS delay chain or an uninverted dataout output of a delay chain which has its datain input driven by an uninverted dqsbusout output of a DQS delay chain.
ID:15949 The delayctrlin[<number>] input of DQS enable control "<name>" may only be connected to an uninverted delayctrlout[<number>] output of a DLL.
ID:15950 delayctrlin[<number>] input of DQS enable control "<name>" must be connected when USE_PHASECTRLIN parameter is set to true or PHASE_SETTING parameter is not equal to 0.
ID:15951 DELAY_BUFFER_MODE parameter of DQS enable control primitive "<name>" does not match that of DLL "<name>" that is driving the delayctrlin inputs of the DQS enable control.
ID:15952 PHASE_SETTING parameter of DQS enable control primitive "<name>" should be less than the value of the DELAY_CHAIN_LENGTH parameter of DLL "<name>" that is driving the delayctrlin inputs of the DQS enable control.
ID:15953 The clk input of DQS enable control primitive"<name>" should not be connected to VCC/GND
ID:15954 The dqsenableout output of DQS enable control "<name>" cannot have more than one fanout
ID:15955 The dqsenableout output of DQS enable control "<name>" may only drive an uninverted dqsenable input of a DQS Enable or an uninverted datain of a delay chain which dataout output drives an uninverted dqsenable input of a DQS Enable
ID:15956 dqsenablein input of DQS enable control "<name>" may not be driven by an inverted dataout output of a DDIO_OUT. It is currently driven by "<name>".
ID:15957 enaphasetransferreg input of DQS enable control primitive "<name>" must be connected when ADD_PHASE_TRANSFER_REG parameter is set to "dynamic"
ID:15958 The enaphasetransferreg input of DQS enable control primitive "<name>" can only be driven by enadqsenablephasetransferreg output of a DQS configuration primitive
ID:15959 phaseinvertctrl input of DQS enable control primitive "<name>" can only be driven by dqsenablectrlphaseinvert output of a DQS configuration primitive.
ID:15960 ADD_PHASE_TRANSFER_REG parameter of DQS_ENABLE_CONTROL primitive "<name>" must be set to the opposite setting of INVERT_PHASE parameter if USE_PHASECTRLIN parameter is FALSE, INVERT_PHASE is not set to DYNAMIC, ADD_PHASE_TRANSFER_REG parameter
ID:15961 datain input of delay chain primitive "<name>" is driven by an inverted output of "<name>". When datain is driven by the following ports, they cannot be inverted: DQS delay chain dqsbusout, DQS enable control dqsenableout, I/O IBUF o, delay chain dataout, DDIO Out dataout, DDIO_OE dataout and output phase alignment output.
ID:15962 The source that is driving datain input of delay chain primitive "<name>" has too many fanout. When datain is driven by one of the following ports, those port cannot have more than one fanout: DQS delay chain dqsbusout, DQS enable control dqsenableout, delay chain dataout, DDIO Out dataout, DDIO_OE dataout and output phase alignment output
ID:15963 The datain input of delay chain primitive "<name>" is driven by the o output of an I/O input buffer primitive that has too many fanout. When the datain input is driven by the o output of an I/O input buffer primitive, that output can only have one other fanout to a directin input of a half-rate input primitive.
ID:15964 The dataout output of delay chain primitive "<name>" has too many fan-outs
ID:15965 The dataout output of delay chain primitive "<name>" must feed a FF/DDIO_IN/INPUT_PHASE_ALIGNMENT block
ID:15966 The <text> output of <text> primitive "<name>" is inverted while feeding the <text> input of <text> primitive "<name>"
ID:15967 The <text> output of <text> primitive "<name>" is uninverted while feeding the <text> input of <text> primitive "<name>"
ID:15968 DELAYCTRLIN[0] input of delay chain primitive "<name>" can only be driven by one of the following DQS config outputs: DQSBUSOUTDELAYSETTING[0], DQSENABLEDELAYSETTING[0], OCTDELAYSETTING1[0], or OCTDELAYSETTING2[0]; or one of the following I/O config outputs: OUTPUTDELAYSETTING1[0], OUTPUTDELAYSETTING2[0], or PADTOINPUTREGISTERDELAYSETTING[0]. It is currently fed by "<name>"
ID:15969 DELAYCTRLIN[<number>] input of delay chain primitive "<name>" can only be driven by the <name>[<number>] output of the configuration primitive "<name>"
ID:15970 DELAYCTRLIN[3] input of delay chain primitive "<name>" must be left unconnected or driven by GND.
ID:15971 IO_CLOCK_DIVIDER atom "<name>" fed by a DQS_DELAY_CHAIN, either directly or indirectly through a delay chain, must have its INVERT_PHASE parameter set to FALSE
ID:15972 The delayctrlin[<number>] input of I/O clock divider "<name>" can only be driven by uninverted delayctrlout[<number>] output of a DLL.
ID:15973 The delayctrlin inputs of I/O clock divider "<name>" must be connected when USE_PHASECTRLIN parameter is set to TRUE or PHASE_SETTING parameter is larger than 0
ID:15974 DELAY_BUFFER_MODE parameter of I/O clock divider "<name>" does not match that of DLL "<name>" that is driving the delayctrlin inputs of the I/O clock divider
ID:15975 PHASE_SETTING parameter of I/O clock divider "<name>" should be less than the value of the DELAY_CHAIN_LENGTH parameter of DLL "<name>" that is driving the delayctrlin inputs of the I/O clock divider
ID:15976 The phasectrlin[<number>] input of I/O clock divider "<name>" must be driven by resyncinputphasesetting[<number>] output of a DQS configuration primitive when USE_PHASECTRLIN parameter is set to true
ID:15977 The clk input of I/O clock divider primitive "<name>" should not be connected to VCC/GND
ID:15978 The phaseselect input of I/O clock divider primitive "<name>" should be driven by dividerphasesetting output of a DQS configuration primitive
ID:15979 USE_PHASECTRLIN and PHASE_SETTING parameters of I/O clock divider primitive "<name>" must be set to FALSE and 0 respectively when clk input is driven by dqsbusout output of a DQS delay chain primitive
ID:15980 The masterin input of I/O clock divider primitive "<name>" can only be driven by the slaveout output of another I/O clock divider primitive
ID:15981 The masterin input of I/O clock divider primitive "<name>" must be driven by slaveout output of another I/O clock divider primitive when USE_MASTERIN parameter is set to TRUE
ID:15982 The slaveout output of I/O clock divider primitive "<name>" can only drive masterin input of another I/O clock divider primitive
ID:15983 The slaveout output of I/O clock divider primitive "<name>" can only have one fanout
ID:15984 The phaseinvertctrl input of I/O clock divider primitive "<name>" can only be driven by resyncinputphaseinvert output of a DQS configuration primitive
ID:15985 OUTPUT_PHASE_ALIGNMENT primitive "<name>" with its phaseinvertctrl input port fed by the dqsoutputphaseinvert output port of a DQS_CONFIG primitive must have its phasectrlin[<number>] input port unconnected or fed by the dqsoutputphasesetting[<number>] output port of the same DQS_CONFIG primitive
ID:15986 OUTPUT_PHASE_ALIGNMENT primitive "<name>" with its phaseinvertctrl input fed by the dqoutputphaseinvert output of a DQS_CONFIG primitive must have its phasectrlin[<number>] input unconnected or fed by the dqoutputphasesetting[<number>] output of the same DQS_CONFIG primitive
ID:15987 OUTPUT_PHASE_ALIGNMENT primitive "<name>" with its phasectrlin input port fed by the dqsoutputphasesetting output port of a DQS_CONFIG primitive must have its phaseinvertctrl input port unconnected or fed by the dqsoutputphaseinvert output port of the same DQS_CONFIG primitive
ID:15988 OUTPUT_PHASE_ALIGNMENT primitive "<name>" with its phasectrlin input port fed by the dqoutputphasesetting output port of a DQS_CONFIG primitive must have its phaseinvertctrl input port unconnected or fed by the dqoutputphaseinvert output port of the same DQS_CONFIG primitive
ID:15989 phaseinvertctrl input port of output phase alignment primitive "<name>" can be unconnected or driven by only the dqsoutputphaseinvert output port of a DQS config primitive if the USE_PHASECTRL_CLK parameter is set to FALSE
ID:15990 phasectrlin[<number>] input port of OUTPUT_PHASE_ALIGNMENT primitive "<name>" can be unconnected or driven by only the dqsoutputphasesetting[<number>] output port of a DQS config primitive if the USE_PHASECTRL_CLK parameter is set to FALSE
ID:15991 USE_PRIMARY_CLOCK parameter of OUTPUT_PHASE_ALIGNMENT primitive "<name>" must be set to TRUE when USE_DELAYED_CLOCK parameter is set to TRUE
ID:15992 ASYNC_MODE parameter of output phase alignment primitive "<name>" must be set to NONE or CLEAR when POWER_UP parameter is set to LOW
ID:15993 ASYNC_MODE parameter of output phase alignment primitive "<name>" must be set to NONE or PRESET when POWER_UP parameter is set to HIGH
ID:15994 OPERATION_MODE parameter of output phase alignment primitive "<name>" is set to either RTENA or EXTENDED_RTENA. When OPERATION_MODE is set to either RTENA or EXTENDED_RTENA, the following parameters must be set to the specified values: SYNC_MODE and ASYNC_MODE must be set to NONE, POWER_UP must be set to LOW and USE_PHASECTRL_CLOCK must be set to TRUE
ID:15995 The clkena input of output phase alignment primitive "<name>" must be connected to VCC when OPERATION_MODE parameter is set to either RTENA or EXTENDED_RTENA
ID:15996 The delayctrlin[<number>] input of output phase alignment primitive "<name>" can only be driven by uninverted delayctrlout[<number>] output of a DLL
ID:15997 The delayctrlin inputs of output phase alignment primitive "<name>" must be connected when USE_PHASECTRLIN parameter is set to TRUE or PHASE_SETTING parameter is larger than 0
ID:15998 DELAY_BUFFER_MODE parameter of output phase alignment primitive "<name>" does not match that of DLL "<name>" that is driving the delayctrlin inputs of the output phase alignment primitive
ID:15999 The phasectrlin[<number>] input of output phase alignment primitive "<name>" must be driven by either dqsoutputphasesetting[<number>] or dqoutputphasesetting[<number>] output of a DQS configuration primitive when USE_PHASECTRLIN parameter is set to "true" and OPERATION_MODE parameter is set to either "out", "ddio_out", "oe" or "extended_oe"
ID:16012 DSP block WYSIWYG primitive "<name>" has <name> port with invalid connection. The output from this port must reach another DSP block and fully connected. Circular connection is not allowed
ID:16013 The accumulate port should not be connected for DSP block WYSIWYG primitive "<name>" in the current operation mode
ID:16014 DSP block WYSIWYG primitive "<name>" has connected port <name> which is invalid for "<name>" operation mode
ID:16015 DSP block WYSIWYG primitive "<name>" clock settings for "<name>" and "<name>" must use the same clock value
ID:16016 To have "<name>" operation mode for DSP block WYSIWYG primitive "<name>", please set parameter "<name>" to "<name>"
ID:16017 DSP block WYSIWYG primitive "<name>" does not support parameter "<name>" set to "<name>" for operation mode "<name>"
ID:16018 DSP WYSIWYG primitive "<name>" has clock setting "<name>" that is not set to "NONE".
ID:16019 The MSF file "<name>" from the base revision of partial reconfiguration partition cannot be located. Region mask verification will be skipped for <name>
ID:16020 The static MSF file "<name>" from the base revision cannot be located. Static region verification will be skipped.
ID:16023 hard IP reset pin "<name>" is assigned to illegal pin "<name>". Change the pin assignment to pin "<name>".
ID:16024 The SOF file "<name>" from base revision cannot be located. Preserved logic verification will be skipped.
ID:16025 Partial reconfiguration region mask verification failed for <name> mask. The mask does not match the mask from the base revision. <name>
ID:16026 Preserved logic verification failed for <name> bits. <name>
ID:16027 The following signals are routed on the periphery clock network, however there is no path to reach the specified clock network from internal logic. Modify your design so the specified signal uses a clock source of a compatible type:
ID:16028 Signal <name> is routed on the <name> network.
ID:16031 Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM.
ID:16033 CDR PLL "<name>" is assigned to illegal location "<name>". Change the location assignment to "<name>".
ID:16035 Device <name> does not support selected configuration mode
ID:16036 Configuration device <name> cannot configure device <name>
ID:16037 The Fitter merged transceiver Avalon Memory-Mapped interface group assignments with same group name "<name>" for simplex TX and simplex RX channel into instance "<name>". Correct the following conflicting TX channel and RX channel location assignments by ensuring the assignments are in the same channel:
ID:16038 The Fitter merged transceiver Avalon Memory-Mapped interface group assignments with same group name "<name>" for simplex TX channel and CDR PLL into instance "<name>". Correct the following conflicting TX channel and CDR PLL location assignments by ensuring the assignments are in the same channel:
ID:16039 Conflicting location assignment <text> is specified for instance <text>.
ID:16040 The compiled configuration mode <name> does not support multiple pages
ID:16041 Invalid enable mode "<name>" for Clock Buffer "<name>" driving PLL "<name>"
ID:16042 Using default timing derating
ID:16043 Using timing derating file <file>.
ID:16044 Detected device <name> which is inconsistent with the added device <name>
ID:16045 Instance "<NAME>" instantiates undefined entity "<NAME>"
ID:16046 The compiled configuration mode <name> does not support multiple pages
ID:16047 Detected device <name> which is inconsistent with the added device <name>
ID:16048 The compiled configuration mode <name> does not support <name>
ID:16049 The compiled configuration mode <name> must have <number> page(s) of data
ID:16050 Invalid enable mode "<name>" for Clock Buffer "<name>" driving PLL "<name>"
ID:16051 Device <name> does not support <name> scheme
ID:16053 Page <name> should have page_flags of <number> instead of <number>
ID:16054 Found duplicate or invalid name for <name> with page_flags of <number>
ID:16055 Overriding termination setting for "<name>" to comply with QSF assignment
ID:16057 Changing projects stops any processing on the current project and closes the project. Do you want to change the current project?
ID:16058 PLLs that use the x1 clock network and drive the same HSSI channel must be placed in the same transceiver bank. PLL "<name>" and PLL "<name>" use the x1 clock network and drive the same HSSI channel, however the PLLs are not assigned to the same transceiver bank. In the Assignment Editor, change the location assignment of the second specified PLL to location "<name>" so the two PLLs are in the same transceiver bank.
ID:16059 <name> (<number> fanout) drives <string> clock <number> (from <string> column at X<number>), with the buffer placed at <string>
ID:16060 Unable to open derating file <file>.
ID:16061 Unsupported element type <element> in timing derating file
ID:16062 Timing derating file parse error on line <line_number> of file <file>
ID:16063 Found invalid character in MIF file <name>
ID:16064 File <name> is not a valid Memory Initialization File
ID:16065 Export failed. Can't export PDF file <file_name>: <error_message>. Verify that the file is closed and that you can write to the specified file and location.
ID:16066 <name> is invalid User Flash Memory (UFM) source. First page UFM will be chosen
ID:16067 <number> out of <number> DSP block(s) in the design are not fully utilizing recommended internal DSP register banks. Design performance may be limited. To take full advantage of device resources, you should either enable the register banks directly (if using WYSIWYG entry) or provide additional registers in your design that the Quartus register packing optimization algorithm can convert to internal DSP register banks. The "Fixed Point DSP Register Packing Details" Fitter report indicates which DSP blocks are affected.
ID:16068 <number> DSP block(s) are unregistered - they use none of the recommended internal DSP register banks. Intel advises using all the recommended internal DSP register banks for high performance designs.
ID:16069 <number> DSP block(s) are partially registered - they use some, but not all of the recommended internal DSP register banks. Intel advises using all the recommended internal DSP register banks for high performance designs.
ID:16071 <number> DSP block(s) are fully registered - they use all of the recommended internal DSP register banks.
ID:16072 Input port "<name>" of PLL REFCLK_MUX "<name>" and input port "<name>" of PLL "<name>" must connect to output port "<name>" of the Transceiver Avalon Memory-Mapped Interface "<name>".
ID:16073 Input port "<name>" of PLL "<name>" is not connected to a PLL REFCLK_MUX. Both PLL and REFCLK_MUX must connect to output port "<name>" of the Transceiver Avalon Memory-Mapped Interface "<name>".
ID:16074 Output port "<name>" of PLL REFCLK_MUX "<name>" is not connected to a PLL. Both PLL and REFCLK_MUX must connect to output port "<name>" of the Transceiver Avalon Memory-Mapped Interface "<name>".
ID:16075 Cannot load <snapshot> snapshot of partition "<partition>" - ensure the partition has been compiled through all earlier stages.
ID:16076 This specific device does not support listening to nsleep port. Parameter "<name>" of atom "<name>" must be set to FALSE.
ID:16077 The file <name> is not expected for the requested operation
ID:16079 The selected device has an HPS. HPS power is not modeled in this release of Power Analyzer. Use the Early Power Estimator (EPE) to model HPS power.
ID:16080 Input port <name> of "<name>" must be connected with a proper clock source.
ID:16081 Input port <name> of "<name>" must be connected with a proper clock source..
ID:16082 Input port <name> of "<name>" must be connected with a proper clock source..
ID:16083 Input port <name> of "<name>" must not be connected.
ID:16085 Input ports <name>, <name> and <name> of "<name>" must be connected and driven by the same clock source.
ID:16086 Parameter "<name>" of atom "<name>" is set to TRUE but nsleep port is NOT connected.
ID:16090 Model for <number> configuration pin(s) is not included in the IBIS output file
ID:16091 Pin "<name>" has no VCCIO voltage of the configuration pin
ID:16094 Syntax error in IBIS model file <name> at line number <number>, column number <number> : <message>
ID:16095 Syntax error encountered in IBIS model file <text>
ID:16096 Can't find IBIS model file <name>
ID:16097 Truncated pin name "<name>" in IBIS Output File to "<name>" to comply with IBIS <name> standard
ID:16098 Truncated IBIS Output File <name> to "<name>" to comply with IBIS <name> standard
ID:16099 Dummy RLC values generated in IBIS model files for device <name> with package <name> and pin count <number>
ID:16100 IBIS model for pin "<name>" at package pin <name> is not available
ID:16101 Can't write to <Output IBIS file name> due to I/O failure
ID:16102 Analysis and Synthesis (quartus_map) with top-level entity name <Top-level entity name> was not run before EDA Netlist Writer. Generated IBIS model file contains models for reserved and dedicated pins only.
ID:16103 Fitter with top-level entity name <Top-level entity name> was not run before EDA Netlist Writer. Generated IBIS model file is for estimation purposes only.
ID:16104 Model for <number> configuration pin(s) is not included in the IBIS output file
ID:16105 Pin "<name>" has no VCCIO voltage of the configuration pin
ID:16106 Current IBIS Writer does not support RLC package model with mutual coupling for device <name>
ID:16107 IBIS output file with per pin RLC package model with mutual coupling support is unavailable.
ID:16108 The file <name> uses a data radix that is not unsupported
ID:16109 Unable to write to file <name>
ID:16110 Address <number> in file <name> is out of bounds
ID:16111 An error occurred while processing file <name> <text>
ID:16113 Signal "<signal name>" with I/O standard assignment "<I/O standard name>" is assigned to an HSSI <text> pin, however the I/O standard is not compatible with the HSSI <text> pin. Legal I/O standards are "<I/O standard name>".
ID:16114 Attribute "<name>" cannot be specified for multidimensional port "<name>" -- attribute is valid only for single-bit or one-dimensional ports
ID:16115 The periphery placer is unable to place the IOs.
ID:16116 IOs with following <atom_type> atoms that have different scan chain "clk", "data_in", or "update" inputs are placed in the same DQS logic block.
ID:16117 IO_CONFIG atom: <ioconfig_atom_name>
ID:16118 Pin <io_name> placed at PIN_<iopad_location> location.
ID:16119 Please re-run the fitter after manually locking down the pins with different scan-chain inputs into separate <dq_grp_size> DQ group locations.
ID:16123 Can't open the file <file_name>. File size is too large.
ID:16124 Can't analyze file <NAME> - no such file exists
ID:16125 Cannot read the settings file after Analysis & Synthesis
ID:16131 Output port "<text>" of Transceiver Avalon Memory-Mapped Interface "<text>" must connect to at least one valid input port of another component.
ID:16132 No design template found. Install a design template or edit design template search paths, or switch to "Empty project".
ID:16133 No design template selected. Select a design template.
ID:16134 Input port "<text>[<number>]" of "<text>" in "<text>" cannot connect to output port "<text>[<number>]" of "<text>" for node "<text>".
ID:16135 Output port "<text>[<number>]" of "<text>" in "<text>" cannot connect to input port "<text>[<number>]" of "<text>" for node "<text>".
ID:16137 Partial Reconfiguration is not supported for <name> device
ID:16138 Output port "<text>[<number>]" of "<text>" connects to "<text>[<number>]" of "<text>".
ID:16139 Perform full chip erase and program at device index <number>
ID:16140 The specified snapshot to be preserved for partition "<name>" is ignored because the snapshot is earlier than the current compilation stage.
ID:16141 Hard IP for PCI Express block "<name>" with Configuration via Protocol (CvP) enabled is assigned to pin "<name>", which is a non-CvP Hard IP for PCI Express location. Change the pin assignment to pin "<name>".
ID:16142 Ignored Input Delay from Pin to Internal Cells logic option assignment on node <name> because node <name> and node <name> are fed by the same delay chain from input or bidirectional pin <name> but have different assignment values
ID:16143 Changed Input Delay from Pin to Internal Cells option assignment on pin <name> from <number> to <number> -- valid range is from <number> to <number>
ID:16144 Too many Input Delay from Pin to Internal Cells logic option assignments to input pin <name> and its fan-outs because pin uses input register -- honoring only one assignment (setting = <number>)
ID:16145 Ignored Input Delay from Pin to Internal Cells logic option assignment (setting = <number>) to input or bidirectional pin <name> because all of its fan-outs already have assignments of a different delay value (setting = <number>)
ID:16146 Ignored Input Delay from Pin to Internal Cells option assignment (setting = <number>) to input or bidirectional pin <name> -- all fan-out already have assignments of a different delay value or are fed by the pin through global or regional clocks
ID:16147 Ignored Input Delay from Pin to Internal Cells logic option assignment to input or bidirectional pin <name> because pin is a DQS I/O pin
ID:16148 Ignored Input Delay from Pin to Internal Cells logic option assignment to input or bidirectional pin <name> because pin fans out to SERDES receiver <name>
ID:16149 Ignored Input Delay from Pin to Internal Cells logic option assignment on input or bidirectional pin <name> because pin fans out to PLL <name>
ID:16150 Ignored Input Delay from Pin to Internal Cells logic option assignment to input or bidirectional pin <name> because pin assigned to VREF pad <name>
ID:16151 Too many Input Delay from Pin to Internal Cells logic option assignments to input pin <name> and its fan-outs -- honoring only <number> assignment(s) (ignored setting = <number>)
ID:16152 Ignored Input Delay from Pin to Internal Cells logic option assignment to input or bidirectional pin <name> because pin is assigned to global clock <name>
ID:16153 Ignored Decrease Input Delay to Internal Cells logic option assignment to input or bidirectional pin "<name>" because pin is assigned to global clock "<name>" and has no non-global destinations
ID:16154 Ignored Input Delay from Pin to Internal Cells logic option assignment (setting = <number>) from input or bidirectional pin <name> to destination logic cell <name> because it is a global destination
ID:16155 Ignored Input Delay from Pin to Internal Cells logic option assignment (setting = <number>) from input or bidirectional pin <name> to destination logic cell <name> because the routing path does not go through a delay chain
ID:16156 Can't set option <name> to <value> -- option is not used on pin <number>
ID:16157 Can't set option <name> to <number> -- option is not used in pin <name> -- changed to <number>
ID:16158 Can't set option <name> on pin <name> to <number> -- legal setting range is from <number> to <number>
ID:16159 Can't set option <type> on pin <name> to <number> -- legal setting range is from <number> to <number> -- changed to the default <number>
ID:16160 Auto delay chain can't change the delay chain setting on I/O pin <name> since it's a PLL compensated pin
ID:16161 The I/O pin <name> cannot meet the timing constraints due to conflicting requirements. The I/O pin is a PLL compensated I/O, but the setup/hold requirements are in conflict with the source PLL mode(source synchronous or ZDB).
ID:16162 Input pin <name> drives <number> SERDES receivers, but must drive only one SERDES receiver
ID:16163 <name> setting has changed from <number> to <number> on <name>.
ID:16164 The following delay chain settings have been changed for package skew compensation.
ID:16165 Input pin <name> has too many fanouts (number of fanouts is <name> which is larger than the threshold value of <name>) -- the delay chains of the input pin will not be optimized
ID:16167 Invalid preservation snapshot "<snapshot>" specified for partition "<name>".
ID:16168 Project target device "<name>" does not match device specified in the generated IP core. Regenerate the IP core so the target device for the IP core and the project is the same.
ID:16169 Instance "<NAME>" has an ambiguous entity binding
ID:16170 Could be "<NAME>.<NAME>"
ID:16171 Connected PR block data port width is invalid. <name> only supports data port width <name>.
ID:16172 Reserving CvP static routing for Partial Reconfiguration base compile
ID:16173 Routing for spine clock flexibility in Configuration via Protocol flow
ID:16174 Filtering redundant routing nodes for Partial Reconfiguration
ID:16184 Port "<name>" does not exist in primitive "<name>" of instance "<name>"
ID:16185 Can't elaborate user hierarchy "<name>"
ID:16186 Can't elaborate top-level user hierarchy
ID:16187 Close Quartus Prime software and open this project in Interface Planner?
ID:16188 Close Quartus Prime software and open Interface Planner?
ID:16189 Can't launch Interface Planner
ID:16190 Port "<name>" of instance "<name>" of type <name> is not connected
ID:16191 I/O primitive <name> is not supported for the selected family (<name>)
ID:16192 Illegal Configuration of I/O Primitive "<name>": Port "<name>" has multiple fan-outs - it should have a single fan-out to <name> pin.
ID:16193 Illegal configuration of the ALT_BIDIR_DIFF or the ALT_BIDIR_BUF I/O primitive instance <name>: Port "<name>" is not connected properly
ID:16194 Illegal value "<name>" for the <name> parameter for instance "<name>"
ID:16195 Illegal parameter "<name>" with instance "<name>" of I/O primitive type <name>
ID:16196 The instance "<name>" of the I/O primitive type "<name>" has both generic and individual termination assignments.
ID:16197 The parameter "<name>" on the I/O primitive type "<name>" is not supported for the "<name>" device family.
ID:16198 The location assignment on the I/O primitive instance "<name>" specifies an exact pin location. This is not supported for the <family> family in the current version of the Quartus Prime software.
ID:16199 You specified a maximum of <number> wires and a minimum of <number> wires for periphery-core transfer on an atom. The minimum number of wires must be less than the maximum number of wires. Update either the Max Wires for Periphery Core Transfer or Min Wires for Periphery Core Transfer assignment to correct the conflict.
ID:16205 DSP WYSIWYG primitive "<name>" does not support "<name>" exception flag output port for the target device
ID:16206 Interface Planner failed to autoplace cell <id>.
ID:16207 Interface Planner failed to unplace cell <id>.
ID:16208 Interface Planner failed to place cell <id>.
ID:16209 Interface Planner failed to apply project assignments.
ID:16210 Plan updated with currently enabled project assignments.
ID:16215 Default derating is no longer supported. Default timing derating for ES devices is now included in the timing model.
ID:16216 Can't generate test bench files -- test bench template writer for System Verilog is not supported.
ID:16217 Configuration device <name> is currently not supported with the specified argument. Please generate the programming file using .cof file.
ID:16218 The current Interface Planner floorplan is valid.
ID:16220 Unable to create project database files because the encrypted source file cannot be located: "<name>".
ID:16222 An error occurred opening the file <filename>.
ID:16224 One or more registers failed to be packed into a DSP bank due to control signal overuse
ID:16225 One or more registers failed to be packed into a DSP bank due to control signal mismatch
ID:16226 One or more registers failed to be packed into a DSP bank due to a Quartus or user restriction
ID:16227 One or more registers failed to be packed into a DSP bank due to no programmable inverts in the DSP block
ID:16228 One or more registers failed to be packed into a DSP bank due to VCC inputs
ID:16229 One or more output registers failed to be packed into a DSP bank due to multiple fan-outs from the DSP block
ID:16234 No legal location could be found out of <total number> considered location(s). Reasons why each location could not be used are summarized below:
ID:16235 One or more output registers failed to be packed into a DSP bank due to DSP block outputs fanning out to instances that are not registers
ID:16237 Starting register placement <text>for periphery-core transfers
ID:16238 Starting register placement <text>for core-periphery transfers
ID:16239 Register placement <text>for periphery-core transfers ending: elapsed time is <text>
ID:16240 Placed <text> <number> <text> core register(s) <text>
ID:16241 Unable to create project database files because the encrypted source file cannot be located: "<name>".
ID:16242 An I/O Pin connected to Transceiver RX Channel cannot connect to PLD core logic. I/O Pin "<text>" cannot connect to core logic input port "<text>[<number>]" of "<text>" for node "<text>".
ID:16243 Encryption Key Programming File <name> is incompatible with selected device
ID:16245 Illegal constraints of performing periphery to core register paths optimization on register <name>.
ID:16246 Register placement <text>for core-periphery transfers ending: elapsed time is <text>
ID:16250 Input file is incompatible with selected output file. <name> EKP file generation can only accept <name> as input
ID:16251 Invalid connection for core output enable signal associated with EMIF/PHYLite input pin <Pin name>. Connect the output enable port to GND or VCC, depending on your parameter configurations.
ID:16252 Atom: <io_12_lane atom name>
ID:16253 Port: <Port name>[<Port index>] (expected: <Expected connection>, found: <Actual connection>)
ID:16254 Region mask verification failed for <name> mask. The mask does not match the mask generated in base revision compilation. <name>
ID:16255 Static bit settings verification failed for <name> bits. <name>
ID:16256 Strictly preserved region mask verification failed for <name> bits. The mask does not match reference mask generated in the design creation compilation. <name>
ID:16257 Logic verification failed for strictly preserved region <name> bits. <name>
ID:16258 The specified design security keys are not consistent among multiple pages bitstream
ID:16259 Encrypted Programmer Object File only option had been enabled. However you do not encrypt all pages bitstream
ID:16263 You don't have sufficient funds in your account to launch a remote compilation.
ID:16264 Invalid file signature on database model file: "<name>". Rerun the Compiler stage that contains the invalid database.
ID:16265 Port <name> is instantiated twice in your design; once by atom <name> and once by <name>. Only single instantiation of this port is allowed. Modify your design so the port is instantiated only once.
ID:16266 The Clock Buffer "<name>" cannot be constrained to the desired level via the returned assignments
ID:16267 The full compiler reports are being uploaded to the Notification Center server ...
ID:16269 <name> is detected as bad POF
ID:16270 The following <number> IOPLLs are driving clkctrl block <name>, but the target device only supports connectivity from one IOPLL.
ID:16272 The following assignment is from Design Template and cannot be changed/removed.
ID:16274 <name>
ID:16275 Output pin "<name>" of module instance "<name>" is not connected, it will be left dangling without any fan-out logic.
ID:16276 Input pin "<name>" of module instance "<name>" is not connected, its fan-out logic will be driven by <name>
ID:16277 Port "<name>" on the entity instantiation of "<name>" is connected to a signal of width <number>. The formal width of the signal in the module is <number>. The extra bits will be left dangling without any fan-out logic.
ID:16278 Port "<name>" on the entity instantiation of "<name>" is connected to a signal of width <number>. The formal width of the signal in the module is <number>. The extra bits will be ignored.
ID:16279 Port "<name>" on the entity instantiation of "<name>" is connected to a signal of width <number>. The formal width of the signal in the module is <number>. The extra bits will be driven by GND.
ID:16280 Multiple serial flash devices at index <number> do not match. The Programmer supports only identical multiple serial flash devices. Change your flash devices so that flash devices are exactly the same with the same part number.
ID:16281 Device at index <number> only supports 256 Mb and larger serial flash devices. Expected serial flash of <number> <number> Mb, but found serial flash devices of <number> <number> Mb. Ensure that the flash setup for the programming file and the hardware is identical.
ID:16282 Two or more external memory interface (EMIF) IP cores in the same column use different calibration routines. The error occurs when IP cores placed in the same column are generated in different versions of Quartus; or, when a memory interface for the hard processor system (HPS) is placed in the same column with a normal memory interface. Regenerate all memory interface IP cores in the current version of Quartus if cores were generated in different Quartus versions. A normal memory interface cannot be placed in the same column as an HPS memory interface.
ID:16283 <EMIF IP or IO_AUX atom name> (hex file: <File containing the calibration code>)
ID:16284 Device at index <number> does not support multiple flash devices. Make sure your programming file is generated for a single flash device.
ID:16285 Can't find design template package <name>
ID:16286 Specify a design template package and installation destination directory
ID:16287 Directory "<name>" does not exist. Do you want to create it?
ID:16288 Can't create destination directory "<name>"
ID:16289 Design template installation failed
ID:16290 Found <number> <type> blocks in your design, however your device can only accommodate <number> <type> blocks. Reduce the number of specified block in the design or select a larger device.
ID:16291 Detected SOF file compiled with <name> configuration scheme which is not supported for <name> configuration mode file generation.
ID:16292 Device <name> does not support Passive Serial configuration and cannot be added as a configuration slave for Active Serial Multi-Device Configuration scheme.
ID:16293 You specified maximum delay of <time> and minimum delay of <time> for periphery-core transfer on an atom. The minimum delay must be less than the maximum delay. Update either the Max Delay for Periphery Core Transfer or Min Delay for Periphery Core Transfer assignment to correct the conflict.
ID:16295 Ignoring virtual IO assignment for <name>
ID:16296 Pin <name> is constrained to a location (<name>) which does not support LVDS Soft-CDR mode.
ID:16297 An error has occurred while trying to initialize the plan stage.
ID:16298 Programming file uses ISP settings from <name> image
ID:16301 IOPLL reference clock is not connected to a clock pin
ID:16302 PLL: <PLL name>
ID:16303 <optimization_mode> optimization mode selected -- <metric> will be prioritized at the potential cost of <degraded_metric>
ID:16304 Mode behavior is affected by advanced setting <compiler_setting> (default for this mode is <mode_default>)
ID:16305 Feedback path used by PLL(s) in location <name> was routed for <compensation type (routed)> clock compensation but the clock targeted for compensation was routed as a <compensation type (target)> clock
ID:16306 Port "<name>" can not be connected in primitive "<name>" of instance "<name>"
ID:16307 EQ should NOT be bypassed at high data-rate.
ID:16310 IO clock crossed the data register.
ID:16311 The generated programming file needs at least <number> cascaded serial flash devices
ID:16312 The generated programming file needs at least <number> cascaded serial flash devices
ID:16327 WYSIWYG RAM primitive "<name>" "<name>" Mix Port Width with "<name>" in "<name>" is not allowed
ID:16328 The real-time ISP option for Max 10 is selected. Ensure all Max 10 devices being programmed are in user mode when requesting this programming option
ID:16333 Value "<text>" for LPM_HINT parameter contains syntax error(s)
ID:16336 WYSIWYG RAM primitive "<name>" when using "<name>", "<name>" need to be used
ID:16337 Your design settings specify that smart compilation should be used during compilation, however, the target device family does not support smart compilation. Remove the SMART_RECOMPILE assignment from your Quartus Prime Settings File (.qsf).
ID:16338 WYSIWYG RAM Primitive "<name>" the mixed-port read-during-write must use don't care when operation mode is set to "<name>" .
ID:16341 You used the quartus_syn executable to run synthesis, however this executable is not supported for device family <name>. Use the quartus_map executable to run synthesis or change the device family to a family that supports the quartus_syn executable.
ID:16342 Maximum depth for <name> is 2047 for WYSIWYG RAM primitive "<name>"
ID:16343 In WYSIWYG primitive, "<name>" port "<name>" does not support in operation mode "<name>"
ID:16344 Design requires <Group Size> contiguous fully bonded lanes, but the target device for your design has a maximum of <Max Group Size> contiguous lanes. Choose a different target device for your design.
ID:16349 WYSIWYG RAM primitive "<name>" cannot have "<name>" port and "<name>" connected because parameter "<name>" is not set.
ID:16350 When in its current operating mode, WYSIWYG RAM primitive "<name>" port "<name>" and "<name>" need to be connected
ID:16352 The number of parallel threads you specified, <number>, is not supported by local machine. Changing the maximum number of parallel threads to <number>.
ID:16353 Expected the <name> device at index <number> to be of type <name>, but detected device of type <name> instead. Ensure that you are using the correct programming file.
ID:16359 DSP Systolic Mode inferencing failed when attempting to combine the top DSP block "<name>" and the bottom DSP block "<name>" into one hard DSP block operating in systolic mode.
ID:16360 DSP output register inferencing into DSP block "<name>" failed.
ID:16361 DSP block WYSIWYG primitive "<name>" has clear port "clr[<number>]" connected, but you did not specify the clear type -- parameter "clear_type" set to "none". Set the clear_type parameter to either 'aclr' or 'sclr' depending on your design requirements.
ID:16362 You set the operation mode set to "sp_mult_acc" for DSP block WYSIWYG primitive "<name>" which requires the output register to be registered. Select a clock source for the output register.
ID:16363 <text>
ID:16364 DSP double accum register inferencing into DSP block "<name>" failed.
ID:16365 The following timing edges are non-unate. Timing analysis results may be pessimistic.
ID:16366 Your design has the autonomous hard IP for PCI Express mode enabled, but the Fitter cannot find a hard reset controller connected to the Hard IP for PCI Express block < <text> >. Add a hard reset controller or turn off the autonomous hard IP for PCI Express mode.
ID:16368 Top-level design entity "<name>" is undefined
ID:16383 Silicon revision parameter for the following EMIF/PHYLite atoms do not match the silicon revision of the currently selected device (<Silicon revision of the currently selected device>). Regenerate the IP cores using the current device (<Currently selected device>).
ID:16384 <Atom name> (<Silicon revision parameter>)
ID:16387 Inject fault at SOF frame <number>, bit(s): <name> \t\tBS frame <number>, bit(s): <name> \t\tEDCRC frame <number>, bit(s): <name>
ID:16389 Can't read or find LMF file <name>
ID:16390 Library Mapping File <name> contains one or more syntax errors
ID:16392 Update <name> option bit to value: <name>
ID:16393 Due to large clock skew, the bonding channel FIFO PLD_TX_CLK or PLD_RX_CLK signal cannot use the LPCLK clock network. Assign a different global clock network to signal < <name> >.
ID:16394 LMF mapping record <name> -> <name> for node "<name>" has no valid entry for the following port(s).
ID:16395 Invalid port name "<name>"
ID:16398 Transceiver group with data pin < <name> > has <number> channels, but only <number> channels are connected to top-level ports. Connect all data pins to a top-level port.
ID:16399 The Quartus Prime software cannot automatically create generated clock on input port "<name>" of the channel. Use the SDC command \'create_generated_clock -master\' to create a clock on input port "<name>" with the appropriate master clock specification. This allows the Quartus Prime software to apply extra clock uncertainty for making timing closure robust.
ID:16400 Transceiver channel data signal < <name> > is assigned to pin < <name> >, but the specified pin is not compatible with the data signal. Assign the specified data signal to pin < <name> >.
ID:16404 The "<command>" command is available only in the Quartus Prime Pro Edition (PE) software.
ID:16405 Could not find a loaded names database. Use the load_db command to open the names database first.
ID:16406 <number> global input pin(s) will use non-dedicated clock routing
ID:16407 Source REFCLK I/O is not placed onto a dedicated REFCLK input pin for <name>, placed at <location>
ID:16409 An in-system source or probe read or write transaction failed. Verify that the connection ID provided to the External Memory Interface Toolkit matches the appropriate in-system source or probe (ISSP) in your design and that the ISSP is not being used by another client.
ID:16410 The traffic generator did not finish within the allotted time limit. Shorten the duration of the traffic generator.
ID:16411 Transceiver channel <<name> >'s clkout is used as REFCLK for cascade FPLL, which will result in high TX jitter.
ID:16414 Reference clock pin < <name> > is locked to RX data pin location < <name> >, however the specified data pin location must be used by a CMU PLL. Assign the reference clock pin to another RX data pin location.
ID:16468 When in its current operating mode, WYSIWYG RAM primitive "<name>" "<name>" is out of range
ID:16469 Source REFCLK I/O cannot be routed using dedicated clock routing for <name>, placed at <location>
ID:16472 Performing driver margining on <type>. This may take a few minutes.
ID:16473 Port <name> is connected in the altera_syncram megafunction -- <name> block for device family <name> of the altera_syncram megafunction cannot use wraddrstall signal
ID:16474 Cannot implement altera_syncram megafunction because RAM size is too large to use with OPERATION_MODE parameter set to value <value>
ID:16475 In altera_syncram megafunction, clock0 port must always be connected
ID:16476 In altera_syncram megafunction, clocken1 port can only be used when clock1 port is used
ID:16477 In altera_syncram megafunction, clocken3 port can only be used when clock1 port is used
ID:16478 altera_syncram megafunction's <par> parameter cannot be set to value <value> for <family> device family
ID:16479 Parameter error: altera_syncram megafunction's <name> parameter is set to an illegal <value> value -- legal values for parameter <name> are <values>
ID:16480 Parameter error: altera_syncram megafunction's <name> parameter is set to an illegal <value> value -- legal values for parameter <name> are <choices>
ID:16481 Parameter error: <name> parameter of altera_syncram megafunction set to value <value> is illegal -- legal values for <name> parameter must be <name>
ID:16482 In altera_syncram megafunction, cannot use <name> port when parameter <name> is less than or equal to 1
ID:16483 Connected <name> port of the altera_syncram megafunction is unused with the current set of parameters
ID:16484 Must connect <name> port of altera_syncram megafunction when using current set of parameters
ID:16485 Cannot use different <clock or clear> ports for <name> port and <name> port in altera_syncram megafunction
ID:16487 In altera_syncram megafunction, when OPERATION_MODE parameter is set to <value>, total number of bits (width x depth) between port A and port B must be the same
ID:16488 Cannot use port A width with port B width in altera_syncram megafunction
ID:16489 Cannot use port A and port B width values with RAM_BLOCK_TYPE parameter value set to AUTO and current set of parameters in altera_syncram megafunction
ID:16491 Cannot have disabled and enabled clock enables in <name> registers and on different sides of RAM block of altera_syncram megafunction -- if using the same clock, clock enables must be either disabled or enabled on both sides of RAM block
ID:16492 Not using extra address lines in altera_syncram megafunction design -- <number> memory words in side <name> specified but total number of address lines is <value>
ID:16493 Insufficient address lines in altera_syncram megafunction design -- <number> memory words in side <name> specified but total number of address lines is <value>
ID:16494 In altera_syncram megafunction, ECC feature cannot be used for the specified combination of ports and parameters
ID:16495 In altera_syncram megafunction, the parameter <par> cannot be set to the value <name> for the RAM block <RAM_BLOCK>
ID:16496 In altera_syncram megafunction, output latch for port <port> cannot be asynchronously cleared for the specified device family <dev>, the clear will be ignored.
ID:16497 Ignoring <name> port -- <name> block for device family <name> of altera_syncram megafunction cannot use rden signal
ID:16498 <name> device family does not support the specified configuration. altera_syncram megafunction will support it by tying the byte-enable to the write enable of the relevant slices.
ID:16516 WYSIWYG RAM primitive "<name>" maximum width ratio for Port A data width A and Port B data width is 4!
ID:16518 WYSIWYG RAM primitive "<name>" port "<name>" and "<name>" cannot connect at the same time
ID:16536 WYSIWYG RAM primitive "<name>" must have "<name>" parameter and set to true when enable_ecc_encoder_bypass is set
ID:16537 Cannot use READ_DURING_WRITE_MODE_PORT_A parameter value set to <name> for device family <family_name> in altera_syncram megafunction
ID:16538 Cannot use READ_DURING_WRITE_MODE_PORT_B parameter value set to <name> for device family <family_name> in altera_syncram megafunction
ID:16539 altera_syncram megafunction's <param name> parameter (<param value>) and <param name> parameter (<param value>) must be set with same value when <operation mode name> is set to <operation mode value> for <device family> device family
ID:16540 In altera_syncram megafunction, cannot use clock1 when <operation mode name> is set to <operation mode value> for <device family> device family
ID:16541 In altera_syncram megafunction, cannot have different clock enable setting for <clock enable> and <clock enable> for device family <device> as they use the same clock
ID:16542 In altera_syncram megafunction, input clear on <clear parameter> parameter is not supported for the specified device family <device>
ID:16543 Incompatible pin pair assignment. RX pin < <text> > is assigned to pin location <text>; TX pin < <text> > is assigned to pin location <text>, but the pin locations are not compatible because they are merged through the Assignment Editor into a single duplex channel. To correct the incompatibility, assign the specified RX pin to pin location <text> or remove the pin assignments.
ID:16545 WYSIWYG RAM primitive "<name>" cannot use "<name>" in true dual port.
ID:16547 Transceiver group with channel < <name> > uses <number> xN clock lines, which exceeds the xN clock network capacity. Reduce the number of xN clock lines used to two.
ID:16548 Transceiver PLL "<name>" has illegal data rate of <number> -- the maximum data rate when using the xN transmitter clock network to drive bonded transmitter channels cannot exceed <number>
ID:16551 Clock buffer <name> has no fanout.
ID:16553 WYSIWYG RAM Primitive "<name>" maximum for "<name>" in "<name>" is 2!
ID:16554 WYSIWYG RAM primitive "<name>" must have width of "<name>" port set to 8.
ID:16556 The synthesis RTL for <NAME> has not been generated. Generate the synthesis RTL from within Platform Designer.
ID:16557 Fitter post-fit operations ending: elapsed time is <time>
ID:16560 HPS F2SDRAM AXI port 0 and port 2 are not supported on the Arria 10 ES silicon. Use a non ES part or disconnect the F2SDRAM AXI port 2 or/and port 0.
ID:16561 The Signal Tap Logic Analyzer instance "<instance>" can't tap node "<bus_name>" because it is a bus. The Signal Tap Logic Analyzer only taps individual nodes. Remove the bus node and add each bit of the bus separately and then try to tap the node again.
ID:16563 In WYSIWYG primitive "<name>" port "<name>" and port "<name>" cannot connect at the same time
ID:16564 WYSIWYG RAM Primitive "<name>" maximum for "<name>" in "<name>" is two.
ID:16565 When using Forwarding Logic in WYSIWYG RAM Primitive "<name>" byte-mask features cannot be connected.
ID:16566 When in its current operating mode, WYSIWYG RAM primitive "<name>" mix port width is not allow on "<name>"
ID:16568 When using Forwarding Logic feature in WYSIWYG RAM primitive "<name>", only "<name>" operation mode is allowed
ID:16570 When using ECC Encoder bypass feature, WYSIWYG RAM primitive "<name>" "<name>" & "<name>" need to be connected
ID:16573 The Incremental Route Signal Tap flow is not possible at this time. A parameter change has been made which requires resynthesis. Rerun Synthesis and try again.
ID:16574 The Incremental Route Signal Tap flow is not possible at this time. A change to the set of Pre-Synthesis taps was made which requires resynthesis. Rerun Synthesis and try again.
ID:16575 The Incremental Route Signal Tap flow has failed. Rerun Synthesis and try again.
ID:16576 The Incremental Route Signal Tap flow is not possible at this time. Changes to the set of Pre-Synthesis taps and the Signal Tap parameters were made which requires resynthesis. Rerun Synthesis and try again.
ID:16577 When using ECC Encoder bypass feature, WYSIWYG RAM primitive "<name>" "<name>" must set as eight
ID:16578 The input buffer < <name> > drives both HSSI nodes and non-HSSI nodes, however the specified input buffer can drive only HSSI nodes. Use a separate input buffer to drive non-HSSI nodes < <name> >.
ID:16579 This option is not supported in Quartus Prime Pro Edition (PE) software
ID:16581 In WYSIWYG RAM primitive "<name>" "<name>" parameter need to specified
ID:16582 In quad-port mode, the width of WYSIWYG RAM primitive "<name>" "<name>" must be less than ten. Change the width of the specified primitive to ten or less or change the operating mode.
ID:16583 The distance between master cgb and channel for xN Transceiver Group "<name>" is <number> banks. The maximum distance allowed is 2 banks to meet xN clock network jitter specification.
ID:16584 In "<name>", the width ratio must be less than four for WYSIWYG RAM primitive "<name>". Change the width ratio of the specified primitive to four or less or change the operating mode.
ID:16586 When signal ENA0 or ENA1 is connected in WYSIWYG RAM primitive "<name>" "<name>", port "<name>" also must be connected. Connect the specified clock port.
ID:16598 All first-stage pipeline registers must share the same clock source for DSP block WYSIWYG primitive "<name>". Change your design so the first-stage pipeline registers feeding the DSP block WYSIWYG primitive share the same clock source.
ID:16599 All second-stage pipeline registers must share the same clock source for DSP block WYSIWYG primitive "<name>". Change your design so the second-stage pipeline registers feeding the DSP block WYSIWYG prmitive share the same clock source.
ID:16600 You connected the "accumulate" port for the DSP block WYSIWYG primitive "<name>" which requires the output register to be enabled. Select a clock source for the output register.
ID:16602 WYSIWYG RAM primitive "<name>" cannot use coherent read and byte-enable mask features at the same time.
ID:16604 When in its current operating mode, WYSIWYG RAM primitive "<name>" "<name>" is out of range
ID:16605 You must open a project to use Design Space Explorer II
ID:16606 WYSIWYG RAM primitive "<name>" must have the "<name>" port connected when "<name>" port is connected
ID:16607 Fitter routing operations ending: elapsed time is <time>
ID:16608 When using Forwarding Logic in WYSIWYG RAM primitive "<name>" wide mode is not allow in "<name>"
ID:16609 In true dual-port mode, WYSIWYG RAM primitive "<name>" width of Port A and Port B cannot be more than twenty. Change the number of ports of the specified primitive to twenty or less or change the operating mode.
ID:16610 WYSIWYG RAM primitive "<name>" mix port width is not allow in "<name>" when forwarding logic is enabled
ID:16611 OCT Block "<name>" cannot terminate pins "<name>" and "<name>" because they have different voltages: "<name>" and "<name>" respectively. Change your pin assignments so that only pins with the same voltage are connected to the same OCT block
ID:16612 OCT Blocks "<name>" and "<name>" cannot be merged because they have different configurations: "<name>" and "<name>" respectively. Change your assignments so that the OCT blocks have the same configuration
ID:16613 OCT Blocks "<name>" and "<name>" cannot be merged because they are in different partitions: "<name>" and "<name>" respectively. Change your design so the OCT blocks are in the same partition
ID:16614 OCT Block "<name>" cannot terminate pins "<name>" and "<name>" because they have different series termination values: "<name>" and "<name>" respectively. Change your pin assignments so that only pins with the same series termination value are connected to an OCT block.
ID:16615 OCT Block "<name>" cannot terminate pins "<name>" and "<name>" because they have different parallel termination values: "<name>" and "<name>" respectively. Change your pin assignments so that only pins with the same parallel termination value are connected to an OCT block.
ID:16618 Fitter routing phase terminated due to routing congestion. Congestion details can be found in Chip Planner.
ID:16620 Traffic generator stalled while margining <type>. Actual margins on this edge may be larger than reported. Attempting to recover the interface by resetting and recalibrating.
ID:16621 Address: <address> Setting: <setting> Value: <value>
ID:16623 Interface Planner already initialized. Close and reopen Interface Planner to reinitialize.
ID:16624 Initialize Interface Planner before running command
ID:16625 Interface Planner failed to initialize
ID:16626 Interface Planner initializing
ID:16627 Interface Planner initialized: elapsed time is <create_time>
ID:16628 Interface Planner shut down
ID:16636 <name>
ID:16637 Interface Planner already initialized once in the current Tcl shell. Close the current Tcl shell to reinitialize.
ID:16638 Removed following I/O cells that do not connect to top-level pins or have illegal connectivity
ID:16639 Too many debug fabrics required to instrument the design. Currently, only <max_fab> debug fabrics per design are supported.
ID:16640 You cannot tap nodes in different Partial Reconfiguration or Reserved Core regions with the same Signal Tap instance. Change your design so that for each Signal Tap instance, all the taps are contained on one side of a Partial Reconfiguration or Reserved Core region boundary. The following nodes and their respective partitions were requested for Signal Tap instance <instance>: <node_spec>
ID:16641 Debug and performance IP cores must be instantiated either within or outside of a Partial Reconfiguration or Reserved Core region boundary. Change your design so that your debug and performance IP cores are fully contained within or outside a Partial Reconfiguration or Reserved Core region.
ID:16642 <name>
ID:16643 Found <assignment name> assignments found for "<pin name>" pin with multiple values. Using value: "<value used>"
ID:16644 Assignment value for "<port name>": "<assignment value>"
ID:16646 Design is incompatible with the current target device. Select a compatible device or modify the design.
ID:16647 Fitter failed during Interface Planner operation Interface Planner is closing.
ID:16648 Design template installation was successful
ID:16651 Close Interface Planner and open this project in the Quartus Prime software?
ID:16652 Close Interface Planner and open the Quartus Prime software?
ID:16653 Can't launch Quartus Prime software
ID:16654 Design template installation was successful. Warning: The installed design template is not supported in the current version of the Quartus Prime software. Download the latest version of the design template from the Design Store or use the supported version of the Quartus Prime software.
ID:16656 Could not find solution for <number> of <number> core registers(s) constrained <text>. Placement and routing for these <number> connection(s) were not committed -- please relax the constraint.
ID:16657 Could not find solution for <number> of <number> core register(s) constrained <text>. Placement and routing for these <number> connection(s) were not committed -- please relax the constraint.
ID:16658 Example Register Name: <text>
ID:16659 Project assignments are not applied to the Interface Planner plan. Run update_plan to apply project assignments to the Interface Planner plan.
ID:16660 Interface Planner already updated with project assignments. Run reset_plan to revert to an unplanned state.
ID:16661 Current device does not support the project
ID:16663 The IP cores in your design may need to be updated. Open your project in the Quartus Prime software to review the status of the IP cores and update them as needed.
ID:16665 Cannot unplace cell <cell_name> because the cell is constrained to the location "<location_name>"
ID:16666 WYSIWYG primitive "<name>" is not compatible with the current device family
ID:16667 HSSI block < <name> > with input port < <name> > is driven by signal < <name> >, however, the input port < <name> > can only be driven by a primary input pin. Change your design so that input port < <name> > is driven by a primary design input pin.
ID:16668 You specified Multi-file-compilation-unit (MFCU) which is not compatible with auto-discovery. We are turning off auto-discovery. To avoid this warning, turn off auto-discovery explicitly by setting AUTO_DISCOVERY_AND_SORT to OFF in your QSF.
ID:16674 Quartus Prime could not automatically create generated clock on input port "<name>" of the channel. Use the SDC command \'create_generated_clock -master\' to create clock on input port "<name>" with the appropriate master clock specification. This allows Quartus Prime to apply extra clock uncertainty for making timing closure robust.
ID:16677 Loading <snapshot_name> database.
ID:16678 Successfully loaded <snapshot_name> database: elapsed time is <elapsed_time>.
ID:16679 Option setting in SOF file is different with current option setting. Do you want to overwrite it?
ID:16680 I/O pin <name> has the LVDS I/O standard assigned to it, however the I/O lane cannot contain pins with the LVDS I/O standard. Modify your design so that pins in the I/O lane are not assigned the LVDS I/O standard.
ID:16681 Advanced Physical Optimization failed to find a legal placement. Disable ADVANCED_PHYSICAL_OPTIMIZATION in your Quartus Prime Settings File (.qsf) and restart the compilation.
ID:16682 Error writing Interface Planner constraints file.
ID:16683 Successfully wrote <filename> Interface Planner floorplanning constraints file
ID:16685 Hard IP for PCI Express block < <name> > has only two channels associated with it, therefore it can only support x1 and x2 channel placement. Modify your design to use x1 and x2 channel placement or select a larger device.
ID:16687 Device <name> does not support using bitstream encryption and bitstream compression features simultaneously.
ID:16689 Missing encryption lock file input file name
ID:16690 WYSIWYG RAM primitive "<name>". Only the "<name>" operating mode is allowed. Ensure that port A and port B data widths are the same when using coherent read mode.
ID:16691 WYSIWYG RAM primitive "<name>" you have specified an illegal operation mode
ID:16692 WYSIWYG RAM primitive "<name>" port "<name>" in "<name>" is not allowed to be connected!
ID:16693 WYSIWYG RAM primitive "<name>" ports "<name>" and "<name>" cannot be connected at the same time when using coherent read mode.
ID:16694 Part <Migration device> is listed as one of the migration devices. External memory interfaces may have a lower performance on this part.
ID:16695 Interface Planner plan not validated. Validate the Interface Planner plan before proceeding.
ID:16696 WYSIWYG primitive "<name>" parameter "<name>" cannot be set to true when using coherent read mode.
ID:16697 WYSIWYG primitive "<name>" parameter "<name>" cannot set to false when port "<name>" is connected.
ID:16698 RZQ name "<name>" is already used in the design. Change the name of the RZQ pin for the RZQ GROUP assignment so that it is unique.
ID:16699 Equivalent device ir and dr shift commands
ID:16701 <command>
ID:16702 No editable memory instance was found.
ID:16703 Can't acquire data multiple times on Signal Tap instance "<name>" when acquiring data from multiple instances simultaneously
ID:16704 Signal Tap data acquisition is in <type> state: <text>
ID:16705 Error #<number> <name>: <name>.
ID:16706 Error #<number> <name>: <name> in frame <name> at bit <name> and frame <name> at bit <name>.<name>
ID:16707 Corrected error #<number> : <name> in frame <name> at bit <name> and frame <name> at bit <name> and.<name>
ID:16708 Cannot set READ_DURING_WRITE_MODE_MIXED_PORTS parameter value set to <name> for device family <family_name> in altera_syncram megafunction
ID:16709 Parameter <parameter1> can only be set to <parameter1_value> when parameter <parameter2> is set to <parameter2_value>
ID:16711 Port <port> can only be used when parameter <parameter> is set to <parameter_value>
ID:16712 Parameter <parameter> can only be set to <parameter_value> for device family <device>
ID:16713 Parameter ENABLE_COHERENT_READ can only be set to TRUE when parameters WIDTH_A and WIDTH_B have the same value. Disable the ENABLE_COHERENT_READ feature, or change the value of the parameter the WIDTH_A or WIDTH_B parameter.
ID:16714 <parameter> feature is not available for device family <device>
ID:16716 Cannot set OPERATION_MODE to <operation_mode> with <ram_block_type> block in altera_syncram megafunction
ID:16717 Supply voltage <value> set to the '<name>' power rail is illegal with respect to core voltage <core_voltage>. Change the supply voltage to a legal value. Refer to the Pin Connection Guidelines for the target device family for legal values.
ID:16718 HSSI reference clock divider < <name> > and input buffer < <name> > are in different design partitions, < <name> > and < <name> >, respectively. Modify your design so that the HSSI reference clock divider and input buffer are in the same design partition.
ID:16719 Your design has input buffer < <name> > that drives HSSI reference clock divider < <name> > and other logic. Modify your design so that the HSSI reference clock divider acts as a wire.
ID:16720 Propagated pin attribute from lower-level pin "<name>" to top-level pin "<name>". Did not propagate pin attribute to the other top-level pins listed below
ID:16721 Did not propagate pin attribute from lower-level pin to top-level pin "<name>"
ID:16722 The SEU internal scrubbing feature is only supported for select Cyclone V and Cyclone V SoC devices. Contact your Intel sales representative for information on these devices and access to the SEU internal scrubbing feature.
ID:16723 The SEU internal scrubbing feature is only supported for select Cyclone V and Cyclone V SoC devices. Contact your Intel sales representative for information on these devices and access to the SEU internal scrubbing feature.
ID:16727 Project archive restoration failed. Your project may be archived from a different Quartus version or may be corrupted. Verify that your project works correctly and then create a new archive for your design.
ID:16731 Global signal "<name>" can only be used within one partition, but is connecting partitions "<name>" and "<name>". Connect signals using partition boundary signals, or merge the partitions that require shared signals.
ID:16734 Loading "<snapshot_name>" snapshot for partition "<partition_name>".
ID:16735 Verilog HDL warning at <location>: actual bit length <number> differs from formal bit length <number> for port "<string>"
ID:16736 Importing <snapshot> snapshot of <block> from revision <revision> into partition "<partition>".
ID:16737 Importing <snapshot> snapshot from <vlnv> into partition "<partition>".
ID:16739 WYSIWYG RAM primitive "<name>" must have "<name>" or "<name>" parameter
ID:16742 Verilog HDL warning at <location>: module <name> instantiation should have an instance name
ID:16743 Verilog HDL warning at <location>: empty port in <string> declaration
ID:16744 Verilog HDL warning at <location>: macro <string> redefined
ID:16745 Verilog HDL warning at <location>: concatenation with unsized literal, will interpret as 32 bits
ID:16746 Verilog HDL warning at <location>: <string> is already implicitly declared on line <number>
ID:16747 Verilog HDL warning at <location>: attribute target identifier <string> not found in this scope
ID:16749 Verilog HDL warning at <location>: identifier <string> is used before its declaration
ID:16750 Verilog HDL warning at <location>: "<string>" inside always_comb block does not represent combinational logic
ID:16752 Verilog HDL warning at <location>: potential always loop found
ID:16753 Verilog HDL warning at <location>: <string> shift count is greater than or equal to the width of the value
ID:16754 Verilog HDL warning at <location>: variable "<string>" should be declared as automatic or static
ID:16755 Verilog HDL warning at <location>: ignoring non-constant initial value of "<string>"
ID:16756 Verilog HDL warning at <location>: case item condition for casex/casez, if non-constant, is not synthesizable
ID:16758 Support for this command is preliminary.
ID:16759 VHDL warning at <location>: formal port or parameter "<string>" has no actual or default value
ID:16760 VHDL warning at <location>: case choice should be a locally static expression
ID:16761 VHDL warning at <location>: actual for formal port "<string>" is neither a static name nor a globally static expression
ID:16762 VHDL warning at <location>: array type case expression should be of a locally static subtype
ID:16763 VHDL warning at <location>: size mismatch with variable slice
ID:16764 VHDL warning at <location>: incomplete sensitivity list specified; assuming completeness
ID:16765 Clock buffer "<node>" is incompatible with the required global signal types of its destination ports. Modify your design to change the clock buffer type for the specified signal or the required global signal type of the destination nodes.
ID:16766 Clock buffer "<node>" can be instantiated in a higher level partition
ID:16767 Can't insert required clock buffer at node "<node>" as the partition is read-only. Unlock the partition to allow the clock buffer to be inserted.
ID:16768 Can't use existing clock buffer for mandatory global fanout at node "<node>". Ensure that the global signal types are consistent in your design and that the existing clock buffer can drive the required global destinations without violating partition boundaries.
ID:16769 The global signal types are incompatible. Ensure that the global signal types are consistent in your design, or modify the type of the clock buffer.
ID:16770 The clock buffer cannot drive the required destination ports without violating partition boundaries. Modify your design to instantiate a clock buffer that drives the required global destination ports without violating partition boundaries.
ID:16771 More than one clock buffer is required to drive mandatory global destination ports of node "<node>". Ensure that all split global/non-global fanout satisfies partition boundary requirements. Duplicate boundary ports for the signal as required, such that each downstream boundary port has only all global or non-global destinations.
ID:16772 Node "<node>" has both required global and non-global fanout. If a clock buffer is required upstream to drive other global destinations, then duplicate the node (if it is a boundary port) such that each boundary port drives either all global or all non-global destinations.
ID:16775 Can't complete design placement. Cell <cell_id> has no legal locations. Change the placement of other cells or adjust your constraints until all unplaced cells have at least one legal location available.
ID:16776 The error detection cyclic redundancy check (EDCRC) feature is not supported for device <name>. Disable the EDCRC feature in the Device and Pin Options dialog box, or remove the EDCRC block from your design.
ID:16777 Successfully deleted compilation database "<name>".
ID:16778 An error occurred while deleting the compilation database "<name>". <msg>.
ID:16779 VHDL warning at <location>: actual port "<name>" of mode "<text>" is not associated with formal port "<name>" of mode "<text>"
ID:16780 Device view ID <view_id> is illegal
ID:16781 Device part "<name>" is illegal
ID:16782 Family "<name>" is illegal
ID:16783 Interface Planner does not support AUTO device part selection for family <family>. Specify a specific target device.
ID:16784 Device family <name> not supported by Interface Planner
ID:16785 Current target device <part> has no pinout defined. Specify a different target device.
ID:16786 No open project exists
ID:16788 Net "<name>" does not have a driver at <location>
ID:16790 Ram "<name>" has no write-port on it at <location>
ID:16792 VHDL Association List warning at <location>: formal <name> that is associated individually cannot be associated with actual of OPEN
ID:16793 The specified snapshot to be preserved for partition "<name>" is ignored because an ECO compile is being performed.
ID:16794 VHDL Subprogram Body warning at <location>: function "<name>" does not always return a value
ID:16801 The instance assignment (<assigment_name>) uses deprecated "entity:inst" style. Instance paths should be specified using only instance names.
ID:16802 Verilog HDL warning at <location>: cannot find port <string> on this module
ID:16803 Verilog HDL warning at <location>: can't index into non-array type <string> for <string>
ID:16804 Verilog HDL warning at <location>: invalid expression in target
ID:16805 Verilog HDL warning at <location>: index is always out of bounds for array <string>
ID:16806 Verilog HDL warning at <location>: instantiating unknown module <string>
ID:16807 Verilog HDL warning at <location>: parameter <string> depends on uninitialized variable
ID:16808 Verilog HDL warning at <location>: <string> cannot be used in expression
ID:16809 Verilog HDL warning at <location>: <string> is already declared
ID:16810 Verilog HDL warning at <location>: no definition for port <string>
ID:16811 Verilog HDL warning at <location>: <string> is not declared
ID:16812 Verilog HDL error at <location>: port connections cannot be mixed ordered and named. Or there might be a trailing comma in named port connection.
ID:16813 Verilog HDL warning at <location>: indexing (of <string>) is not allowed in a constant expression
ID:16814 Verilog HDL error at <location>: unknown literal value <string> for parameter <string> ignored
ID:16815 Verilog HDL warning at <location>: <string> is not a constant
ID:16816 Verilog HDL warning at <location>: unmatched <string> translate/synthesis off pragma found; matching pair with same keywords is required
ID:16817 Verilog HDL warning at <location>: overwriting previous definition of <string> <string>
ID:16818 Verilog HDL warning at <location>: block identifier is required on this block
ID:16819 Verilog HDL warning at <location>: variable <string> is too small to store FSM state <number>. FSM not extracted
ID:16820 Verilog HDL warning at <location>: constant expression cannot contain a hierarchical identifier
ID:16821 Verilog HDL info at <location>: going to vhdl side to elaborate module <string>
ID:16822 Verilog HDL info at <location>: back to verilog to continue elaboration
ID:16823 Verilog HDL warning at <location>: re-analyze <string> <string> since <string> <string> is overwritten or removed
ID:16824 Verilog HDL error at <location>: constant expression required
ID:16825 Verilog HDL error at <location>: premature EOF found in <string> section, missing <string>
ID:16826 Verilog HDL error at <location>: operator <string> is only allowed in a <string>, not in <string>
ID:16827 Verilog HDL error at <location>: cannot open include file <string>
ID:16828 Verilog HDL error at <location>: <string> does not accept dimensions
ID:16829 Verilog HDL error at <location>: <string> does not accept an initial value
ID:16830 Verilog HDL warning at <location>: signing ignored on type <string>
ID:16831 Verilog HDL error at <location>: <string> statement is invalid here
ID:16832 Verilog HDL warning at <location>: absolute path name not allowed for <> include files
ID:16833 Verilog HDL error at <location>: mismatch in closing label <string>; expected <string>
ID:16834 Verilog HDL warning at <location>: operator <string> not yet supported for synthesis
ID:16835 Verilog HDL error at <location>: operator <string> not yet supported for synthesis
ID:16836 Verilog HDL error at <location>: cannot have packed dimensions of unpacked type <string>
ID:16837 Verilog HDL error at <location>: X or Z in value for 2-state enum <string> is not allowed
ID:16838 Verilog HDL error at <location>: cannot create implicit enum value for <string> since previous value contains X or Z
ID:16839 Verilog HDL error at <location>: invalid recursive module <text> instantiation of <string>
ID:16840 Verilog HDL error at <location>: size mismatch in enum definition for literal '<string>'
ID:16841 Verilog HDL error at <location>: <string> has no port called <string>
ID:16842 Verilog HDL warning at <location>: port <string> is already connected
ID:16843 Verilog HDL error at <location>: port <string> is already connected
ID:16844 Verilog HDL error at <location>: port <string> is not connected on <string> call <string>
ID:16845 Verilog HDL error at <location>: argument of <string> should be an identifier
ID:16846 Verilog HDL error at <location>: dimension for <string> is out of bounds
ID:16847 Verilog HDL warning at <location>: concatenation member label not yet supported; label ignored
ID:16848 Verilog HDL error at <location>: statement outside sequential area is not supported for synthesis
ID:16849 Verilog HDL error at <location>: hierarchical name <string> into function or task is not supported for synthesis
ID:16850 Verilog HDL error at <location>: formal port <string> expects a modport or interface instance actual
ID:16851 Verilog HDL error at <location>: formal port <string> of type <string> does not match with actual type <string>
ID:16852 Verilog HDL error at <location>: expression not allowed on <string> statement for <string>
ID:16853 Verilog HDL warning at <location>: <string> statement for <string> expects an expression
ID:16854 Verilog HDL error at <location>: expression cannot be negative
ID:16855 Verilog HDL error at <location>: invalid context for genvar <string>
ID:16856 Verilog HDL error at <location>: size of the corresponding unpacked dimensions do not match
ID:16857 Verilog HDL warning at <location>: ignoring parameter override for <string>, since it has already been set
ID:16858 Verilog HDL error at <location>: cycle range must be ascending
ID:16859 Verilog HDL error at <location>: clock for system call '<string>' missing in this context
ID:16860 Verilog HDL error at <location>: system call <string> not allowed in this dialect. Use System Verilog mode
ID:16861 Verilog HDL error at <location>: prefix of method <string> should be <string>
ID:16862 Verilog HDL warning at <location>: method <string> not supported for synthesis
ID:16863 Verilog HDL warning at <location>: return value of subprogram call <string> is ignored
ID:16864 Verilog HDL warning at <location>: <string> may be used uninitialized in static subprogram <string> and create unintended latch behavior
ID:16865 Verilog HDL error at <location>: hierarchical branch index should be a constant
ID:16866 Verilog HDL error at <location>: actual for type parameter <string> should be a data type
ID:16867 Verilog HDL info at <location>: <string> is declared here
ID:16868 Verilog HDL error at <location>: operator <string> is not allowed in <string>
ID:16869 Verilog HDL warning at <location>: invalid use of void function <string>
ID:16870 Verilog HDL error at <location>: invalid use of void function <string>
ID:16871 Verilog HDL error at <location>: invalid concurrent assertion in task/function
ID:16872 Verilog HDL error at <location>: automatic variable not allowed in <name>
ID:16873 Verilog HDL error at <location>: property instance <string> is not allowed in sequence expression
ID:16874 Verilog HDL error at <location>: concurrent assertion statement not allowed inside a looping statement
ID:16875 Verilog HDL error at <location>: assignment operator <string> not allowed outside procedural statements
ID:16876 Verilog HDL warning at <location>: variable <string> might have multiple concurrent drivers
ID:16877 Verilog HDL error at <location>: duplicate member values in enum definition for enum literal <string>
ID:16878 Verilog HDL error at <location>: event expression is not allowed here
ID:16879 Verilog HDL error at <location>: prefix of assignment pattern must be a data type
ID:16880 Verilog HDL error at <location>: instance '<string>' already declared in the bind target scope
ID:16881 Verilog HDL error at <location>: invalid circular dependency found through <string>
ID:16882 Verilog HDL error at <location>: non-net port <string> cannot be of mode <string>
ID:16883 Verilog HDL warning at <location>: this feature is not yet supported
ID:16884 Verilog HDL info at <location>: analyzing included file <string>
ID:16885 Verilog HDL warning at <location>: second declaration of <string> ignored
ID:16886 Verilog HDL error at <location>: <string> is not declared within package <string>
ID:16887 Verilog HDL error at <location>: <string> is not an instance of <string>
ID:16888 Verilog HDL warning at <location>: <string> is not yet supported for synthesis
ID:16889 Verilog HDL error at <location>: <string> is not yet supported for synthesis
ID:16890 Verilog HDL error at <location>: invalid left hand side of with clause
ID:16891 Verilog HDL warning at <location>: <string> in always_comb/always_latch is not allowed
ID:16892 Verilog HDL error at <location>: unpacked member <string> is not allowed in packed struct/union
ID:16893 Verilog HDL error at <location>: invalid select on unpacked structure/union type variable <string>
ID:16894 Verilog HDL warning at <location>: range expressions not allowed in hierarchical pathnames
ID:16895 Verilog HDL error at <location>: too many delays in gate instantiation
ID:16896 Verilog HDL warning at <location>: invalid context for real expression
ID:16897 Verilog HDL error at <location>: invalid context for real expression
ID:16898 Verilog HDL warning at <location>: self-reference to <string> ignored
ID:16899 Verilog HDL error at <location>: zero or negative value for size
ID:16900 Verilog HDL warning at <location>: enumeration range must be a non-negative integer value
ID:16901 Verilog HDL error at <location>: alias bit length <number> differs from actual bit length <number>
ID:16902 Verilog HDL error at <location>: only [expr1:expr2] syntax is allowed for packed ranges of types
ID:16903 Verilog HDL error at <location>: concatenation member label not allowed in multiple assignment pattern
ID:16904 Verilog HDL error at <location>: an enum variable may only be assigned to same enum typed variable or one of its values
ID:16905 Verilog HDL error at <location>: cannot assign <string> type to <string> type
ID:16906 Verilog HDL error at <location>: incompatible unpacked dimensions in assignment
ID:16907 Verilog HDL error at <location>: invalid concat label for <string>
ID:16908 Verilog HDL warning at <location>: too many indices into <string>
ID:16909 Verilog HDL error at <location>: invalid target for field:value initialization
ID:16910 Verilog HDL warning at <location>: ignoring -incdir options for this library declaration
ID:16911 Verilog HDL error at <location>: cannot format <string> <string> to standard absolute path form
ID:16912 Verilog HDL info at <location>: comparing file <string> to library pattern <string>: did not match
ID:16913 Verilog HDL info at <location>: comparing file <string> to library pattern <string>: matched library <string>
ID:16914 Verilog HDL error at <location>: file <string> matched multiple library patterns
ID:16915 Verilog HDL warning at <location>: polarity not allowed before <string> in edge-sensitive paths
ID:16916 Verilog HDL warning at <location>: operator overloading is not supported yet
ID:16917 Verilog HDL warning at <location>: range is not allowed in a prefix
ID:16918 Verilog HDL error at <location>: range is not allowed in a prefix
ID:16919 Verilog HDL error at <location>: multiple configuration default clauses are not allowed
ID:16920 Verilog HDL error at <location>: configuration with multiple designs cannot be instantiated
ID:16921 Verilog HDL error at <location>: configuration cell clause cannot contain a cell library and a liblist
ID:16922 Verilog HDL error at <location>: array element widths (<number>, <number>) don't match
ID:16923 Verilog HDL error at <location>: inconsistent dimension in declaration
ID:16924 Verilog HDL warning at <location>: redeclaration of ansi port <string> is not allowed
ID:16925 Verilog HDL error at <location>: <string> not allowed in this dialect. Use v2k mode
ID:16926 Verilog HDL error at <location>: incompatible complex type assignment
ID:16927 Verilog HDL warning at <location>: invalid format specifier <character> for <string>
ID:16928 Verilog HDL warning at <location>: missing or empty argument against format specification for <string>
ID:16929 Verilog HDL error at <location>: bit-select or part-select is not allowed in a <string> statement for non-net <string>
ID:16930 Verilog HDL error at <location>: assignment to const variable <string>
ID:16931 Verilog HDL error at <location>: <string> was previously declared as type
ID:16932 Verilog HDL error at <location>: declarations not allowed in unnamed block
ID:16933 Verilog HDL warning at <location>: cannot select <string> inside <string> due to dimension mismatch
ID:16934 Verilog HDL warning at <location>: invalid initial value of <string> port <string> for <string> <string> ignored
ID:16935 Verilog HDL warning at <location>: indexed range expression contains whitespace between <string> and :
ID:16936 Verilog HDL error at <location>: invalid context for <string>
ID:16937 Verilog HDL error at <location>: <string> not allowed in this dialect. Use system verilog mode
ID:16938 Verilog HDL error at <location>: number of loop variables in the FOREACH loop are more than the array dimensions
ID:16939 Verilog HDL warning at <location>: UDP primitive <string> does not have a table
ID:16940 Verilog HDL error at <location>: invalid use of `uselib directive : cannot mix lib with file|dir|libext
ID:16941 Verilog HDL error at <location>: <string> is visible via multiple package imports
ID:16942 Verilog HDL error at <location>: clocking block signal <string> can be driven only with a non-blocking assignment
ID:16943 Verilog HDL error at <location>: <string> was forward declared as <string> type not as <string>
ID:16944 Verilog HDL error at <location>: cannot have packed dimensions of type <string>
ID:16945 Verilog HDL error at <location>: forward typedef <string> was not defined in the scope where it is declared
ID:16946 Verilog HDL error at <location>: invalid reference to automatic variable <string>
ID:16947 Verilog HDL error at <location>: automatic variable <string> cannot be written in this context
ID:16948 Verilog HDL error at <location>: parameter connections cannot be mixed ordered and named
ID:16949 Verilog HDL warning at <location>: decimal constant <string> is too large, using <number> instead
ID:16950 Verilog HDL error at <location>: decimal constant <string> is too large, using <number> instead
ID:16951 Verilog HDL warning at <location>: multiple overrides for parameter <string>
ID:16952 Verilog HDL warning at <location>: <string> expects at least <number> arguments
ID:16953 Verilog HDL warning at <location>: <string> expects at most <number> arguments
ID:16954 Verilog HDL warning at <location>: notifier variable <string> must be a single bit register
ID:16955 Verilog HDL error at <location>: part-select <string> is not allowed in declaration
ID:16956 Verilog HDL warning at <location>: parallel path description may only have single input terminal descriptor and single output terminal descriptor
ID:16957 Verilog HDL error at <location>: an object or type with name <string> already exists in Covergroup scope
ID:16958 Verilog HDL warning at <location>: keyword '<string>' is not allowed here in this mode of verilog
ID:16959 Verilog HDL error at <location>: single value range is not allowed in this mode of verilog
ID:16960 Verilog HDL error at <location>: <string> in compilation scope are not allowed
ID:16961 Verilog HDL warning at <location>: invalid reference to chandle type
ID:16962 Verilog HDL error at <location>: invalid reference to chandle type
ID:16963 Verilog HDL warning at <location>: expression should be of type queue or element of queue
ID:16964 Verilog HDL error at <location>: invalid concatenation of real expression
ID:16965 Verilog HDL error at <location>: invalid concatenation of unpacked value
ID:16966 Verilog HDL error at <location>: assignment pattern is invalid for use with <string> port <string>
ID:16967 Verilog HDL error at <location>: invalid operand for operator <string>
ID:16968 Verilog HDL error at <location>: enum data type cannot be used with <string> operator
ID:16969 Verilog HDL error at <location>: invalid operator <string> in assignment to enum
ID:16970 Verilog HDL error at <location>: invalid cast operation
ID:16971 Verilog HDL error at <location>: new expression can only be assigned to a class/covergroup handle/dynamic array
ID:16972 Verilog HDL error at <location>: argument should be dynamic array
ID:16973 Verilog HDL error at <location>: invalid context for $
ID:16974 Verilog HDL error at <location>: use '{index : value} syntax in associative array literal
ID:16975 Verilog HDL error at <location>: number of elements does not match with the type
ID:16976 Verilog HDL error at <location>: invalid operand with streaming operator
ID:16977 Verilog HDL error at <location>: invalid stream expression
ID:16978 Verilog HDL error at <location>: invalid enumeration base type
ID:16979 Verilog HDL error at <location>: cannot mix event and non-event types in this operation
ID:16980 Verilog HDL error at <location>: cannot mix assoc and non-assoc arrays
ID:16981 Verilog HDL error at <location>: assigning a <string> type to a string requires a cast
ID:16982 Verilog HDL error at <location>: cannot assign a string to <string> type
ID:16983 Verilog HDL error at <location>: arrays have different elements
ID:16984 Verilog HDL error at <location>: associative array keys do not match
ID:16985 Verilog HDL error at <location>: invalid slicing of associative array
ID:16986 Verilog HDL error at <location>: invalid index for associative array
ID:16987 Verilog HDL error at <location>: invalid reference to <string>
ID:16988 Verilog HDL warning at <location>: invalid usage of signing with unpacked struct/union type
ID:16989 Verilog HDL error at <location>: invalid usage of signing with unpacked struct/union type
ID:16990 Verilog HDL warning at <location>: event expressions must result in a singular type
ID:16991 Verilog HDL error at <location>: only genvar can be assigned here
ID:16992 Verilog HDL error at <location>: invalid data type for udp register <string>
ID:16993 Verilog HDL error at <location>: invalid data type for udp port <string>
ID:16994 Verilog HDL error at <location>: <string> cannot be declared within UDP <string>
ID:16995 Verilog HDL error at <location>: first argument of <string> should be a string
ID:16996 Verilog HDL error at <location>: second argument of <string> should be a memory name
ID:16997 Verilog HDL error at <location>: port <string> is not connected to this instance
ID:16998 Verilog HDL error at <location>: actual and formal for a ref must be equivalent types
ID:16999 Verilog HDL error at <location>: field <string> of packed struct/union may not be declared rand or randc
ID:17000 WYSIWYG RAM primitive "<name>" must feed a single tri-state bus node
ID:17001 Latch "<name>" detected. Mismatch may occur during formal verification
ID:17002 Combinational loop detected. Provide cut point information to the formal verification tool. Insert cut buffer "<name>"
ID:17003 WYSIWYG I/Os found with illegal padio connections
ID:17004 WYSIWYG primitive "<name>" padio port connected with atom "<name>" must connect to only a single top-level pin of the same type, but feeds other logic
ID:17005 WYSIWYG primitive "<name>" padio port is connected illegally
ID:17006 Some WYSIWYG primitives POWER_UP_HIGH states changed
ID:17007 WYSIWYG primitive "<WYSIWYG name>" will now power up <high or low>
ID:17008 WYSIWYG I/O operation modes do not match their padio pin's type
ID:17009 WYSIWYG I/O "<name>" operation mode is <type>, which does not match padio pin "<name>" type of <type>
ID:17010 WYSIWYG ASMI primitives converted to equivalent logic
ID:17011 WYSIWYG SPI primitive "<name>" converted to equivalent logic
ID:17012 WYSIWYG I/O primitives converted to equivalent logic
ID:17013 WYSIWYG I/O primitive "<name>" converted to equivalent logic
ID:17014 WYSIWYG LCELL primitives have synchronous control signals that are not part of a carry chain
ID:17015 WYSIWYG LCELL primitive "<name>" has synchronous control signals that are not part of a carry chain
ID:17016 Found the following redundant logic cells in design
ID:17017 Removed the following redundant logic cells
ID:17018 Parallel expander chain length <number> exceeds limit of current device. Change length to <number>
ID:17019 Ignored Logic Cell Insertion logic option on node "<name>" -- illegal value specified for number of logic cells to insert
ID:17020 Inserted <number> logic cells after node "<name>"
ID:17021 Inserted <number> logic cells between source node "<name>" and destination node "<name>"
ID:17022 Ignored Logic Cell Insertion logic option between "<name>" and "<name>" -- Logic Cell Insertion can be assigned only between data signals that do not have a global signal assignment
ID:17023 Ignored Logic Cell Insertion logic option between "<name>" and "<name>" -- No direct path could be found between the specified nodes
ID:17024 Ignored Logic Cell Insertion logic option on "<name>" -- the specified node either has a global assignment, or it does not drive any data signals
ID:17025 Ignored Logic Cell Insertion logic option on "<name>" -- Logic Cell Insertion cannot be performed on PADIO ports
ID:17027 Synchronous clear or synchronous set on input registers of I/O primitive "<name>" not supported for current AUTO device or for a WYSIWYG I/O primitive in DDIO mode
ID:17029 Inserted <number> logic cells for Maximum Fan-Out assignment on "<name>"
ID:17030 Ignored Maximum Fan-Out assignment
ID:17031 Ignored Maximum Fan-Out logic option for node "<name>"
ID:17033 WYSIWYG I/O primitive "<name>" has missing or unconnected padio input port
ID:17034 WYSIWYG I/O primitive "<name>" has missing or unconnected data_in input port
ID:17036 Removed <number> MSB VCC or GND address nodes from RAM block "<name>"
ID:17037 Illegal configuration of I/O primitive <name>: port "<name>" should be directly connected to a single <name> pin.
ID:17038 I/O primitive <name> fed by PADIO port of a WYSIWYG pin
ID:17039 I/O primitive <name> feeds PADIO port of a WYSIWYG pin
ID:17040 Atom <name>'s Power-Up HIGH assignment is not honored
ID:17041 Selected device does not support Power-Up Level option
ID:17042 Verilog HDL error at <location>: invalid data type for random variable <string>
ID:17043 Gate-level register retiming is skipped because Synthesis Effort is set to Fast.
ID:17044 Illegal connection on I/O input buffer primitive <name>. Source I/O pin <name> drives out to destinations other than the specified I/O input buffer primitive. Modify your design so the specified source I/O pin drives only the specified I/O input buffer primitive.
ID:17045 Input port <name> of I/O input buffer primitive <name> is not connected. It must be driven by a top-level pin.
ID:17046 Illegal connection found on I/O output buffer primitive <name> to <name>. The IO output buffer should only drive out to a top-level pin.
ID:17047 WYSIWYG DLL primitive <name> converted to equivalent logic
ID:17048 Logic cell "<name>"
ID:17049 <number> registers lost all their fanouts during netlist optimizations.
ID:17050 Register "<name>" lost all its fanouts during netlist optimizations.
ID:17051 WYSIWYG Clock Delay Control primitive <name> converted to a wire
ID:17052 List truncated at <number> items
ID:17053 Cannot translate WYSIWYG "<name>" to family <name> since its function is not compatible with the targeted family
ID:17054 WYSIWYG oscillator primitives converted to equivalent logic
ID:17055 WYSIWYG oscillator primitive "<name>" converted to equivalent logic
ID:17056 WYSIWYG JTAG primitives converted to equivalent logic
ID:17057 WYSIWYG JTAG primitive "<name>" converted to equivalent logic
ID:17058 WYSIWYG CRC block primitives converted to equivalent logic
ID:17059 WYSIWYG CRC block primitive "<name>" converted to equivalent logic
ID:17060 WYSIWYG APF CONTROLLER primitives converted to equivalent logic
ID:17061 WYSIWYG APF CONTROLLER primitive "<name>" converted to equivalent logic
ID:17062 WYSIWYG APF CONTROLLER primitive "<name>" cannot be converted to equivalent logic because its port "<name>" is connected
ID:17063 WYSIWYG remote update block primitives converted to equivalent logic
ID:17064 WYSIWYG remote update block primitive "<name>" converted to equivalent logic
ID:17065 Synthesis swept away <number> nodes. For details of what was eliminated, see the Optimization Results || Nodes Synthesized Away report panel for Partition: "<name>".
ID:17066 Verilog HDL warning at <location>: invalid reference to event type
ID:17067 Verilog HDL error at <location>: invalid reference to event type
ID:17068 Verilog HDL error at <location>: invalid argument of type <string> in <string>(), expected <string>
ID:17069 Verilog HDL error at <location>: invalid argument of type <string> in <string>(), expected <string>
ID:17070 Verilog HDL error at <location>: cyclic reference to SVA <string> <string>
ID:17071 Verilog HDL error at <location>: aliasing can be done only on net types
ID:17072 Verilog HDL error at <location>: nets connected in alias statement must be type compatible
ID:17073 Verilog HDL error at <location>: generate loop index <string> is not defined as a genvar
ID:17074 Verilog HDL warning at <location>: assignment under multiple single edges is not supported for synthesis
ID:17075 Verilog HDL error at <location>: width does not match, stream larger than <string>
ID:17076 Verilog HDL warning at <location>: no loop index variable found in foreach statement
ID:17077 Verilog HDL error at <location>: foreach statement on associative/dynamic array is not supported
ID:17078 Verilog HDL warning at <location>: unknown version specifier string <string>, `begin_keywords ignored
ID:17079 Verilog HDL warning at <location>: `end_keywords without `begin_keywords
ID:17080 Verilog HDL warning at <location>: unmatched `begin_keywords directive in compilation unit
ID:17081 Verilog HDL error at <location>: <string> is not a valid constant function call
ID:17082 Verilog HDL error at <location>: global or hierarchical references "<name>" may not be used in constant function "<name>"
ID:17083 Verilog HDL error at <location>: elements of <string> cannot be mixed ordered and named
ID:17084 Verilog HDL warning at <location>: more than one default value found in literal
ID:17085 Verilog HDL error at <location>: some element(s) in <string> is missing
ID:17086 Verilog HDL error at <location>: expression has <number> elements; expected <number>
ID:17087 Verilog HDL error at <location>: out of range index label for array literal
ID:17088 Verilog HDL warning at <location>: assignment pattern key <string> is already covered
ID:17089 Verilog HDL warning at <location>: module <string> in library <string> is not yet analyzed
ID:17090 Verilog HDL error at <location>: The library <string> was not found
ID:17091 Verilog HDL error at <location>: No library search path could be found. Please set a search path to where module can be saved
ID:17092 Verilog HDL error at <location>: Save failed due to mkdir failure
ID:17093 Verilog HDL error at <location>: The module <string> was not found in library <string>
ID:17094 Verilog HDL error at <location>: <string> does not contain a known Verilog parse-tree format
ID:17095 Verilog HDL error at <location>: <string> has persistence version number <string>, which is outside the range 0x0ab00029 to <string> that this executable can restore
ID:17096 Verilog HDL warning at <location>: <string> was previously created using a PSL-enabled Verilog analyzer, since the current Verilog analyzer is not PSL-enabled, there is a high probability that a restore error will occur due to unknown PSL constructs
ID:17097 Verilog HDL warning at <location>: <string> was previously created using a AMS-enabled Verilog analyzer, since the current Verilog analyzer is not AMS-enabled, there is a high probability that a restore error will occur due to unknown AMS constructs
ID:17098 Verilog HDL warning at <location>: <string> was previously created using a System Verilog-enabled Verilog analyzer, since the current Verilog analyzer is not System Verilog-enabled, there is a high probability that a restore error will occur due to unknown System Verilog constructs
ID:17099 Verilog HDL error at <location>: <string>.<string> failed to restore
ID:17100 Verilog HDL error at <location>: Verilog library search path not set; cannot restore
ID:17101 Verilog HDL error at <location>: <string> does not contain a known VERI parse-tree format
ID:17102 Verilog HDL error at <location>: The path "<string>" does not exist
ID:17103 Verilog HDL info at <location>: The default veri library search path is now "<string>"
ID:17104 Verilog HDL info at <location>: The veri library search path for library "<string>" is now "<string>"
ID:17105 Verilog HDL error at <location>: This parse-tree is too large to be saved
ID:17106 Verilog HDL error at <location>: A Verilog parse-tree node is trying to be created from a SaveRestore object that is in save mode!
ID:17107 Verilog HDL error at <location>: Error from RegisterDependencies
ID:17108 Verilog HDL error at <location>: Registering Dependencies Error: <string>
ID:17109 Verilog HDL error at <location>: Registering Dependencies Error: The <string> '<string>' could not be found during restore
ID:17110 Verilog HDL error at <location>: <string> needs to be re-saved since <string>.<string> changed
ID:17111 Verilog HDL error at <location>: Verilog reader: User Interrupt. Cleaning up....
ID:17112 Verilog HDL warning at <location>: cannot open verilog file <string>
ID:17113 Verilog HDL error at <location>: cannot open verilog file <string>
ID:17114 Verilog HDL warning at <location>: library '<string>' is empty
ID:17115 Verilog HDL info at <location>: first instantiation was done here
ID:17116 Verilog HDL error at <location>: invalid net data type
ID:17117 Verilog HDL error at <location>: net data types must be 4 state
ID:17118 Verilog HDL error at <location>: <string> net arrays are not allowed
ID:17119 Verilog HDL error at <location>: invalid index expression
ID:17120 Verilog HDL error at <location>: return type of extern method <string> does not match prototype
ID:17121 Verilog HDL warning at <location>: formal name of extern method <string> does not match prototype
ID:17122 Verilog HDL error at <location>: formal name of extern method <string> does not match prototype
ID:17123 Verilog HDL error at <location>: formal type of extern method <string> does not match prototype
ID:17124 Verilog HDL error at <location>: formal count of extern method <string> does not match prototype
ID:17125 Verilog HDL error at <location>: cannot select inside <string> using hierarchical reference
ID:17126 Verilog HDL error at <location>: class <string> does not have a parameter named <string>
ID:17127 Verilog HDL error at <location>: concurrent assertion after timimg control is not allowed
ID:17128 Verilog HDL error at <location>: invalid concurrent assertion in action block
ID:17129 Verilog HDL error at <location>: local variable <string> referenced in expression where it does not flow
ID:17130 Verilog HDL error at <location>: invalid reference to <string> <string>
ID:17131 Verilog HDL error at <location>: method <string> is not allowed in disable iff condition
ID:17132 Verilog HDL error at <location>: explicit clocking event must be specified for <string> in disable iff condition
ID:17133 Verilog HDL error at <location>: invalid context for disable iff
ID:17134 Verilog HDL error at <location>: invalid function call with <string> argument in assertion expression
ID:17135 Verilog HDL error at <location>: local variable <string> can be passed only as entire actual argument to sequence on which ended or triggered is applied
ID:17136 Verilog HDL error at <location>: hierarchical access to local variable <string> is invalid
ID:17137 Verilog HDL error at <location>: local variable passed to formal <string> of sequence <string> to which ended or triggered is applied. The local variable does not flow out of the sequence
ID:17138 Verilog HDL error at <location>: not operator cannot be applied to recursive property
ID:17139 Verilog HDL error at <location>: static methods cannot be virtual
ID:17140 Verilog HDL error at <location>: invalid reference to non-static <string> from static function
ID:17141 Verilog HDL error at <location>: instance constant <string> cannot be declared static
ID:17142 Verilog HDL error at <location>: access to <string> member <string> from outside a class context is invalid
ID:17143 Verilog HDL error at <location>: access to <string> member <string> from <string> class context is invalid
ID:17144 Verilog HDL warning at <location>: invalid edge on named event
ID:17145 Verilog HDL warning at <location>: <string> <string> having interface port(s) (<string>) cannot be elaborated by itself
ID:17146 Verilog HDL error at <location>: <string> is an unknown type
ID:17147 Verilog HDL error at <location>: elements must both be signed or both be unsigned
ID:17148 Verilog HDL error at <location>: elements must both be 2-state or both be 4-state
ID:17149 Verilog HDL error at <location>: statement label and block identifier are not allowed together
ID:17150 Verilog HDL warning at <location>: <string> in final block is invalid
ID:17151 Verilog HDL warning at <location>: repeat expression should evaluate to non-negative value
ID:17152 Verilog HDL error at <location>: invalid actual arguments passed in recursive property <string>
ID:17153 Verilog HDL warning at <location>: <string> in always_comb/always_latch/always_ff is not allowed
ID:17154 Verilog HDL error at <location>: all identifiers need to have initial value
ID:17155 Verilog HDL warning at <location>: .* token can only appear at most once in port list
ID:17156 Verilog HDL warning at <location>: non-net variable cannot be connected to inout port <string>
ID:17157 Verilog HDL error at <location>: non-net variable cannot be connected to inout port <string>
ID:17158 Verilog HDL error at <location>: virtual interface <string> cannot be used as port
ID:17159 Verilog HDL warning at <location>: unique if/case has matching case items
ID:17160 Verilog HDL error at <location>: <string> statement not allowed within fork..join
ID:17161 Verilog HDL error at <location>: invalid SVA sequence/property expression
ID:17162 Verilog HDL error at <location>: the call to super.new must be the first statement in the constructor
ID:17163 Verilog HDL warning at <location>: object handle as arguments to <string> not valid for synthesis
ID:17164 Verilog HDL warning at <location>: multiple definitions of new in class <string>, taking the first one
ID:17165 Verilog HDL warning at <location>: class assignment is not synthesizable
ID:17166 Verilog HDL warning at <location>: expression not valid for synthesis
ID:17167 Verilog HDL error at <location>: system functions/tasks "<name>" may not be used in constant function "<name>"
ID:17168 Verilog HDL error at <location>: invalid reference to <string> from static function/task
ID:17169 Verilog HDL error at <location>: invalid reference to non-static id <string> from class scope
ID:17170 Verilog HDL error at <location>: step cannot be used in <string>
ID:17171 Verilog HDL warning at <location>: expression with variable or undeterminable width as argument to $bits
ID:17172 Verilog HDL warning at <location>: z value in udp table entry is invalid and will be treated as x
ID:17173 Verilog HDL error at <location>: ref type port <string> cannot be left unconnected
ID:17174 Verilog HDL error at <location>: left hand side of inside operator is not singular expression
ID:17175 Verilog HDL error at <location>: number of ticks for $past must be 1 or greater
ID:17176 Verilog HDL error at <location>: second argument of $<string> must be a memory
ID:17177 Verilog HDL error at <location>: positional arguments must occur before named arguments
ID:17178 Verilog HDL error at <location>: invalid output symbol '<character>' for combinational udp
ID:17179 Verilog HDL error at <location>: invalid current state symbol '<character>' for sequential udp
ID:17180 Verilog HDL error at <location>: invalid next state symbol '<character>' for sequential udp
ID:17181 Verilog HDL error at <location>: combinational udp port <string> cannot be reg
ID:17182 Verilog HDL error at <location>: <string> <string> in subclass cannot override <string> in superclass
ID:17183 Verilog HDL error at <location>: return type of <string> in subclass does not match with return type in superclass
ID:17184 Verilog HDL error at <location>: port count <number> of <string> in subclass does not match with port count <number> in superclass
ID:17185 Verilog HDL error at <location>: type of argument <string> of virtual method <string> does not match with type of argument in superclass
ID:17186 Verilog HDL error at <location>: replacing builtin package '<string>' violates IEEE 1800 LRM
ID:17187 Verilog HDL error at <location>: cannot have multiple initializations in udp
ID:17188 Verilog HDL error at <location>: packed dimension must specify a range
ID:17189 Verilog HDL error at <location>: task attached to the sequence cannot have out and inout formal arguments
ID:17190 Verilog HDL error at <location>: invalid input symbol '<character>' for udp
ID:17191 Verilog HDL error at <location>: cannot set both signing and void type on function decl
ID:17192 Verilog HDL error at <location>: sequential udp output port <string> must be reg
ID:17193 Verilog HDL warning at <location>: cannot bind module <string>, mixed language library vl not compiled
ID:17194 Verilog HDL warning at <location>: binary dump database must be encrypted to secure `protected RTL
ID:17195 Verilog HDL warning at <location>: non-module variable <string> cannot be initialized at declaration
ID:17196 Verilog HDL error at <location>: invalid declaration of built-in method <string>
ID:17197 Verilog HDL error at <location>: cannot re-specify direction for signal <string> to <string> because it was specified as input
ID:17198 Verilog HDL error at <location>: method new cannot have return type
ID:17199 Verilog HDL error at <location>: invalid use of virtual keyword for built-in method <string>
ID:17200 Verilog HDL warning at <location>: name of <name> declaration in <name> definition does not match that in extern <name>
ID:17201 Verilog HDL warning at <location>: port <string> should exactly match its corresponding port in extern module <text>
ID:17202 Verilog HDL error at <location>: actual <string> definition does not have port <string>
ID:17203 Verilog HDL error at <location>: invalid actual value for ref port <string> for <string>
ID:17204 Verilog HDL error at <location>: combinational udp cannot have initial statement
ID:17205 Verilog HDL error at <location>: identifier <string> is not in udp port list
ID:17206 Verilog HDL warning at <location>: direction of port <string> does not match that in extern module <text> declaration
ID:17207 Verilog HDL warning at <location>: scalared or vectored keyword can be used with vectored data types
ID:17208 Verilog HDL error at <location>: a void type may only be used in a tagged union
ID:17209 Verilog HDL warning at <location>: expected a system function, not system task $<string>
ID:17210 Verilog HDL error at <location>: only one event control is allowed in an always_ff block
ID:17211 Verilog HDL error at <location>: an always_ff block must have one and only one event control
ID:17212 Verilog HDL error at <location>: static qualifier for constraint block <string> does not match prototype
ID:17213 Verilog HDL error at <location>: weight in randcase is negative
ID:17214 Verilog HDL error at <location>: invalid <name> expression for coverpoint expression
ID:17215 Verilog HDL warning at <location>: method never defined for <string> <string>
ID:17216 Verilog HDL warning at <location>: port <string> must not be declared to be an array
ID:17217 Verilog HDL error at <location>: enum member <string> has value that is outside the representable range of the enum
ID:17218 Verilog HDL error at <location>: a distribution expression in constraint must contain at least one random variable
ID:17219 Verilog HDL error at <location>: randc variables cannot be used in distribution and solve-before
ID:17220 Verilog HDL error at <location>: non rand variable <string> cannot be used in solve before
ID:17221 Verilog HDL error at <location>: invalid void cast of task enable <string>
ID:17222 Verilog HDL warning at <location>: dynamic variables shall not be written with non-blocking assignments
ID:17223 Verilog HDL error at <location>: first argument level of system task <string> must be a positive integer
ID:17224 Verilog HDL warning at <location>: genvar <string> should be declared within module where it is used
ID:17225 Verilog HDL error at <location>: cannot access <string> member <string> of class <string> in scope of <string>
ID:17226 Verilog HDL error at <location>: null as source expression is not allowed here
ID:17227 Verilog HDL error at <location>: default clocking specified multiple times
ID:17228 Verilog HDL info at <location>: another default clocking is specified here
ID:17229 Verilog HDL error at <location>: unpacked value/target cannot be used in assignment
ID:17230 Verilog HDL error at <location>: prefix of randomize is not a class id
ID:17231 Verilog HDL error at <location>: member <string> of unpacked structure/union may not be declared rand or randc
ID:17232 Verilog HDL error at <location>: variable <string> is written by both continuous and procedural assignments
ID:17233 Verilog HDL error at <location>: invalid argument to dumpvars
ID:17234 Verilog HDL error at <location>: prefix <string> of constraint_mode is not the object handle containing constraint block
ID:17235 Verilog HDL error at <location>: aliasing an individual signal <string> to itself is not allowed
ID:17236 Verilog HDL error at <location>: multiple statement function/task without begin/end not supported in this mode of Verilog
ID:17237 Verilog HDL error at <location>: incomplete structure literal, no value is specified for field <string>
ID:17238 Verilog HDL error at <location>: reference to type <string> through instance <string> is not allowed here
ID:17239 Verilog HDL error at <location>: prefix <string> of rand_mode is not a object handle or a variable of type rand or randc
ID:17240 Verilog HDL error at <location>: type reference expression may not be hierarchical name or elements of dynamic type
ID:17241 Verilog HDL error at <location>: interface type objects cannot be declared within class
ID:17242 Verilog HDL error at <location>: unexpected <string>
ID:17243 Verilog HDL error at <location>: new timescale value (<string>) conflicts with an existing value
ID:17244 Verilog HDL error at <location>: error in timescale or timeprecision statement. <timeprecision> must be at least as precise as <timeunit>
ID:17245 Verilog HDL error at <location>: <string> literal not a power of 10
ID:17246 Verilog HDL error at <location>: expected simple identifier as loop variable
ID:17247 Verilog HDL warning at <location>: cast without ' violates IEEE 1800 syntax
ID:17248 Verilog HDL warning at <location>: edge path description violates IEEE 1800 syntax
ID:17249 Verilog HDL warning at <location>: gate instantiation in root scope violates IEEE 1800 syntax
ID:17250 Verilog HDL warning at <location>: package import in class violates IEEE 1800 syntax
ID:17251 Verilog HDL warning at <location>: hierarchical name in identifier list violates IEEE 1800 syntax
ID:17252 Verilog HDL warning at <location>: enum <enum_type> without type violates IEEE 1800 syntax
ID:17253 Verilog HDL warning at <location>: empty loop variable assignment statement violates IEEE 1800 syntax
ID:17254 Verilog HDL error at <location>: <string> is not a valid package or class type prefix for '::'
ID:17255 Verilog HDL error at <location>: primitive <string> connection must be a scalar var or net
ID:17256 Verilog HDL warning at <location>: posedge or negedge on real is invalid
ID:17257 Verilog HDL warning at <location>: multiple packed dimensions are not allowed in this mode of verilog
ID:17258 Verilog HDL error at <location>: module instantiation of <string> is not allowed in interface <string>
ID:17259 Verilog HDL warning at <location>: solve before expression in constraint set violates IEEE 1800 syntax
ID:17260 Verilog HDL error at <location>: prefix of array method <string> should not be <string>
ID:17261 Verilog HDL error at <location>: multiple definitions of <string>
ID:17262 Verilog HDL warning at <location>: <string> is not supported for synthesis
ID:17263 Verilog HDL error at <location>: <string> is not supported for synthesis
ID:17265 Verilog HDL error at <location>: poorly formed formal for macro definition <string>
ID:17266 Verilog HDL error at <location>: .* in port not allowed without declaration of extern <string>
ID:17267 Verilog HDL error at <location>: <string> expressions not allowed in argument of <string> randomize call
ID:17268 Verilog HDL warning at <location>: assert/assume/cover property statement in root scope violates IEEE 1800 syntax
ID:17269 Verilog HDL error at <location>: clocked expression not valid in function/task argument
ID:17270 Verilog HDL warning at <location>: clocked expression not valid in property/sequence argument, violates IEEE 1800 syntax
ID:17271 Verilog HDL warning at <location>: modport declaration id without direction not allowed, violates IEEE 1800 syntax
ID:17272 Verilog HDL warning at <location>: open value range with both bounds as '$' violates IEEE 1800 syntax
ID:17273 Verilog HDL warning at <location>: argument <number> of task <string> is implicitly defined, violates IEEE 1800 syntax
ID:17274 Verilog HDL warning at <location>: missing '{', violates IEEE 1800 syntax
ID:17275 Verilog HDL warning at <location>: forward declaration of covergroup violates IEEE 1800 syntax
ID:17276 Verilog HDL warning at <location>: alias declaration in program violates IEEE 1800 syntax
ID:17277 Verilog HDL warning at <location>: parameter declaration inside specify block violates IEEE 1800 syntax
ID:17278 Verilog HDL warning at <location>: using <string>.<string> in modport violates IEEE 1800 syntax
ID:17279 Verilog HDL error at <location>: <string> must be defined as a clocking id
ID:17280 Verilog HDL error at <location>: modport port direction mismatch
ID:17281 Verilog HDL warning at <location>: unexpected <'>, violates IEEE 1800 syntax
ID:17282 Verilog HDL warning at <location>: unexpected default, violates IEEE 1800 syntax
ID:17283 Verilog HDL warning at <location>: case statement with no case item violates IEEE 1800 syntax
ID:17284 Verilog HDL warning at <location>: unexpected <string>, violates IEEE 1800 syntax
ID:17286 Verilog HDL warning at <location>: local qualifier before constraint declaration violates IEEE 1800 syntax
ID:17287 Verilog HDL warning at <location>: solve-before in foreach violates IEEE 1800 syntax
ID:17288 Verilog HDL warning at <location>: struct/union/enum as slice size in streaming concatenation violates IEEE 1800 syntax
ID:17289 Verilog HDL warning at <location>: life times of extern declaration and prototypes do not match
ID:17290 Verilog HDL warning at <location>: invalid call to <string> in constraint block
ID:17291 Verilog HDL error at <location>: only automatic functions allowed in constraint block
ID:17292 Verilog HDL error at <location>: only input and const ref ports allowed in function called from constraint block
ID:17293 Verilog HDL error at <location>: event type variable <string> not allowed here
ID:17294 Verilog HDL error at <location>: new expression can only be assigned to a class/covergroup
ID:17295 Verilog HDL warning at <location>: unexpected final, violates IEEE 1800 syntax
ID:17296 Verilog HDL warning at <location>: system function call as initial value of type parameter violates IEEE 1800 syntax
ID:17297 Verilog HDL warning at <location>: bracketed constraint block violates IEEE 1800 syntax
ID:17298 Verilog HDL warning at <location>: dpi task import property 'pure' violates IEEE 1800 syntax
ID:17299 Verilog HDL warning at <location>: loop statement with empty body is not permitted in this mode of verilog
ID:17300 Verilog HDL warning at <location>: <string> expects <number> arguments, violates IEEE 1800 syntax
ID:17301 Verilog HDL warning at <location>: extern function declaration <string> violates IEEE 1800 syntax
ID:17302 Verilog HDL warning at <location>: wildcard in cross coverage violates IEEE 1800 syntax
ID:17303 Verilog HDL error at <location>: non integral type variables are not allowed in constraint declaration
ID:17304 Verilog HDL info at <location>: `begin_keywords used to upgrade the language mode
ID:17305 Verilog HDL error at <location>: `begin_keywords directives cannot be specified inside a design unit
ID:17306 Verilog HDL error at <location>: empty parameter not allowed in macro definition
ID:17307 Verilog HDL warning at <location>: encountered duplicate formal name <string>, actual value <string> will be ignored
ID:17308 Verilog HDL error at <location>: invalid multiconcat expression in target
ID:17309 Verilog HDL warning at <location>: specparam <string> not allowed here
ID:17310 Verilog HDL warning at <location>: loop variable declaration is not allowed in this mode of verilog
ID:17311 Verilog HDL error at <location>: out-of-block <string> declaration <string> must be in the same scope as the class <string>
ID:17312 Verilog HDL error at <location>: positional notation should not be mixed with other type of notation
ID:17313 Verilog HDL warning at <location>: <string> delay form with this gate violates IEEE 1364 LRM
ID:17314 Verilog HDL warning at <location>: empty concatenation not allowed here
ID:17315 Verilog HDL error at <location>: invalid expression in type operator
ID:17316 Verilog HDL error at <location>: invalid prefix for <string>
ID:17317 Verilog HDL error at <location>: size casting a real expression violates IEEE 1800 LRM
ID:17318 Verilog HDL warning at <location>: solve id-list before id-list hard violates IEEE 1800 syntax
ID:17319 Verilog HDL error at <location>: strength without assignment is not allowed in net declaration
ID:17320 Verilog HDL error at <location>: invalid assignment of structure literals to union
ID:17321 Verilog HDL error at <location>: both strengths required for <string>
ID:17322 Verilog HDL warning at <location>: unknown pragma '<string>' value '<string>' ignored
ID:17323 Verilog HDL warning at <location>: assignment sub expression is allowed only in System Verilog mode
ID:17324 Verilog HDL error at <location>: invalid initialization in declaration. Initialization in declaration is only supported in SystemVerilog 2009 and newer
ID:17325 Verilog HDL warning at <location>: unexpected with default, violates IEEE 1800 syntax
ID:17326 Verilog HDL warning at <location>: elaboration system task <string> violates IEEE 1800 (2005) syntax
ID:17327 Verilog HDL warning at <location>: min-typ-max expression in argument violates IEEE 1800 syntax
ID:17328 Verilog HDL warning at <location>: macro name <string> starting with a number violates Verilog syntax
ID:17329 Verilog HDL warning at <location>: empty modport port declaration violates IEEE 1800 syntax
ID:17330 Verilog HDL error at <location>: packed union contains members of different size
ID:17331 Verilog HDL warning at <location>: <string> in enum literal range violates IEEE 1800 syntax
ID:17332 Verilog HDL error at <location>: the sva directive is not sensitive to clock
ID:17333 Verilog HDL warning at <location>: timeunit/precision declaration with a space before unit violates IEEE 1800 syntax
ID:17334 Verilog HDL warning at <location>: loop variable declaration without initialization violates IEEE 1800 syntax
ID:17335 Verilog HDL error at <location>: edge must be specified for the contextually inferred clock
ID:17336 Verilog HDL error at <location>: the clock flow cannot change in the RHS of <string> operator
ID:17337 Verilog HDL warning at <location>: type identifier <string> used in invalid context
ID:17338 Verilog HDL error at <location>: type identifier <string> used in invalid context
ID:17339 Verilog HDL warning at <location>: empty item in case item list violates IEEE 1364 syntax
ID:17340 Verilog HDL warning at <location>: white space between <string> and <string> violates IEEE 1800 syntax
ID:17341 Verilog HDL warning at <location>: udp table entry <string> conflicts with earlier entry
ID:17342 Verilog HDL warning at <location>: invalid edge specification <string> in udp
ID:17343 Verilog HDL error at <location>: direction is not allowed in formal argument of let
ID:17344 Verilog HDL error at <location>: instantiation is not allowed in sequential area except checker instantiation
ID:17345 Verilog HDL error at <location>: intra-assignment delay control is not allowed in an assignment to a clocking
ID:17347 Verilog HDL warning at <location>: invalid use of parameter <string> with unbounded value
ID:17348 Verilog HDL warning at <location>: invalid expression in system call <string>
ID:17349 Verilog HDL error at <location>: <string> needs at least <number> arguments
ID:17350 Verilog HDL warning at <location>: space between colon and equal in dist operator violates IEEE 1800 syntax
ID:17351 Verilog HDL error at <location>: strength is not allowed in <string> switch
ID:17352 Verilog HDL warning at <location>: only subroutine call can be used in deferred assertion
ID:17353 Verilog HDL warning at <location>: continuing <string> <string> declaration in modport violates IEEE 1800 syntax
ID:17354 Verilog HDL warning at <location>: only simple module name as bind target are supported for rtl synthesis
ID:17355 Verilog HDL error at <location>: incorrect use of macro <string>, argument was not closed
ID:17356 Verilog HDL warning at <location>: root scope declaration is not allowed in verilog 95/2K mode
ID:17357 Verilog HDL warning at <location>: extra braces around constraint expressions violates IEEE 1800 syntax
ID:17358 Verilog HDL error at <location>: parameter <string> has no actual or default value
ID:17359 Verilog HDL error at <location>: cycle delay in assignment only defined under default clock
ID:17360 Verilog HDL warning at <location>: system function call <string> with non-constant <string> argument is not synthesizable
ID:17361 Verilog HDL error at <location>: replication is not allowed in unpacked array concatenation
ID:17362 Verilog HDL error at <location>: wrong element type in unpacked array concatenation
ID:17363 Verilog HDL error at <location>: references to the <string> are not allowed in packages
ID:17364 Verilog HDL error at <location>: recursive `include via file <string>
ID:17365 Verilog HDL info at <location>: previous error may be due to too many nested include file
ID:17366 Verilog HDL warning at <location>: invalid blocking assignment of non-program variable <string>
ID:17367 Verilog HDL warning at <location>: invalid non-blocking assignment of program variable <string>
ID:17368 Verilog HDL error at <location>: automatic variable <string> is not allowed in procedural continuous assignments
ID:17369 Verilog HDL error at <location>: genvar <string> is already used in this scope
ID:17370 Verilog HDL error at <location>: invalid specify input/output terminal descriptor in PATHPULSE
ID:17371 Verilog HDL error at <location>: parameter <string> is already connected
ID:17372 Verilog HDL warning at <location>: invalid <string> port in function <string> used in procedural continuous assignment statement
ID:17373 Verilog HDL warning at <location>: invalid <string> port in function <string> used in event expression
ID:17374 Verilog HDL error at <location>: dynamic range is not allowed in this mode of verilog
ID:17375 Verilog HDL error at <location>: real type port is not allowed in this mode of verilog
ID:17376 Verilog HDL error at <location>: parameter initial value cannot be omitted in this mode of verilog
ID:17377 Verilog HDL warning at <location>: initial value of parameter <string> is omitted
ID:17378 Verilog HDL error at <location>: digits must follow decimal point in real <string>
ID:17379 Verilog HDL error at <location>: expression size is larger than 2**<number> bits
ID:17380 Verilog HDL error at <location>: modport item <string> must refer to an item in interface <string>
ID:17381 Verilog HDL error at <location>: type must be specified for local variable formal argument
ID:17382 Verilog HDL error at <location>: keyword local is missing for port item with direction
ID:17383 Verilog HDL error at <location>: default actual argument for inout/output port <string> is not allowed
ID:17384 Verilog HDL error at <location>: invalid type for local variable formal argument
ID:17385 Verilog HDL error at <location>: clocking event not allowed in clocking block
ID:17386 Verilog HDL error at <location>: checker instance is not allowed in fork-join block
ID:17387 Verilog HDL warning at <location>: checker cannot be elaborated by itself
ID:17388 Verilog HDL error at <location>: empty arguments are allowed only in system verilog
ID:17389 Verilog HDL error at <location>: unbounded range is not allowed with <string> operator
ID:17390 Verilog HDL error at <location>: error in protected region near <string>
ID:17391 Verilog HDL warning at <location>: <string> <string> is deprecated in this mode of verilog
ID:17392 Verilog HDL warning at <location>: unknown port direction <string> found for port <string>. Assume input
ID:17393 Verilog HDL warning at <location>: unknown signal type <string> found for added signal <string>. Assume wire
ID:17394 Verilog HDL error at <location>: cannot omit port identifier for this declarations
ID:17395 Verilog HDL warning at <location>: multiple dimension class instance not supported for synthesis
ID:17396 Verilog HDL warning at <location>: initial value not honored for array class instance
ID:17397 Verilog HDL warning at <location>: modport <string> contains interface method, using full interface
ID:17398 Verilog HDL error at <location>: the system function <string> not sensitive to clock
ID:17399 Verilog HDL warning at <location>: ignoring incorrect/unknown option: <string>
ID:17400 Verilog HDL error at <location>: system function call <string> inside abort function should have explicit clock
ID:17401 Verilog HDL warning at <location>: no clock inferred, multiple event control found
ID:17402 Verilog HDL warning at <location>: no clock inferred, delay control found
ID:17403 Verilog HDL warning at <location>: no clock inferred, event control id used in procedural code
ID:17404 Verilog HDL warning at <location>: no clock inferred, multiple inferred clock
ID:17405 Verilog HDL error at <location>: empty parameter assignment not allowed
ID:17406 Verilog HDL warning at <location>: possible infinite loop detected in implicit state machine conversion
ID:17407 Verilog HDL error at <location>: inside operator not allowed with casex or casez
ID:17408 Verilog HDL warning at <location>: ignoring non-constant initial value of static variable <string>
ID:17409 Verilog HDL error at <location>: forward typedef <string> is already fully defined
ID:17410 Verilog HDL error at <location>: use of <string> #(params) here violates IEEE 1800 syntax
ID:17411 Verilog HDL error at <location>: only trireg nets can have a charge strength specification
ID:17412 Verilog HDL warning at <location>: invalid size of integer constant literal
ID:17413 Verilog HDL warning at <location>: only one terminal allowed as the source or destination of parallel paths
ID:17414 Verilog HDL warning at <location>: <string> is not a predefined system timing check
ID:17415 Verilog HDL warning at <location>: fixed width part select is not allowed in verilog 95 mode
ID:17416 Verilog HDL error at <location>: invalid use of x or z character in decimal number
ID:17417 Verilog HDL error at <location>: multiple definitions of global clocking are not allowed
ID:17418 Verilog HDL error at <location>: global clocking referenced without declaration
ID:17419 Verilog HDL warning at <location>: <string> <string> having generic interface port(s) (<string>) cannot be elaborated by itself
ID:17420 Verilog HDL error at <location>: rand join production control must have at least two production items
ID:17421 Verilog HDL error at <location>: compilation unit has not been closed before this analyze call
ID:17422 Verilog HDL error at <location>: assignment to non clocking block signal/variable <string>, not allowed in cycle delay intra assignment
ID:17423 Verilog HDL error at <location>: use casting to use streaming concatenation with other operators
ID:17424 Verilog HDL warning at <location>: library <string> is not present
ID:17425 Verilog HDL error at <location>: bad operand to set membership operator
ID:17426 Verilog HDL warning at <location>: cannot find return_port_name <string> in module <string>, falling back to default evaluation
ID:17427 Verilog HDL warning at <location>: cannot map <string> having output port to module <string> in sequential area
ID:17428 Verilog HDL warning at <location>: cannot map return_port_name of a <string>, falling back to default evaluation
ID:17429 Verilog HDL error at <location>: incorrect number of dimensions in instantiation
ID:17430 Verilog HDL error at <location>: number of unpacked dimensions <number> does not match the number of dimensions <number> of VHDL unconstrained array
ID:17431 Verilog HDL error at <location>: invalid to define packed dimensions for vhdl unconstrained arrays
ID:17432 Verilog HDL info at <location>: ignore unsupported data type <string> during package conversion
ID:17433 Verilog HDL warning at <location>: type <string> is used before its declaration
ID:17434 Verilog HDL warning at <location>: invalid reference of <string> inside interface <string>
ID:17435 Verilog HDL warning at <location>: task or function <string> with ref arguments must be automatic
ID:17436 Verilog HDL error at <location>: dynamic range is not allowed in net declaration
ID:17437 Verilog HDL error at <location>: cannot instantiate object of virtual class <string>
ID:17438 Verilog HDL error at <location>: TBDM: cannot remove <string> having multiple declarations with multiple ids
ID:17439 Verilog HDL warning at <location>: converting <string> to <string>
ID:17440 Verilog HDL error at <location>: net type must be explicitly specified for '<string>' when default_nettype is none
ID:17441 Verilog HDL error at <location>: previous definition of <string> <string> is static elaborated, cannot overwrite
ID:17442 Verilog HDL error at <location>: no associated actual for formal <string>
ID:17443 Verilog HDL error at <location>: cannot create <string> due to mkdir failure
ID:17444 Verilog HDL error at <location>: invalid instantiation: <string> <string> cannot be instantiated in this way
ID:17445 Verilog HDL error at <location>: package export <string>::<string> failed, name not found
ID:17446 Verilog HDL error at <location>: package export <string>::<string> failed, name locally declared
ID:17447 Verilog HDL error at <location>: wait statement must be followed by event control statement
ID:17448 Verilog HDL error at <location>: invalid case item comparison of <string> type with <string> type
ID:17449 Verilog HDL warning at <location>: non-void function <string> called as a task without void casting
ID:17450 Verilog HDL error at <location>: all elements of structure are not type equivalent, cannot use multi assignment pattern
ID:17451 Verilog HDL error at <location>: function/task declaration in root scope violates verilog AMS syntax
ID:17452 Verilog HDL error at <location>: only named parameter assignment is allowed in use clause
ID:17453 Verilog HDL error at <location>: only local parameter declarations are allowed in configuration
ID:17454 Verilog HDL warning at <location>: module <string> does not have a parameter named <string> to override
ID:17455 Verilog HDL error at <location>: struct/union element <string> is already declared
ID:17456 Verilog HDL warning at <location>: unterminated string literal continues onto next line
ID:17457 Verilog HDL error at <location>: range must be bounded by constant expressions
ID:17458 Verilog HDL warning at <location>: <name> declaration is not allowed here in this mode of verilog
ID:17459 Verilog HDL warning at <location>: case <string>equality operator always evaluates to <string> due to comparison with x or z
ID:17460 Verilog HDL warning at <location>: overwriting previous value of parameter <string>
ID:17461 Verilog HDL error at <location>: multiple dimensions in <string> instantiation is not allowed in this mode of Verilog
ID:17462 Verilog HDL error at <location>: resolution function <string> must be automatic
ID:17463 Verilog HDL error at <location>: resolution function <string> must have single input argument
ID:17464 Verilog HDL error at <location>: argument <string> of resolution function <string> must be dynamic array
ID:17465 Verilog HDL error at <location>: argument <string> of resolution function <string> must be an input
ID:17466 Verilog HDL error at <location>: <string> is not a valid resolution function for type <string> : <string>
ID:17467 Verilog HDL info at <location>: previous declaration of <string> is from here
ID:17468 Verilog HDL error at <location>: method <string> is not allowed in argument of sampled value function
ID:17469 Verilog HDL error at <location>: use of local variable <string> in sampled value function is invalid
ID:17470 Verilog HDL error at <location>: modport port <string> does not support declared direction <string>
ID:17471 Verilog HDL error at <location>: clocking argument for <string> is not of type event control
ID:17472 Verilog HDL warning at <location>: invalid to use all zero replications in concat
ID:17473 Verilog HDL error at <location>: default value for <string> is not allowed in extern method body when not specified in class
ID:17474 Verilog HDL warning at <location>: mismatch in default argument value for <string>, <string> in prototype and <string> in extern method body
ID:17475 Verilog HDL error at <location>: <string> block cannot have a label both before and after the <string> keyword
ID:17476 Verilog HDL warning at <location>: configuration has multiple instance clause for same instance
ID:17477 Verilog HDL warning at <location>: instance clause specifying hierarchical path cannot refer inside another configuration
ID:17478 Verilog HDL error at <location>: Member field <string> of <string> cannot be initialized at declaration
ID:17479 Verilog HDL warning at <location>: empty statement in <string>
ID:17480 Verilog HDL error at <location>: bit stream casting is only allowed on same size data
ID:17481 Verilog HDL error at <location>: invalid rhs in generate loop initialization assignment
ID:17482 Verilog HDL error at <location>: invalid randomize method
ID:17483 Verilog HDL warning at <location>: unsatisfiable sequence in assertion
ID:17484 Verilog HDL warning at <location>: unique/priority if/case is not full
ID:17485 Verilog HDL warning at <location>: cannot find cell <string> in logical library <string>
ID:17486 Verilog HDL warning at <location>: cannot find cell <string> in liblist
ID:17487 Verilog HDL error at <location>: invalid use of genvar <string>
ID:17488 Verilog HDL error at <location>: parameter port list is not allowed with .* in port list
ID:17489 Verilog HDL error at <location>: incompatible assignment
ID:17490 Verilog HDL error at <location>: each member expression of assignment pattren should have a bitstream datatype
ID:17491 Verilog HDL error at <location>: checker formal argument '<string>' may not be of interface type
ID:17492 Verilog HDL error at <location>: generic interconnect may specify at most one delay value
ID:17493 Verilog HDL error at <location>: generic interconnect must not specify any drive strength
ID:17494 Verilog HDL error at <location>: generic interconnect must not specify any data type
ID:17495 Verilog HDL error at <location>: generic interconnect must not specify initial assignment expression
ID:17496 Verilog HDL warning at <location>: use of char as keyword violates IEEE 1800 syntax
ID:17497 Verilog HDL info at <location>: connection type is incompatible with formal type for port <string> in instance <string>
ID:17498 Verilog HDL warning at <location>: parameter '<string>' declared inside generate block shall be treated as localparam
ID:17499 Verilog HDL warning at <location>: empty range with constant bounds, low-bound and high-bound may be reversed
ID:17500 Verilog HDL warning at <location>: real data type is not a legal type of an associative array index
ID:17501 Verilog HDL warning at <location>: index <string> is out of range [<number>:<number>] for <string>
ID:17502 Verilog HDL error at <location>: <string> is not enabled in this product
ID:17503 Verilog HDL error at <location>: invalid nested interface class <string> within <string>
ID:17504 Verilog HDL error at <location>: invalid extends, class <string> may not extend an interface class
ID:17505 Verilog HDL error at <location>: only interface class can be referenced in <string> clause
ID:17506 Verilog HDL error at <location>: invalid use of new with interface/abstract class
ID:17507 Verilog HDL error at <location>: pure virtual method <string> can exist only in abstract class
ID:17508 Verilog HDL error at <location>: <string> <string> in subclass <string> cannot override <string> in superclass
ID:17509 Verilog HDL error at <location>: formal count of virtual method <string> does not match prototype
ID:17510 Verilog HDL error at <location>: type of argument <string> for virtual method <string> in subclass <string> does not match the type of argument in superclass
ID:17511 Verilog HDL error at <location>: class <string> must implement/redeclare <string> from interface/base classes
ID:17512 Verilog HDL error at <location>: the name <string> must be defined in <string> due to having conflicting visibility in multiple base classes
ID:17513 Verilog HDL error at <location>: call to rand_mode/constraint_mode on interface class handle is invalid
ID:17514 Verilog HDL error at <location>: elements must have same number of bits
ID:17515 Verilog HDL error at <location>: return type for virtual method <string> in class <string> is not type equivalent to the superclass method
ID:17516 Verilog HDL warning at <location>: argument name <string> for virtual method <string> in subclass <string> does not match the argument name <string> in superclass
ID:17517 Verilog HDL warning at <location>: DPI is deprecated in import/export declarations, use DPI-C instead
ID:17518 Verilog HDL error at <location>: invalid formal argument type for <string>
ID:17519 Verilog HDL error at <location>: invalid DPI function return value detected
ID:17520 Verilog HDL error at <location>: ref mode is not a legal mode in DPI argument
ID:17521 Verilog HDL warning at <location>: extra semicolon is not allowed here in this dialect. Use SystemVerilog mode
ID:17522 Verilog HDL error at <location>: width of actual <number> differs from expected width of formal <number> or <number> for port <string>
ID:17523 Verilog HDL warning at <location>: implication operator can be used only in constraint expression in SystemVerilog 1800-2005 dialect
ID:17524 Verilog HDL error at <location>: no top level module/unit found, elaboration aborted
ID:17525 Verilog HDL error at <location>: object <string> is not visible under prefix <string> via modport <string> of interface <string>
ID:17526 Verilog HDL warning at <location>: `include directive not isolated on its own line
ID:17527 Verilog HDL error at <location>: width of actual <number> differs from expected width of formal <number> or <number>
ID:17528 Verilog HDL warning at <location>: function <string> has no return value assignment
ID:17529 Verilog HDL warning at <location>: unknown system task <string> ignored for synthesis
ID:17530 Verilog HDL warning at <location>: defparam containing interface instance reference <string> is not supported for synthesis
ID:17531 Verilog HDL warning at <location>: instantiating empty extern <string> <string>
ID:17532 Verilog HDL info at <location>: use class scope resolution operator (::) instead of dot (.)
ID:17533 Verilog HDL info at <location>: <string> is not yet supported in implicit state machine conversion
ID:17534 Verilog HDL error at <location>: single value range is not allowed in packed dimension
ID:17535 Verilog HDL error at <location>: only predefined method sample can be overridden in covergroup
ID:17536 Verilog HDL error at <location>: arguments passed by reference cannot be used within fork-join_any or fork_join_none blocks
ID:17537 Verilog HDL info at <location>: expected type : <string>, observed type : <string>
ID:17538 Verilog HDL error at <location>: unexpected parameter values in module port declaration
ID:17539 Verilog HDL error at <location>: elements of dynamic variables may not be written with nonblocking, continuous or procedural continuous assignments
ID:17540 Verilog HDL error at <location>: elements of dynamic variables are only allowed in procedural blocks
ID:17541 Verilog HDL warning at <location>: the syntax for <string> has been changed from <string> to <string>
ID:17542 Verilog HDL error at <location>: associative/queue dimension is not allowed for parameters
ID:17543 Verilog HDL warning at <location>: constant expression cannot be used as event expression
ID:17544 Verilog HDL error at <location>: invalid target for assignment
ID:17545 Verilog HDL error at <location>: synthesis directive "<string>" is not supported
ID:17546 Verilog HDL error at <location>: synthesis directive "read_comments_as_HDL" is not supported
ID:17547 Verilog HDL error at <location>: cannot connect unsized constant <string> to a blackbox port
ID:17548 VHDL warning at <location>: magnitude comparator on user-encoded values can create simulation-synthesis differences
ID:17549 VHDL warning at <location>: character <string> is not in type <string>
ID:17550 VHDL warning at <location>: digit '<character>' is larger than base in <string>
ID:17551 VHDL info at <location>: netlist <string>(<string>) remains a blackbox, due to errors in its contents
ID:17552 VHDL warning at <location>: overwriting existing primary unit <string>
ID:17553 VHDL warning at <location>: overwriting existing secondary unit <string>
ID:17554 VHDL warning at <location>: possible infinite loop; process does not have a wait statement
ID:17555 VHDL info at <location>: re-analyze unit <string> since unit <string> is overwritten or removed
ID:17556 VHDL warning at <location>: subtype of alias <string> does not have the same bounds or direction as the target name
ID:17557 VHDL warning at <location>: <string> expects <number> arguments
ID:17558 VHDL info at <location>: another match is here
ID:17559 VHDL warning at <location>: unmatched <string> translate/synthesis off pragma found; matching pair with same keywords is required
ID:17560 VHDL info at <location>: going to verilog side to elaborate module <string>
ID:17561 VHDL info at <location>: back to vhdl to continue elaboration
ID:17562 VHDL warning at <location>: subprogram call <string> ignored for synthesis
ID:17563 VHDL warning at <location>: entity <string> does not have an architecture
ID:17564 VHDL warning at <location>: actual expression for generic <string> cannot reference a signal
ID:17565 VHDL warning at <location>: resolution function <string> without synthesis directive will use three-state wiring
ID:17566 VHDL error at <location>: subprogram <string> does not conform with its declaration
ID:17567 VHDL error at <location>: if-condition is an event, not an edge
ID:17568 VHDL warning at <location>: cannot access '<string>' from inside pure function '<string>'.
ID:17569 VHDL error at <location>: character with value 0x<number> is not a graphic literal character
ID:17570 VHDL error at <location>: range constraints cannot be applied to array types
ID:17571 VHDL error at <location>: construct '<string>' not allowed in VHDL'87; use VHDL'93 mode
ID:17572 VHDL error at <location>: elements of file type are not allowed in composite types
ID:17573 VHDL warning at <location>: argument to operator call <string> is ambiguous. Use qualified expression or switch to 87 mode
ID:17574 VHDL warning at <location>: design unit <string> contains unconstrained port(s)
ID:17575 VHDL error at <location>: <string> is not a valid operator symbol
ID:17576 VHDL error at <location>: port <string> is already associated in the primary binding
ID:17577 VHDL error at <location>: near <string> ; prefix should denote an array type
ID:17578 VHDL error at <location>: literal <string> exceeds maximum integer value
ID:17579 VHDL error at <location>: missing full type definition for <string>
ID:17580 VHDL error at <location>: wait statement not allowed inside a function
ID:17581 VHDL error at <location>: deferred constant <string> is allowed only in package declaration
ID:17582 VHDL error at <location>: operator <string> not defined on physical values
ID:17583 VHDL info at <location>: non-constant loop found; will execute up to <number> iterations
ID:17584 VHDL error at <location>: formal <string> of mode <string> must have an associated actual
ID:17585 VHDL error at <location>: case choice must be a locally static expression
ID:17586 VHDL error at <location>: in an array aggregate expression, non-locally static choice is allowed only if it is the only choice of the only association
ID:17587 VHDL error at <location>: parameter in attribute delayed must be globally static expression
ID:17588 VHDL error at <location>: range constraint in scalar type definition must be locally static
ID:17589 VHDL error at <location>: aggregate target in assignment must be all locally static names
ID:17590 VHDL error at <location>: expression has incompatible type
ID:17591 VHDL error at <location>: sensitivity list can have only static signal name
ID:17592 VHDL error at <location>: attribute <string> requires a static signal prefix
ID:17593 VHDL error at <location>: index/slice name with label prefix must have static index/slice
ID:17594 VHDL error at <location>: parameter value of attribute '<string> is out of range
ID:17595 VHDL error at <location>: <string> not allowed in entity statement part
ID:17596 VHDL error at <location>: attribute delayed may not be read from formal signal parameter <string>
ID:17597 VHDL error at <location>: cannot index the result of a type conversion
ID:17598 VHDL error at <location>: allocator subtype indication cannot be unconstrained array
ID:17599 VHDL error at <location>: partial formal element already associated
ID:17600 VHDL error at <location>: not all partial formals of <string> have actual
ID:17601 VHDL warning at <location>: function return type array bounds do not match function return value array bounds
ID:17602 VHDL error at <location>: function return type array bounds do not match function return value array bounds
ID:17603 VHDL error at <location>: designated type of access type cannot be file type
ID:17604 VHDL error at <location>: formal parameter of type file must be associated with a file object
ID:17605 VHDL warning at <location>: <string> statement choice <string> is outside the range of the select
ID:17606 VHDL error at <location>: cannot drive implicit signal guard
ID:17607 VHDL error at <location>: attribute <string> requires a constrained array prefix type
ID:17608 VHDL error at <location>: cannot assign null waveform to non-guarded signal
ID:17609 VHDL warning at <location>: extended identifier <string> contains non-graphic character 0x<number>
ID:17610 VHDL error at <location>: no index value can belong to null index range
ID:17611 VHDL error at <location>: designated type of file type cannot be file, access type, protected type or formal generic type
ID:17612 VHDL error at <location>: designated type of file type cannot be multidimensional array type
ID:17613 VHDL error at <location>: prefix of <string> in the use clause must be library or package identifier
ID:17614 VHDL error at <location>: attribute may not be of file or access type
ID:17615 VHDL error at <location>: base value <number> must be at least two and at most sixteen
ID:17616 VHDL error at <location>: cannot open file '<string>'
ID:17617 VHDL error at <location>: cannot read attribute <string> of mode linkage signal <string>
ID:17618 VHDL error at <location>: cannot use null waveform in concurrent signal assignment
ID:17619 VHDL error at <location>: attribute <string> may not be read from formal signal parameter <string>
ID:17620 VHDL error at <location>: invalid recursive instantiation of <string>(<string>)
ID:17621 VHDL error at <location>: type conversion (to <string>) cannot have <string> operand
ID:17622 VHDL error at <location>: types do not conform for deferred constant <string>
ID:17623 VHDL error at <location>: an alias object must be a static name
ID:17624 VHDL error at <location>: attribute <string> does not take a parameter when prefix is not an array type
ID:17625 VHDL error at <location>: attribute <string> requires a locally static parameter
ID:17626 VHDL error at <location>: the type of vhdl port is invalid for verilog connection
ID:17627 VHDL error at <location>: unit <string> not found in library <string>
ID:17628 VHDL warning at <location>: <string> was previously created using a PSL-enabled VHDL analyzer, since the current VHDL analyzer is not PSL-enabled, there is a high probability that a restore error will occur due to unknown PSL constructs
ID:17629 VHDL error at <location>: <string>.<string> failed to restore
ID:17630 VHDL error at <location>: <string> was created using a later vhdl_version_number, forward compatibility is not supported
ID:17631 VHDL error at <location>: The library <string> was not found
ID:17632 VHDL error at <location>: No VHDL library search path could be found. Please set a search path to where unit can be saved
ID:17633 VHDL error at <location>: Save failed due to mkdir failure
ID:17634 VHDL error at <location>: VHDL library search path not set; cannot restore
ID:17635 VHDL error at <location>: <string> does not contain a known VHDL parse-tree format
ID:17636 VHDL error at <location>: <string> was created using code corresponding to a vhdl_version_number of <string>, backward compatibility of versions before 0x0ab00001 is not supported
ID:17637 VHDL error at <location>: The path "<string>" does not exist
ID:17638 VHDL info at <location>: The default vhdl library search path is now "<string>"
ID:17639 VHDL info at <location>: The vhdl library search path for library "<string>" is now "<string>"
ID:17640 VHDL error at <location>: This parse-tree is too large to be saved
ID:17641 VHDL error at <location>: A VHDL parse-tree node is trying to be created from a SaveRestore object that is in save mode!
ID:17642 VHDL info at <location>: Binary saving <string> '<string>'
ID:17643 VHDL error at <location>: Registering Dependencies Error: Type of design unit \'<string>.<string>\'
ID:17644 VHDL error at <location>: Registering Dependencies Error: <string> '<string>' could not be found during restore
ID:17645 VHDL error at <location>: Registering Dependencies Error: The library \'<string>\' is not defined
ID:17646 VHDL error at <location>: <string> needs to be re-saved since <string>.<string> changed
ID:17647 VHDL error at <location>: <string> needs to be re-saved since <string>.<string>.<string> changed
ID:17648 VHDL error at <location>: Registering Dependencies Error: unknown pointer type
ID:17649 VHDL error at <location>: cannot open vhdl file <string>
ID:17650 VHDL error at <location>: VHDL reader: User Interrupt. Cleaning up....
ID:17651 VHDL warning at <location>: readline called past the end of file <string>
ID:17652 VHDL error at <location>: character/string literal may not be designator for an object alias
ID:17653 VHDL error at <location>: prefix of attribute <string> is not a type mark
ID:17654 VHDL error at <location>: invalid use of incomplete type
ID:17655 VHDL error at <location>: invalid syntax for subtype indication
ID:17656 VHDL error at <location>: invalid use of deferred constant <string>
ID:17657 VHDL error at <location>: signal formal <string> cannot be associated with type conversion or function call at actual
ID:17658 VHDL error at <location>: the type <string> of vhdl port <string> is invalid for verilog connection
ID:17659 VHDL error at <location>: array size is larger than 2**<number>
ID:17660 VHDL warning at <location>: prefix of expanded name does not denote an enclosing construct
ID:17661 VHDL error at <location>: signal assignments not allowed in entity statement part
ID:17662 VHDL error at <location>: name of entity to be configured by <string> is same as configuration name
ID:17663 VHDL error at <location>: the attribute specification for design unit <string> is not within the declarative part of the design unit
ID:17664 VHDL error at <location>: wait statements in branch statements are not supported for synthesis
ID:17667 VHDL error at <location>: component instantiation <string> is already bound with primary unit <string>, should not be bound again with <string>
ID:17668 VHDL error at <location>: binding indication in configuration specification must have entity aspect
ID:17669 VHDL error at <location>: <string> configuration specification for component <string> must be last one given
ID:17670 VHDL error at <location>: verilog module port <string> does not match with type <string> of component port
ID:17671 VHDL error at <location>: cannot assign signal <string> from within a subprogram
ID:17672 VHDL warning at <location>: cannot call impure function <string> from within pure function <string>
ID:17673 VHDL error at <location>: cannot call impure function <string> from within pure function <string>
ID:17674 VHDL warning at <location>: cannot call side-effect procedure <string> from within pure function <string>
ID:17675 VHDL error at <location>: cannot call side-effect procedure <string> from within pure function <string>
ID:17676 VHDL error at <location>: protected body <string> has no protected type defined
ID:17677 VHDL error at <location>: protected type method argument cannot be file or access type
ID:17678 VHDL error at <location>: protected type method cannot return file or access type
ID:17679 VHDL error at <location>: array type case expression must be of a locally static subtype
ID:17680 VHDL error at <location>: protected type is not yet supported for synthesis
ID:17681 VHDL error at <location>: access type cannot be a formal of mode out
ID:17682 VHDL error at <location>: near <string> ; prefix should denote a discrete or physical type or subtype
ID:17683 VHDL error at <location>: cannot dereference a null access value
ID:17684 VHDL error at <location>: expression has <number> elements ; formal <string> expects <number>
ID:17685 VHDL error at <location>: formal <string> associated individually was not in contiguous sequence
ID:17686 VHDL error at <location>: error in protected region near <string>
ID:17687 VHDL warning at <location>: binary dump database must be encrypted to secure `protect RTL
ID:17688 VHDL error at <location>: verilog module parameter <string> does not match with type <string> of component generic
ID:17689 VHDL error at <location>: cannot truncate invalid sized bit string literal <string>
ID:17690 VHDL error at <location>: use of library logical name WORK is invalid inside context declaration
ID:17691 VHDL error at <location>: suffix <string> in the context reference does not denote a context declaration
ID:17692 VHDL error at <location>: VHDL 1076-2008 construct not yet supported
ID:17693 VHDL error at <location>: aggregate target name has already been specified
ID:17694 VHDL error at <location>: Invalid if generate syntax, else branch should appear last
ID:17695 VHDL error at <location>: <string> is not an uninstantiated package
ID:17696 VHDL error at <location>: subprogram kind mismatch in subprogram instantiation
ID:17697 VHDL error at <location>: invalid nesting of resolution indication function
ID:17698 VHDL error at <location>: this construct is only supported in VHDL 1076-2008
ID:17699 VHDL error at <location>: subprogram name should be specified as actual for formal generic subprogram <string>
ID:17700 VHDL error at <location>: package name should be specified as actual for formal generic package <string>
ID:17701 VHDL error at <location>: only alternative label can be used with if/case generate statement
ID:17702 VHDL error at <location>: question mark delimiter should be in both places after keyword case
ID:17703 VHDL error at <location>: case expression type of matching case is not a bit or a std_ulogic or 1-dimensional array of bit/std_ulogic
ID:17704 VHDL error at <location>: case expression type of matching case is not a bit/std_ulogic array type
ID:17705 VHDL error at <location>: external name referring <string> is not yet supported
ID:17706 VHDL error at <location>: package path name should start with library logical name
ID:17707 VHDL error at <location>: absolute path name should start with primary unit name
ID:17708 VHDL warning at <location>: /* in comment
ID:17709 VHDL error at <location>: element type of the array declaration is same as the parent array type
ID:17710 VHDL error at <location>: a function name may not be an uninstantiated subprogram
ID:17711 VHDL error at <location>: variable in package inside process,subprogram or protected block cannot be 'shared'
ID:17712 VHDL warning at <location>: keyword inertial can only be used in port map
ID:17713 VHDL error at <location>: function return type is not specified
ID:17714 VHDL error at <location>: non empty context clause cannot precede a context declaration
ID:17715 VHDL info at <location>: multiple clocking is not yet supported
ID:17716 VHDL info at <location>: single wait statement, no need to convert to explicit state machine
ID:17717 VHDL info at <location>: not converting statement with event control without edged expression
ID:17718 VHDL error at <location>: parameter should be followed by its list
ID:17719 VHDL warning at <location>: possible infinite loop in some certain condition
ID:17720 VHDL error at <location>: invalid element in external name
ID:17721 VHDL error at <location>: external reference <string> remains unresolved
ID:17722 VHDL warning at <location>: enumeration array type not supported in cross language port/generic connection
ID:17723 VHDL error at <location>: external name referring <string> is not bound
ID:17724 VHDL warning at <location>: invalid subtype indication in alias declaration for external name
ID:17725 VHDL error at <location>: <string> is not the top unit
ID:17726 VHDL error at <location>: <string> cannot be used as a port
ID:17727 VHDL error at <location>: no package instance is specified for interface package element <string>
ID:17728 VHDL error at <location>: default expression or subprogram is not specified in uninstantiated package for interface package element <string>
ID:17729 VHDL error at <location>: formal generic package <string> does not match with actual
ID:17730 VHDL error at <location>: uninstantiated package cannot be specified in use clause
ID:17731 VHDL error at <location>: <string> statement have same choice in multiple items
ID:17732 VHDL error at <location>: matching choice with value <string> does not represent any value
ID:17733 VHDL warning at <location>: value in initialization depends on signal <string>
ID:17734 VHDL error at <location>: element type of the record element is same as the parent record type
ID:17735 VHDL error at <location>: pragma function <string> cannot fit multi-bit result into single-bit return type <string>
ID:17736 VHDL error at <location>: block comment was not closed
ID:17737 VHDL warning at <location>: access value for <string> is not allocated or already free'd
ID:17738 VHDL warning at <location>: condition in if generate must be static
ID:17739 VHDL warning at <location>: range in for generate must be static
ID:17740 VHDL warning at <location>: expression in case generate must be globally static
ID:17741 VHDL error at <location>: group constituent <string> must be <string>
ID:17742 VHDL error at <location>: <string> group constituents in group declaration
ID:17743 VHDL error at <location>: entity class entry with box must be the last one within the entity class entry list
ID:17744 VHDL error at <location>: '<string>' is not compiled in package <string>
ID:17745 VHDL error at <location>: record element <string> is already constrained
ID:17746 VHDL error at <location>: near <string> ; prefix should denote an object or object alias
ID:17747 VHDL error at <location>: <string> was created using an incompatible version_number, vhdl 2008 backward compatibility is not supported for this version
ID:17748 VHDL error at <location>: choice others is not permitted when aggregate expression is of the aggregate type
ID:17749 VHDL error at <location>: array aggregate elements must be all named or all positional
ID:17750 VHDL error at <location>: choice direction does not match with the context direction
ID:17751 VHDL error at <location>: signature not allowed for non-overloadable entity
ID:17752 VHDL warning at <location>: default expression of interface object is not globally static
ID:17753 VHDL error at <location>: matching case selector expression contains meta value '-'
ID:17754 VHDL error at <location>: actual values for generic <string> do not match between package instantiation and interface package
ID:17755 VHDL error at <location>: <string> is not allowed in package declaration
ID:17756 VHDL error at <location>: range expression expected here
ID:17757 VHDL error at <location>: unaffected is not allowed in sequential signal assignment statement
ID:17758 VHDL error at <location>: type mismatch in <string>
ID:17759 VHDL error at <location>: ambiguous type in <string>, <string>
ID:17760 VHDL error at <location>: character <string> of type <string> is not expected here
ID:17761 VHDL error at <location>: source of subprogram instantiation is not an uninstantiated subprogram
ID:17762 VHDL error at <location>: target of signal force must be a signal
ID:17763 VHDL error at <location>: aggregate is not allowed as the target of signal <string>
ID:17764 VHDL warning at <location>: design unit <string> contains uninitialized generic(s) <string>
ID:17765 VHDL warning at <location>: unit <string> does not have a generic named <string> to override
ID:17766 VHDL error at <location>: protected type <string> body is already defined
ID:17767 VHDL error at <location>: argument of operator <string> cannot be an OTHERS aggregate
ID:17768 VHDL error at <location>: suffix of protected type name cannot be 'all'
ID:17769 VHDL error at <location>: element <string> is not in protected type <string>
ID:17770 VHDL warning at <location>: shared variables must be of a protected type
ID:17771 VHDL error at <location>: argument out of valid domain in function <string>
ID:17772 VHDL error at <location>: bad record element constraint
ID:17773 VHDL warning at <location>: signal <string> is used in subtype-indication/type-definition
ID:17774 VHDL warning at <location>: <string> was previously created using a non-PSL-enabled VHDL analyzer, and since the current VHDL analyzer is PSL-enabled, there is a high probability that a restore error will occur due to newer VHDL 2008 constructs
ID:17775 VHDL warning at <location>: an index in an external name must be a globally static expression
ID:17776 VHDL error at <location>: <string> is not the label of a generate
ID:17777 VHDL error at <location>: index value <string> is out of range for for-generate <string>
ID:17778 VHDL warning at <location>: exponentiation operation has overflowed
ID:17779 VHDL warning at <location>: no top level unit found, elaboration aborted
ID:17780 VHDL error at <location>: parameter value of attribute '<string>' is invalid
ID:17781 VHDL error at <location>: an ending label <string> found but there was no main label
ID:17782 VHDL error at <location>: library alias name <string> already exists as a logical library
ID:17783 VHDL error at <location>: 'in' port <string> cannot be forced mode out
ID:17784 VHDL warning at <location>: complex expressions in variable slices are assumed independent, this may lead to extra logic.
ID:17785 VHDL error at <location>: Libraries exist. Creation of dual dialect vdb file failed.
ID:17786 VHDL info at <location>: multiple matching subprogram for <string>
ID:17787 VHDL info at <location>: another match here
ID:17788 VHDL error at <location>: unit <string> not found in 1993 version of the library <string>
ID:17789 VHDL info at <location>: package <string> not present in 2008
ID:17790 VHDL info at <location>: procedure <string> not present in 2008
ID:17791 VHDL error at <location>: member <string> of uninstantiated package <string> is referenced outside the scope of the package
ID:17792 VHDL error at <location>: designated type of access type cannot be protected type
ID:17793 VHDL error at <location>: elements of protected type are not allowed in composite types
ID:17794 VHDL error at <location>: null range choice is allowed only if it is the only choice of the aggregate association
ID:17795 VHDL error at <location>: formal part(function-call/type-conversion) needs formal designator as argument
ID:17796 VHDL warning at <location>: return type of pure function cannot be of access type
ID:17797 VHDL warning at <location>: return type of function cannot be of a file type or protected type
ID:17798 VHDL error at <location>: actual subprogram <string> associated with formal <string> cannot be uninstantiated
ID:17799 VHDL error at <location>: target of simple force assignment cannot be a member of a resolved composite signal
ID:17800 VHDL error at <location>: <string> is not allowed in a package, declared in a subprogram, process statement or protected type body
ID:17801 VHDL error at <location>: port map aspect and generic map aspect are not allowed if entity aspect is open
ID:17802 VHDL warning at <location>: component instance <string> does not have a primary binding
ID:17803 VHDL error at <location>: OTHERS or ALL should be the only signal name in the list
ID:17804 VHDL error at <location>: time expression in disconnect specification must be static
ID:17805 VHDL error at <location>: <string> is not a guarded signal
ID:17806 VHDL warning at <location>: ignoring non-constant initial value of <string>
ID:17807 VHDL warning at <location>: parameter of resolution function <string> is not an unconstrained array
ID:17808 VHDL warning at <location>: resolution function <string> cannot be an impure function
ID:17809 VHDL error at <location>: a file cannot be of formal generic type
ID:17810 VHDL error at <location>: uninstantiated package <string> cannot be used in external name
ID:17811 VHDL error at <location>: the object class <string> specified for external name is inconsistent with the class of denoted object <string>
ID:17812 VHDL error at <location>: variable <string> denoted by external name is not a shared variable
ID:17813 VHDL warning at <location>: exponentiation operation may overflow
ID:17814 VHDL warning at <location>: exponent may be negative
ID:17815 VHDL error at <location>: an event on the clock enable condition is not supported for synthesis
ID:17816 VHDL error at <location>: synthesis directive "<string>" is not supported
ID:17817 VHDL error at <location>: synthesis directive "read_comments_as_HDL" is not supported
ID:17818 Netlist warning at <location>: net <string> is already driven by input port <string>
ID:17819 Netlist info at <location>: this is where the port is declared
ID:17820 Netlist info at <location>: net <string> is declared here
ID:17821 Netlist error at <location>: port <string> of width <number> cannot connect to <number> bit actual
ID:17822 Netlist warning at <location>: net <string> is driven by multiple input ports
ID:17823 Netlist info at <location>: driving port <string> is declared here
ID:17824 Netlist error at <location>: unexpected driver found on RAM net, write_port expected
ID:17825 Netlist error at <location>: output of write_port is not a RAM net
ID:17826 Netlist error at <location>: unexpected sink found on RAM net, read_port expected
ID:17827 Netlist error at <location>: input of read_port is not a RAM net
ID:17828 Netlist error at <location>: cannot open file <string>
ID:17829 Netlist error at <location>: <string> was created using code corresponding to a db_version_number of <string>. Currently, backward compatibility (version < 0x0ab00001) is not supported
ID:17830 Netlist error at <location>: An error occurred during database binary restore
ID:17831 Netlist warning at <location>: initial value for ram <string> must be preserved to avoid dangling nets after ram blast
ID:17832 Netlist warning at <location>: mix of clocked and un-clocked RAM write from multiple concurrent area is not supported for blasting
ID:17833 Netlist error at <location>: mixed blocking and non-blocking assignments on write port is not supported
ID:17834 Netlist error at <location>: multiplier size is larger than 2**<number> bits
ID:17835 Netlist warning at <location>: huge infered rams
ID:17836 Netlist error at <location>: unresolved external reference <string>, cannot save binary database
ID:17837 RX channel < <name> > requires an associated reference clock pin. Connect a reference clock pin to the RX channel.
ID:17838 TX PLL < <name> > requires an associated reference clock pin. Connect a reference clock pin to the TX PLL.
ID:17854 Verilog HDL warning at <location>: index <number> falls outside the bounds [<number>:<number>] of array "<name>"
ID:17855 Specify the missing required remote farm settings.
ID:17856 The DSP block WYSIWYG primitive "<atom name>" requires that the <port names> data ports be connected in the current operation mode. Make sure the specified ports of the specified WYSIWYG are connected.
ID:17857 Port(s) <port name> for DSP block WYSIWYG primitive "<atom name>" should not be connected when parameter <parameter name> is set to "<value>". Make sure the parameter is set correctly or disconnect the violating port.
ID:17858 Port <port name> for DSP block WYSIWYG primitive "<atom name>" should be connected when parameter <parameter name> is set to "<value>".
ID:17860 The width of port <port name> for DSP block WYSIWYG primitive "<atom name>" should be <number> bits when parameter <parameter name> is set to "<value>".
ID:17861 The width of port <port name> for DSP block WYSIWYG primitive "<atom name>" should match the value given by the parameter <parameter name>.
ID:17863 The --write_settings_files option cannot be on in QHD mode. This option will be ignored, leaving the Quartus settings file unmodified. Use the command-line option --write_settings_files=off to avoid this warning.
ID:17865 Parameter(s) <parameter name> for DSP block WYSIWYG primitive "<atom name>" must be <value> when <atom setting condition>.
ID:17866 No path was found satisfying set_net_delay assignment from "<From Collection>" to "<To Collection>".
ID:17867 Created QLK file <name>
ID:17868 Can't generate the encryption lock file (.qlk). Choose a target device that supports encryption lock files, or change your encryption settings.
ID:17869 The <feature name> feature for DSP block WYSIWYG primitive "<atom name>" is not supported when parameter <parameter 1> is set to <value>. Change the specified parameter or disable the feature by changing parameter <parameter 2> to "<value>".
ID:17870 The <feature name> feature on the top and bottom multiplier for DSP block WYSIWYG primitive "<atom name>" should be used simultaneously. Make sure that parameters <parameter 1> and <parameter 2> are both set to "<value>" to enable the feature.
ID:17871 Parameter(s) <parameter 1> for DSP block WYSIWYG primitive "<atom name>" can only be set to "<value>" if parameter <parameter 2> is set to "<value>".
ID:17872 Port(s) <port name> for DSP block WYSIWYG primitive "<atom name>" should not be connected when parameter <parameter 1> is set to "<value>" and <parameter 2> is set to <value>. Make sure the parameters are set correctly or disconnect the violating port.
ID:17873 Parameter <parameter 1> for DSP block WYSIWYG primitive "<atom name>" should have the same value as parameter <parameter 2> when <condition>.
ID:17875 Strictly preserved Logic Lock region "<name>" cannot contain excluded element types. Change your design so that excluded element types are removed from the specified strictly preserved Logic Lock region.
ID:17877 The PMA interface width of master clock generation block (CGB) < <name> > is different from the PMA interface width of slave CGB < <name> > for bonded HSSI group with channel < <name> >. Modify your HSSI IP core so the PMA interface width for the master and slave CGBs are the same.
ID:17883 To enable the scan chain feature, port SCANIN for DSP block WYSIWYG primitive "<atom name>" must be connected from the SCANOUT port of another DSP block.
ID:17884 Port <port name> bus should have signals from the same source for DSP block WYSIWYG primitive "<atom name>". Check that all bus signals are coming from another DSP block.
ID:17889 <message>
ID:17891 Ports SCANIN and CHAININ for DSP block WYSIWYG primitive "<atom name>" are connected from different DSP blocks. Make sure that ports SCANIN and CHAININ of the specified DSP block are connected from the same DSP block.
ID:17893 To properly enable the scan chain feature, port SCANOUT for DSP block WYSIWYG primitive "<atom name>" must be connected to the SCANIN port of another DSP block and circular connection is not allowed
ID:17894 Ports SCANOUT and CHAINOUT for DSP block WYSIWYG primitive "<atom name>" are connected to different DSP blocks. Make sure that ports SCANOUT and CHAINOUT of the specified DSP block are connected to the same DSP block.
ID:17896 Port <port name> for DSP block WYSIWYG primitive "<atom name>" must only drive one port.
ID:17897 No <Clock Type>clock period was found satisfying the <Assignment Type> assignment from "<From Collection>" to "<To Collection>". The assignment at location <Location> is invalid.
ID:17898 VHDL Primary Unit Declaration warning at <location>: overwriting existing primary unit "<name>"
ID:17899 VHDL Secondary Unit Declaration error at <location>: overwriting existing secondary unit "<name>"
ID:17900 To properly enable the chainadder feature, port CHAININ for DSP block WYSIWYG primitive "<atom name>" must be connected from the CHAINOUT port of the previous DSP block.
ID:17901 To properly enable the chainadder feature, port CHAINOUT for DSP block WYSIWYG primitive "<atom name>" must be connected to the CHAININ port of the next DSP block and circular connection is not allowed
ID:17902 Port <port name> for DSP block WYSIWYG primitive "<atom name>" when connected should be <number> bits wide.
ID:17903 Port <clear port name> for DSP block WYSIWYG primitive "<atom name>" is connected to VCC, resulting in the output signals always being cleared.
ID:17904 The dynamic control signals input register clocks "load_const_clock", "accumulate_clock", "negate_clock" and "sub_clock" of the DSP block WYSIWYG primitive "<atom name>" should be driven by the same clock source. However, each clock signal can be individually bypassed (meaning no input register is used for the corresponding dynamic control signal) by assigning the value "none".
ID:17906 DSP block WYSIWYG primitive "<atom name>" has different settings for bx_clock and by_clock in operation_mode "<operation mode>". When one of the clocks are used, the other must also be driven by the same clock source.
ID:17907 When in systolic mode and the second pipeline register is used for DSP block WYSIWYG primitive "<atom name>", second_pipeline_clock and input_systolic_clock must share the same clock source.
ID:17909 Error detection has been disabled
ID:17910 The cell named <name> with ID <id> is not a physical cell.
ID:17911 The location named <name> with ID <id> is not a physical cell location.
ID:17912 Partition "<partition_name>" contains an output port, "<port_name>", that connects to partition and has no routing. It is possible that the destination logic was swept away. Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
ID:17914 Partition "<partition_name>" contains a preserved output port, "<port_name>", that connects to "<dst_name>" in partition "<dst_partition_name>", entering the partition on port "<dst_partition_port>". This connection has no routing. Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
ID:17915 Margining VREF <vref> setting: <setting>
ID:17916 Partition "<partition_name>" contains an output port, "<port_name>", that connects to partition "<dst_partition_name >" on port "<dst_port_name>" and has no routing. It is possible that the destination logic was swept away. Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination.
ID:17917 The cell named <name> with ID <id> is not a placeable cell using interactive placement.
ID:17918 Can't generate the encrypted Hard Processor System (HPS) data. Verify that you are using the correct HPS data file and commands.
ID:17919 Almemmult megafunction does not support <device_family> device family. Instead, Intel recommends using the altera_syncram megafunction.
ID:17920 Checksum on line <number> does not match expected checksum
ID:17921 Data in HEX File overlaps between data blocks at address <address> and address <address>
ID:17922 File <text> is not a valid Hexadecimal (Intel-Format) File
ID:17923 Can't save or open file <name>
ID:17924 Found invalid character in MIF file <name>
ID:17925 File <name> is not a valid Memory Initialization File
ID:17926 An error occurred opening the file <filename>.
ID:17929 Verilog HDL warning at <location>: parameter initial value should not be omitted in this version of Verilog
ID:17931 Feature <name> is only available with a valid license. You can purchase this feature to gain full access to it.
ID:17932 Location <location> is already occupied by <count> <type>s
ID:17933 There is no valid device available for timing-analysis.
ID:17934 The top-level I/O names: "altera_reserved_tck", "altera_reserved_tms", "altera_reserved_tdi", and "altera_reserved_tdo" are reserved. Change the name of the following I/Os to another name that is not reserved: <res_pin_spec>.
ID:17936 Cannot perform requested placement operation because not all the affected cells have one or more legal locations.
ID:17937 The inputs to the LAB at location (<number>,<number>) exceed the number of legal inputs. This LAB may be locked or have other LAB-level input restrictions. Refer to the submessage(s) for the specific input nodes that do not fit in the LAB. Remove some inputs to this LAB so the number of inputs does not exceed the legal limit.
ID:17939 A design is already loaded.
ID:17940 A design is not loaded.
ID:17941 The design could not be loaded due to errors.
ID:17942 No open project exists
ID:17943 Your design contains pin assignments to I/O bank '<name>', however the specified I/O bank does not exist on the target device. In the Pin Planner, change your assignments so that all pins are assigned to legal locations.
ID:17944 Input and output buffers associated with the bi-directional pin "<pin name>" are in different partitions. Pin will be created in the top partition.
ID:17945 Calibrated <type> termination setting to value <setting>
ID:17947 Can't create Fault Injection File. Verify that you are using the uncompressed Raw Binary File.
ID:17949 Can't create Fault Injection File. Verify that you are using the uncompressed Raw Binary File.
ID:17950 Pin corresponding to CLKUSR has not been reserved in the device. Cannot perform unused RX clock workaround.
ID:17953 Preserved <number> unused RX channel(s).
ID:17954 Can't synthesize exponentiation operator "**" with non-constant operands (filename: "<name>", line: <number>). Change your design to remove the exponentiation operator.
ID:17955 Selected cell already placed. Unplace the cell before replacing.
ID:17956 A child cell of the cell named <cell_name> with ID <cell_id> is already placed in location named <placed_loc_name> with ID <placed_loc_id> and that is not a descendant location of the requested location named <desired_loc_name> with ID <desired_loc_id>.
ID:17959 Fast Forward step #<step number> completed.
ID:17965 This family is not supported by the Quartus Prime Pro Edition software.
ID:17966 Starting Hyper-Retimer operations.
ID:17968 Completed Hyper-Retimer operations.
ID:17971 Both the asynchronous clear and synchronous clear signals are selected in your IP core, however these signals cannot be selected simultaneously.Choose either the asynchronous clear or synchronous clear signal. Use the IP parameter Editor to instantiate IP cores in your design to avoid validation error.
ID:17972 Synchronous clear source error: illegal value <text> for <name> parameter. Use the IP Parameter Editor to regenerate the ALTERA_MULT_ADD IP core with a legal parameter value.
ID:17975 The loaded design is not writeable.
ID:17976 Merging of multiple assigned regions is prohibited.
ID:17977 Merging of multiple assigned regions is prohibited.
ID:17978 Device family <name> does not have <name> blocks -- using available memory blocks
ID:17979 "<Region target>" is constrained to the <placement/routing> region <Region bounding box(es)>, which is not fully contained by the region of its parent instance "<Parent region target>" <Parent region bounding box(es)>. As a result, design instance "<Region target>" will be constrained to the intersection of these regions <Updated region bounding box(es)>. Expand or move the bounds of the region or its parent region so that the regions overlap.
ID:17980 "<Region target>" is constrained to the <placement/routing> region <Region bounding box(es)> that does not overlap with the region of its parent instance "<Parent region target>" <Parent region bounding box(es)>
ID:17981 Assignment of type named <type> are not currently modifiable.
ID:17982 The assignment target <iname> could not be found in the design.
ID:17983 The desired assignemnt could not be created.
ID:17984 The point-to-point assignment cannot be created as the source <iname_src> and target <iname_dst> are not in the same partition.
ID:17985 WYSIWYG RAM Primitive "<name>" cannot use "<name>" in simple quad port port.
ID:17986 WYSIWYG RAM Primitive "<name>" the mixed-port read-during-write must use don't care or new_a_old_b when operation mode is set to "<name>" .
ID:17991 Assignment ID <id> not modifyable as it is already deleted.
ID:17996 Elaborating Platform Designer system entity "<name>"
ID:17997 Finished elaborating Platform Designer system entity "<name>"
ID:17998 <name>
ID:17999 <name>
ID:18000 Registers with preset signals will power-up high
ID:18008 Converted <number> single input CARRY primitives to CARRY_SUM primitives
ID:18009 Ignored <number> CARRY_SUM primitives
ID:18010 Register <name> will power up to <level>
ID:18011 Ignored <number> CARRY_SUM primitive(s) -- cannot place fan-out logic in single logic cell
ID:18012 Can't place logic fed by CARRY_SUM primitive "<name>" into a single logic cell
ID:18013 Ignored <number> CARRY_SUM primitives -- cannot place fan-in logic in single logic cell
ID:18014 Can't place logic feeding CARRY_SUM primitive "<name>" in single logic cell
ID:18015 Ignored <number> CARRY_SUM primitives -- logic cell requires more inputs than it can contain
ID:18016 Can't place CARRY primitive "<name>" -- logic cell requires more inputs than it can contain
ID:18017 CASCADE primitive "<name>" is fed by non-combinational logic
ID:18018 CASCADE primitive "<name>" contains fan-out to more than one destination
ID:18019 Can't implement CASCADE primitive "<name>" -- polarity of CASCADE primitives and other primitives in cascade chain are inconsistent
ID:18020 CASCADE primitive "<name>" fed by VCC or GND
ID:18021 Primitive "<name>" of type <type> cannot feed CASCADE primitive "<name>" because the primitive already contains fan-out to one or more CASCADE primitives
ID:18022 Can't feed XOR gate "<name>" with CASCADE primitive <name>
ID:18023 Can't feed gate primitive "<name>" with CASCADE primitive "<name>" because it is already fed by CASCADE primitive "<name>"
ID:18024 Can't feed gate "<name>" of type <type> with CASCADE primitive "<name>"
ID:18025 CARRY primitive "<name>" is part of cyclic carry chain
ID:18026 CASCADE primitive "<name>" is part of cyclic cascade chain
ID:18027 Carry chain that starts with CARRY primitive "<name>" requires <number> clear signals, but device can only contain <number> clear signals
ID:18028 Carry chain that starts with CARRY primitive "<name>" too long for the current device
ID:18030 Abort compilation after writing out the BLIF netlist.
ID:18032 Cout port of WYSIWYG LCELL primitive "<name>" is connected to gate primitive "<name>", but must be connected to a WYSIWYG LCELL
ID:18033 Cin port of WYSIWYG LCELL primitive "<name>" connected to gate primitive "<name>", but must be connected to a WYSIWYG LCELL
ID:18034 Cascout port of WYSIWYG LCELL primitive "<name>" is connected to gate primitive "<name>", but must be connected to a WYSIWYG LCELL
ID:18035 Cascin port of WYSIWYG LCELL primitive "<name>" is connected to gate primitive "<name>", but must be connected to a WYSIWYG LCELL
ID:18036 WYSIWYG LCELL primitive "<name>" feeds more than one logic cell via carry or cascade chains
ID:18042 Node "<name>" of type <type>
ID:18047 <name>
ID:18050 Node "<name>"
ID:18051 Found the following redundant logic cells in design
ID:18052 Removed the following redundant logic cells
ID:18053 Timing-driven register duplication created <number> duplicate registers
ID:18054 Ignored following assignments for SYNTH_CRITICAL_CLOCK
ID:18055 Ignored assignment for SYNTH_CRITICAL_CLOCK from clock "<name>" to clock "<name>" -- no registers were found for clock "<name>"
ID:18056 Ignored assignment for SYNTH_CRITICAL_CLOCK for clock "<name>" -- no registers were found for this clock
ID:18057 The assignment to disallow NOT gate push-back on register "<name>" is ignored
ID:18058 Inserted <number> logic cells for Maximum Fan-Out assignment on "<name>"
ID:18059 Ignored Maximum Fan-Out assignment
ID:18060 Ignored Maximum Fan-Out logic option for node "<name>"
ID:18061 Ignored Power-Up Level option on the following registers
ID:18062 Inserted logic cells for Maximum Fan-Out assignment
ID:18063 Output directory "<name>" could not be created or is not accessible
ID:18064 Qip file "<name>" that is being generated from a Platform Designer system file already exists in the project.
ID:18065 File "<dup_file>" is a duplicate of already analyzed file "<original_file>" (same filename, same library name and same md5 digest). Skipping analysis of this file.
ID:18066 Qip file "<qip_file>" that is being generated from the Platform Designer file already exists in the generation directory ("<generation_dir>").
ID:18067 One or more files being generated from the Platform Designer file already exist in the generation directory ("<generation_dir>") and they have been modified.
ID:18068 The previously generated files in the generation directory ("<generation_dir>") already match the files to be generated from the Platform Designer file.
ID:18069 Skipped generation of the Platform Designer file "<platform_designer_file>".
ID:18070 Previously generated files were detected in the Platform Designer file generation directory ("<generation_dir>").
ID:18071 Skipped generation of the Platform Designer file "<platform_designer_file>" based on the current regeneration policy setting (Tools/Settings/IP Settings).
ID:18072 Illegal project name "<name>".
ID:18075 Can't set current drive strength for an input pin (<pin name>) The assignment was ignored
ID:18078 The instance hierarchy "<name>" specified in the PARTIAL_RECONFIGURATION assignment does not refer to a partition. Specify an instance hierarchy that refers to a partition or create a design partition on this instance hierarchy.
ID:18081 Ramstyle is explicitly set to mixed_rw_old, setting RAM mixed-ports read-during-write behavior to old (filename: "<name>", line: <number>).
ID:18082 Ramstyle=mixed_rw_old overwrites mixed-ports read-during-write 'NEW' behavior specified in the RTL (filename: "<name>", line: <number>).
ID:18083 mixed_rw_old ramstyle conflicts with no_rw_check ramstyle. mixed_rw_check ramstyle will be ignored (filename: "<name>", line: <number>).
ID:18084 Assignments for the current design are not available in the current context.
ID:18085 VCCR_GXB/VCCT_GXB QSF Voltages assignment missing for "<name>". The QSF assignment can be added as "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE <a voltage value (0_9V, 1_0V or 1_1V)> -to <name of the input/ouput port of the top level design>". In case an explicit assignment cannot be added for an instance, the warning can be suppressed by adding a statement to the .qip files as follows "set_instance_assignment -name MESSAGE_DISABLE 18085 -entity "<entity name>" ".
ID:18086 The Quartus Prime Pro Edition software does not support this feature.
ID:18087 Signal: <signal>
ID:18088 Region has routing region. Edit the routing region size and location via the Chip Editor.
ID:18089 Region has no routing region. Setting the Routing Region to YES will create a default routing region. Edit the routing region size and location via the Chip Editor.
ID:18090 External memory and PHYLite interfaces must share common reset signal when constrained to the same I/O column. The following conflicting signals were found:
ID:18091 Your design contains a NativePHY or PLL IP core with a transceiver channel or PLL block, however you did not explicitly instantiate a corresponding PreSICE Calibration Engine. Instantiate the corresponding PreSICE Calibration Engine on the same side as the transceiver channel or PLL block and constrain the strip on which the PreSICE Calibration Engine resides. You can instantiate the PreSICE Calibration Engine with the altera_xcvr_uc_a10 IP core.
ID:18092 Your design contains invalid or duplicate Signal Tap assignments as a result of migrating your design. To remove the invalid or duplicate assignments, run Analysis and Synthesis or a full compilation from the GUI, or run the quartus_stp module from the command-line before running a full compilation.
ID:18093 Memory depth (<number>) in the Memory Initialization File "<name>" is larger than the flash memory depth (<number>). Truncated remaining initial content value to fit flash memory. If you do not want the remaining initial content value to be truncated, make sure the Memory Initialization File contains the same memory depth values for the flash memory.
ID:18094 Memory depth (<number>) in the Memory Initialization File "<name>" is less than the flash memory depth (<number>). Make sure the Memory Initialization File contains the sufficient memory depth values for the flash memory.
ID:18095 WYSIWYG primitive "<name>" has port A data input unregistered. Port A data input must be connected to a register with same clock source.
ID:18096 WYSIWYG primitive "<mlab name>" and WYSIWYG primitive "<reg name>" are connected to different clock source. Port A data input must be connected to a register with same clock source.
ID:18097 Partition "<original_partition>" contains assignment "<assignment_name>" with setting "<original_value>", which is different from setting "<partition_value>" in partition "<partition_name>". Modify your design so all partitions use the same setting for the specified assignment.
ID:18098 The "HPS early release of HPS I/O" option is not available in the Arria 10 ES silicon. Use a non ES part or disable the HPS early release of HPS I/O
ID:18101 An external memory interface or PHYLite IP core reference clock fed by a cascaded PLL. Connect the external memory interface or PHYLite IP core reference clock to an input buffer.
ID:18102 Upstream PLL: <PLL name>
ID:18103 Downstream PLL: <PLL name>
ID:18105 Port pin_perst of PCI Express hard IP block <name> is not connected to a top-level pin. Connect the pin_perst port to a top-level pin.
ID:18107 Partition "<parent_partition>" is preserved at snapshot "<parent_snapshot>", however child partition "<child_partition>" is preserved at earlier snapshot "<child_snapshot>". Modify your design so that child partitions contain preservation directives later than their parent partitions.
ID:18108 Can't place multiple pins assigned to pin location <name> (<name>)
ID:18109 Pin <name> is assigned to pin location <name> (<name>)
ID:18110 Your design has autonomous hard IP for PCI Express mode enabled and contains Hard IP for PCI Express block < <text> >, but does not have a hard reset controller connected to the specified block. You have used the INI variable hssi_stratixv_bypass_ahip_with_src_check=on to allow you to compile your design with this set of conditions. To remove the warning, add a hard reset controller or turn off the autonomous hard IP for PCI Express mode.
ID:18111 Partition "<partition_name>" specified to be preserved does not exist in the design. Specify a valid partition for preservation.
ID:18113 Design template installation failed
ID:18115 Logic Lock region has a routing region as an expansion over the Logic Lock region. Edit the routing region expansion size and location via the Chip Editor.
ID:18119 The routing expansion of a Logic Lock region must be a non-negative integer
ID:18120 Project name required.
ID:18121 Illegal top-level entity name "<name>".
ID:18123 The databases already exist, use -overwrite.
ID:18124 The requested databases do not exist in the archive.
ID:18125 Port "<name>" does not exist in macrofunction "<name>".
ID:18126 PR user pin <user pin> conflicts with reserved pin <reserved pin>. Try setting the reserved pin as regular I/O.
ID:18127 The operation is invalid because it will cause the region to fall outside of its routing region.
ID:18128 Both the asynchronous and synchronous clear signals are selected in your IP core, however these signals cannot be selected simultaneously. Choose either the asynchronous clear or synchronous clear signal. Use the IP parameter Editor to instantiate IP cores in your design to avoid validation error.
ID:18129 Clock need to be enabled when using asynchronous clear or synchronous clear signal.
ID:18133 The Logical Element multiplier implementation cannot be used together with synchronous clear signal for LPM_MULT.
ID:18134 The squaring operation cannot be used together with synchronous clear signal for LPM_MULT.
ID:18135 Can't compile design--your project generates files with paths that exceed the maximum length allowed by the operating system. Move or rename the project directory to reduce the number of characters in the path. The following file paths exceed the operating system limits: <files_spec>
ID:18136 Delay value "<Delay>" is not valid
ID:18137 Port at position <number> does not exist in macrofunction "<name>"
ID:18138 PCI Express Hard IPs < <name> > and < <name> >'s two ATX PLLs are <number> ATX PLLs apart. They need to be 3 or more ATX PLLS apart. Modify the PCI Express Hard IPs location constraints in the Assignment Editor to make ATX PLLs placement legal.
ID:18139 Hyper-Retimer failed to successfully retime the circuit.
ID:18140 The operation is invalid because it will cause the Logic Lock region to fall outside of its routing region.
ID:18141 The channel location corresponding to pin-name < <name> > is non-empty. Unused channel preservation is not needed.
ID:18142 Unused channel preservation is not supported for a non-production device.
ID:18143 The file <name> was already specified
ID:18144 Unable to generate port diff report due to errors when running IP port diff tool
ID:18145 Old IP file <name> has module name <name> whereas the new IP file <name> has module name <name>
ID:18146 The specified partition '<partition>' does not exist in the design. Specify a valid partition name.
ID:18149 The large periphery clock type is not supported in the version of Quartus Prime Pro. Please modify the clock type of the following signal.
ID:18150 Unable to change the Routing Region property for the Logic Lock region named "<name>" to <value>. View the message in the System tab of the Messages window for details.
ID:18151 Device <name> does not support using bitstream encryption and bitstream compression features simultaneously.
ID:18152 <reason>
ID:18153 DDIO_OUT "<name>" async_mode parameter must be set to "clear" or "preset" when "areset" port is connected
ID:18154 DDIO_OUT "<name>" sync_mode parameter must be set to "clear" or "preset" when "sreset" port is connected
ID:18155 DDIO_IN "<name>" async_mode parameter must be set to "clear" or "preset" when "areset" port is connected
ID:18156 DDIO_IN "<name>" sync_mode parameter must be set to "clear" or "preset" when "sreset" port is connected
ID:18158 Unable to change the Routing Expansion property for the Logic Lock region named "<name>" to <value>. View the message in the System tab of the Messages window for details.
ID:18160 Unable to change the Core-Only property for the Logic Lock region named "<name>" to <value>. View the message in the System tab of the Messages window for details.
ID:18162 More than one device family has been specified on the command line. The last specified family will be used.
ID:18163 Pin ~ALTERA_CLKUSR~ was reserved for calibration. This pin must be assigned a 100-125 MHz clock.
ID:18164 The design contains partial reconfiguration or Reserved Core partitions <failed_pr_partitions>, that are not in Logic Lock region, that is, reserved, core-only region with a defined routing region. Modify your design so that all such partitions are in a Logic Lock regions with the correct settings.
ID:18165 "<Region target>" placement constraint <Region bounding box(es)> must be fully contained within routing constraint <Region routing bounding box(es)>
ID:18167 "<Region target>" is constrained to an invalid <placement/routing> region "<Region>"
ID:18169 The Quartus Prime Pro Edition Design Software must be installed to use quartus_syn. Either install the Quartus Prime Pro Edition Design Software or use quartus_map.
ID:18170 Fitter needs to use <number> out of <number> entities of type <string> in this region
ID:18171 Fitter needs to use <number> out of <number> entities of type <string> in this region
ID:18173 Quartus Prime Pro Edition Logic Lock region assignments can only be used in Quartus Prime Pro Edition. Remove these assignments, or modify them to use Quartus Prime Standard Logic Lock region assignments.
ID:18174 Unknown snapshot "<ss_override>". Using the last successful snapshot "<ss_last_compiled>". Refer to --help for --snapshot values.
ID:18175 Quartus Prime Pro Edition uses a new compilation directory structure. Once converted, this project cannot be used in other editions of Quartus Prime. Continue with this project in Quartus Prime Pro Edition?
ID:18176 This project uses the Quartus Prime Pro Edition compilation directory structure. It can only be opened in the Quartus Prime Pro Edition.
ID:18178 Are you sure that you want to delete the selected Logic Lock region "<name>" and its routing region? You will not be able to undo the operation.
ID:18179 Can't merge the selected Logic Lock regions. <reason>
ID:18184 Port "<name>" in macrofunction "<name>" has no range declared,the Quartus Prime software will connect the port to pin "<name>" because the pin is a member of a single bit bus with the same name as the port
ID:18185 Your design contains IP components that must be regenerated. To regenerate your IP, use the Upgrade IP Components dialog box, available on the Project menu in the Quartus Prime software
ID:18186 You must upgrade the IP component instantiated in file <instance> to the latest version of the IP component.
ID:18187 <note>
ID:18188 The width and height of a Logic Lock region must be positive integers
ID:18189 Unable to change the width of the Logic Lock region named "<name>" to <value>. <reason>
ID:18190 Unable to change the height of the Logic Lock region named "<name>" to <value>. <reason>
ID:18191 Unable to change the Origin for the Logic Lock region named "<name>" to "<value>". <reason>
ID:18192 Unable to change the Reserved property for the Logic Lock region named "<name>" to <value>. <reason>
ID:18193 The Logic Lock region named "<name>" can no longer be found. It may have been deleted.
ID:18194 Unable to delete the Logic Lock region named "<name>". <reason>
ID:18195 Unable to merge the Logic Lock regions. <reason>
ID:18196 Unable to load Logic Lock region assignments. Either there is no open project, or the Quartus Prime Settings File for the project is corrupted or missing.
ID:18197 Are you sure that you want to delete the selected Logic Lock region and its routing region?
ID:18198 Location <name> is not a legal origin for a Logic Lock region.
ID:18199 ECC feature cannot be used for the specified combination of parameters(i.e ram block). ECC does not support mixed widths DCFIFO.
ID:18200 ECC feature cannot be used for the specified combination of parameters(i.e ram block).
ID:18201 ECCSTATUS port must exist when enable_ecc is true and vice versa.
ID:18202 ECCSTATUS port must exist when enable_ecc is true and vice versa.
ID:18203 Invalid clock region assignment "<full clock region assignment string>". "<clock region name>" is not a valid clock region.
ID:18205 ATX PLLs < <name> > and < <name> > under feedback compensated transceiver group < <name> > are < <number> > ATX PLLs apart. Modify the ATX PLLs location constraints in the Assignment Editor to make ATX PLLs at least 4 ATX PLLS apart.
ID:18207 Some modules have been skipped due to smart recompilation. You can turn off smart recompilation under Compilation Process Settings in the Settings dialog to fully recompile your design
ID:18208 "<Region target>" is a reserved region with placement constraint <Region bounding box(es)>
ID:18209 "<Region target>" is an empty region because it is excluded by the other reserved regions.
ID:18210 Quartus Prime Standard Edition Logic Lock region assignments cannot be used in Quartus Prime Pro Edition. Remove these assignments or modify them to use the Quartus Prime Pro Edition Logic Lock region assignments.
ID:18212 Cannot load <snapshot> snapshot for partition "<partition>" - the partition is not in a version compatible format.
ID:18213 Device <name> does not support using bitstream encryption during <name> mode. Disable the encryption feature to generate a bitstream.
ID:18215 Quartus Prime Standard Edition Logic Lock region assignments cannot be used in Quartus Prime Pro Edition. Remove these assignments, or modify them to use Quartus Prime Pro Edition Logic Lock region assignments.
ID:18217 Found multiple interfaces with ID <bad_id>. Reassigning one of them to ID <new_id>.
ID:18218 Attempted to fit <Number of merge groups> IOPLL merge groups in <Number of IOPLL locations> locations.
ID:18229 Failed to update settings from the imported netlist to the current version of the software.
ID:18230 Checking the imported netlist for invalid settings in the current version of the software.
ID:18231 Legalizing the imported netlist to the current version of the software.
ID:18232 Successfully updated settings from the imported netlist to the current version of the software.
ID:18233 System Verilog output format is not supported by the EDA Netlist Writer in the Quartus Prime Pro Edition software. Refer to --help for --format values.
ID:18234 ATX PLLs <name> and <name> are <number> ATX PLLs apart. For ATX PLL VCO frequencies between <name> and <name>, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), they must be placed <number> ATX PLLs apart.
ID:18235 Library search order is as follows: "<name>". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER.
ID:18237 File "<dup_file>" is a duplicate of already analyzed file "<original_file>" (same filename, same library name and same md5 digest). Skipping analysis of this file.
ID:18238 OpenCore Simulation-Only Evaluation feature is turned on for all cores in the design
ID:18239 OpenCore Plus Hardware Evaluation feature is not supported in Quartus Prime Pro Edition Design Software, defaulting to OpenCore Simulation-Only Evaluation.
ID:18240 Platform Builder Editor is not installed or could not be found
ID:18241 Platform Builder Editor (<text>) failed to launch
ID:18242 File extension (<name>) is not supported by the Platform Builder Editor
ID:18243 File '<file name>' already exists. Do you want to overwrite the existing file?
ID:18244 Platform Builder file (<file name>) cannot be created
ID:18249 The current design uses partial reconfiguration, but the current license file does not support partial reconfiguration. Upgrade the license to support partial reconfiguration or remove any assignment or IP that uses partial reconfiguration.
ID:18251 "<Requested Operating Conditions>" does not match any valid operating conditions. Available operating conditions are: <Available Operating Conditions>
ID:18252 The Fitter is using Physical Synthesis.
ID:18253 Verilog HDL warning at <location>: port "<string>" remains unconnected for this instance
ID:18254 Verilog HDL warning at <location>: "<string>" is synthesized as "<string>": might cause synthesis - simulation differences
ID:18257 Input port "<name>" is not connected on this instance at <location>
ID:18258 Fitter Physical Synthesis operations beginning
ID:18259 Fitter Physical Synthesis operations ending: elapsed time is <time>
ID:18260 Verilog HDL warning at <location>: using initial value of <string> since it is never assigned another value
ID:18261 VHDL Variable Declaration warning at <location>: used initial value expression "<string>" for variable "<name>" because variable was never assigned a value
ID:18262 RX channel < <name> > requires an associated reference clock pin. Connect a reference clock pin to the RX channel.
ID:18263 Cell named <name> with ID <id> has no legal locations.
ID:18265 Can't connect to the Intel FPGA website. Verify that you have an active internet connection.
ID:18266 Signal "<src>" drives multiple clock buffers.
ID:18267 Clock buffer node "<node>"
ID:18268 Placed (but not routed) <number> of <number> core register(s)
ID:18269 Placed and routed <number> of <number> core register(s)
ID:18270 No core registers were placed or routed
ID:18271 Part name <name> is illegal
ID:18273 No valid snapshot available. Please run compilation prior to launching the Technology Map Viewer.
ID:18275 Create revision with copy results option is not supported in Quartus Prime Pro Edition (PE) software
ID:18276 The fitter will not perform Hyper Aware Register Chain Optimization because hold timing optimization has been disabled.
ID:18277 GPIO pin <name> has illegal OCT setting: "<value>"
ID:18278 Illegal parameter value: Cannot select Aynchronus and Synchronous clear signal simultaneouly
ID:18279 Clock Enable Block "<name>" has port ena that should not be connected when parameter ena_register_mode is set to "<value>". The input will be ignored.
ID:18280 I/O pin <name> has a VREF setting assigned to it but does not drive an I/O lane. Remove the VREF setting for the I/O Pin
ID:18282 Block "<name>" is constrained to the region with lower-left corner "<location>" and upper-right corner "<location>" which overlaps with reserved Logic Lock Region "<name>" with lower-left corner "<location>" and upper-right corner "<location>"
ID:18283 Platform Designer is not installed or could not be found
ID:18284 Platform Designer (<text>) failed to launch
ID:18285 File extension (<name>) is not supported by Platform Designer
ID:18286 Platform Designer file (<file name>) cannot be created
ID:18287 WYSIWYG RAM primitive "<name>" in operation mode "<name>" uses an unsupported value for parameter "<name>"
ID:18288 Block "<name>" is constrained to the region with lower-left corner "<location>" and upper-right corner "<location>" but also is a member of a Logic Lock Region which does nto overlap: Logic Lock Region "<name>" with lower-left corner "<location>" and upper-right corner "<location>"
ID:18289 Started post-fitting delay annotation
ID:18290 Delay annotation completed successfully
ID:18291 Timing characteristics of device <name> are preliminary
ID:18292 Advance timing characteristics for device <name>. Delays will change in future releases.
ID:18293 This speed grade (or min_timing) is not available in the current device.
ID:18299 Expanding entity and wildcard assignments.
ID:18300 Expanded entity and wildcard assignments. Elapsed time: <elapsed_time>
ID:18301 Oscillators <name> and <name> have different signal sources on their OSCENA ports
ID:18302 Generic PLL detected: <name>. Use of generic PLLs is illegal for the current part.
ID:18303 Name "<name>" is illegal. Avoid using '*', ':' and '|' in your naming scheme because these characters have special meaning in Quartus.
ID:18305 DSP block WYSIWYG primitive "<atom name>" cannot perform a subtraction operation with unsigned operands. Make sure ports SUB and NEGATE are disconnected or grounded, or make sure all operands are set to using signed representation.
ID:18307 Platform Designer (<text>) failed to launch
ID:18308 File extension (<name>) is not supported by Platform Designer.
ID:18309 Platform Designer file (<file name>) cannot be created
ID:18310 Platform Designer is not installed or could not be found
ID:18311 The bottom multiplier cannot be used for a single multiply operation for the DSP block WYSIWYG primitive "<atom name>". The top multiplier should be used instead. Make sure the input and output ports for the bottom multiplier are disconnected.
ID:18312 In order to use port RESULTB from the bottom multiplier for DSP block WYSIWYG primitive "<atom name>", ports BY and BX or COEFSELB must be connected.
ID:18313 The width of port <port name> for DSP block WYSIWYG primitive "<atom name>" should be <number> bits when the operation mode is set to "<systolic operation mode>". A DSP in systolic mode can only connect to/from another DSP in systolic mode.
ID:18314 I/O pin <name> is driving a ref clock and has a pseudo-differential I/O standard. Try setting the I/O standard to a true differential I/O Standard
ID:18315 WYSIWYG ClockLock PLL primitives (<name>) are not supported in Quartus Prime Pro Edition Design Software, instantiate WYSIWYG PLL's instead.
ID:18316 Cannot find the port "<port>" in the Intel FPGA IP Evaluation Mode entity "<entity>". Intel FPGA IP Evaluation Mode specification file is invalid.
ID:18320 Bidirectional port "<name>" directly or indirectly feeds itself.
ID:18321 Bidirectional ports "<name>" and "<name>" directly or indirectly feed each other.
ID:18322 Launching the gate level functional simulation although timing simulation option is chosen.
ID:18323 The top-level entity cannot be an Intel FPGA IP Evaluation Mode entity.
ID:18324 File extension .<name> is only supported in the Quartus Pro.
ID:18326 The design pin '<name>' has been assigned to CLKUSR pin location '<name>'. Quartus Prime auto-reserves the CLKUSR pin for calibration of transceivers and certain IOs. If the pin '<name>' will not be assigned a 100-125MHz clock, you must remove the location assignment on it. Otherwise, to remove the critical warning use the QSF assignment 'set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF'.
ID:18327 Illegal IOPLL WYSIWYG found: <name>. No raw user-instantiated IOPLL WYSIWYGs are allowed for the current part.
ID:18330 Metastability: Ignoring Synchronizer Identification setting Off, and using Auto instead.
ID:18375 Platform Designer is not installed or could not be found
ID:18376 Platform Designer (<text>) failed to launch
ID:18377 File extension (<name>) is not supported by Platform Designer
ID:18378 File '<file name>' already exists. Do you want to overwrite the existing file?
ID:18379 Qsys file (<file name>) cannot be created
ID:18380 Platform Designer is not installed or could not be found
ID:18381 Platform Designer tool (<text>) failed to launch
ID:18382 File extension (<name>) is not supported by Platform Designer
ID:18383 File extension .<name> is only supported in the Quartus Pro.
ID:18384 Platform Designer file (<file name>) cannot be created
ID:18385 Programming Object File contains dual images, with different JTAG user codes 0x<number> and 0x<number>. If you require a common JTAG user code for both images, change the JTAG user code in the General tab of the Device and Pin Options dialog box.
ID:18386 <Source of the clock signal> (<fanout> fanout) drives <clock sectors driven>
ID:18387 Failed to read POF ID in device <number>.
ID:18389 Can't read Intel FPGA IP Evaluation Mode specification file -- "<reason>"
ID:18390 Intel FPGA IP Evaluation Mode (Simulation-Only) feature is turned on for all cores in the design
ID:18391 Intel FPGA IP Evaluation Mode feature is turned on for the following cores
ID:18392 "<name>" will use the Intel FPGA IP Evaluation Mode feature
ID:18393 Intel FPGA IP Evaluation Mode feature will not be used - <text>
ID:18394 Some cores in this design do not support the Intel FPGA IP Evaluation Mode feature
ID:18395 "<name>" does not support the Intel FPGA IP Evaluation Mode feature
ID:18396 EDA simulation disabled for this design
ID:18397 "<name>" cannot be simulated with Intel FPGA IP Evaluation Mode (Simulation-Only).
ID:18399 Block '<string>' has -from block '<string>' and this -from block is not recognized as a MACRO_HEAD
ID:18400 Block '<string>' is a MACRO_HEAD
ID:18401 Port <port> must be used when parameter <parameter> is set to <parameter_value>
ID:18404 Intel recommends removing all location assignments when changing the board. Do you want to remove all location assignments?
ID:18407 Cannot adjust delay of type <type> because the desired setting <setting> is out of range. Ignoring the setting.
ID:18408 Finished recentering delays based on driver margining results.
ID:18409 Parameter <parameter1> can only be set to <parameter2_value> when parameter <parameter2> is set to <parameter2_value>
ID:18410 WYSIWYG RAM primitive "<name>" "<name>" port is not connected
ID:18411 One or more registers failed to be packed into a DSP bank due to conflicting use of synchronous and asynchronous clears
ID:18412 The <part_name> device is sensitive to electrical glitches. Refer to the guidelines for Clock and Data Input Signal For MAX10 E144 Package in the Signal Integrity Design Guidelines in the MAX10 device documentation.
ID:18414 Only the the pin_device back annotation mode is supported in the Quartus Prime Pro Edition (PE) software
ID:18415 The memory connected to the In-System Memory Content Editor instance is in use.
ID:18416 The memory connected to the In-System Memory Content Editor instance is in use. Performed <num_writes> writes successfully.
ID:18419 The Hyper-Retimer is not supported for device <name>. This feature is only available for device families with HyperFlex architectures.
ID:18421 WYSIWYG RAM Primitive "<name>" mixed port read during write cannot set "<name>" in this operation mode.
ID:18422 WYSIWYG LCELL COMB primitive "<name>" cannot use the CARRY_IN, DATA_G or DATA_H ports when in normal LUT mode
ID:18423 WYSIWYG LCELL COMB primitive "<name>" must use the DATA_H port when in extended LUT mode
ID:18424 WYSIWYG LCELL COMB primitive "<name>" cannot use the DATA_E, DATA_F, DATA_G, DATA_H or COMB_OUT ports when in arithmetic LUT mode
ID:18425 Verilog HDL warning at <location>: assignment to const variable <string>
ID:18426 Verilog HDL warning at <location>: assignment pattern is invalid for use with <string> port <string>
ID:18427 Verilog HDL warning at <location>: ref type port <string> cannot be left unconnected
ID:18428 Verilog HDL error at <location>: type <string> is used before its declaration
ID:18429 Verilog HDL error at <location>: checker port must not specify any direction in SystemVerilog 1800-2009 dialect
ID:18430 Verilog HDL error at <location>: keyword local is not allowed in checker port declaration
ID:18431 Verilog HDL error at <location>: invalid direction in checker port, use input or output
ID:18432 Verilog HDL error at <location>: body of extern method <string> is never defined
ID:18433 Verilog HDL warning at <location>: only nonvoid DPI function can be specified as pure
ID:18434 Verilog HDL warning at <location>: output/inout argument cannot be specified in pure DPI function
ID:18435 Verilog HDL warning at <location>: target of assignment pattern cannot be enumeration type
ID:18436 Verilog HDL error at <location>: dynamic types are not allowed in non-tagged unions
ID:18437 Verilog HDL info at <location>: previous definition of module <string> is here
ID:18438 Verilog HDL warning at <location>: result of this <string> operation does not fit in <number> bits
ID:18439 Verilog HDL error at <location>: cannot variable index values having different length
ID:18440 Verilog HDL error at <location>: invalid argument for unique constraint
ID:18441 Verilog HDL error at <location>: randc variables cannot be used in <string> constraint
ID:18442 Verilog HDL error at <location>: invalid non-integral expression in unique constraint
ID:18443 Verilog HDL warning at <location>: parameter <string> with unpacked dimension should have a data type
ID:18444 Verilog HDL error at <location>: local parameter declared in a configuration must be assigned a literal value
ID:18445 Verilog HDL error at <location>: invalid argument in <string>, required <string>
ID:18446 Verilog HDL error at <location>: duplicate class item qualifier <string>
ID:18447 Verilog HDL error at <location>: conflicting class item qualifiers, <string> and <string>
ID:18448 Verilog HDL error at <location>: direction of formal <string> in extern method <string> does not match prototype
ID:18449 Verilog HDL error at <location>: non-printable character 0x<number> in escaped identifier
ID:18450 Verilog HDL error at <location>: export/import task/function is not supported for synthesis
ID:18451 Verilog HDL error at <location>: invalid reference to $unit::<string> from package
ID:18452 Verilog HDL warning at <location>: instance <string> should start with one of the specified designs
ID:18453 Verilog HDL error at <location>: explicitly declared port <string> cannot be redeclared
ID:18454 Verilog HDL warning at <location>: data object <string> is already declared
ID:18455 Verilog HDL warning at <location>: module <string> is previously defined, ignoring this definition
ID:18456 Verilog HDL warning at <location>: automatic variable is not allowed in <string>
ID:18457 Verilog HDL warning at <location>: extra semicolon in $unit (global) scope
ID:18458 Verilog HDL warning at <location>: non-constant initial value of non-net output port <string> is not allowed
ID:18459 Verilog HDL error at <location>: select condition can only be used in bin selection
ID:18460 Verilog HDL error at <location>: virtual method <string> in superclass cannot be overridden by a static method in subclass
ID:18461 Verilog HDL error at <location>: non-static variable <string> cannot be used in initial expression for static variable <string>
ID:18462 Verilog HDL error at <location>: clocking block input signal <string> cannot be driven
ID:18463 Verilog HDL error at <location>: clocking block output signal <string> cannot be read
ID:18464 Verilog HDL error at <location>: <string> argument <string> in covergroup <string> is not allowed
ID:18465 Verilog HDL error at <location>: covergroup formal argument <string> cannot be accessed outside the covergroup <string>
ID:18466 Verilog HDL warning at <location>: specify block ignored for synthesis
ID:18467 Verilog HDL warning at <location>: checker body cannot have always construct
ID:18468 Verilog HDL warning at <location>: checker port having direction must specify a data type
ID:18469 Verilog HDL error at <location>: checker body cannot have always_ff/always_comb/always_latch/final construct in SystemVerilog 1800-2009 dialect
ID:18470 Verilog HDL error at <location>: invalid value for ref formal, value must be assignable
ID:18471 Verilog HDL warning at <location>: synthesis of <string> is not supported
ID:18472 Verilog HDL error at <location>: hierarchical reference to let declaration <string> is invalid
ID:18473 Verilog HDL error at <location>: return type of function <string> needs to use class resolution operator to indicate internal type <string>
ID:18474 Verilog HDL error at <location>: invalid class resolution operator for parameterized class <string>, expected explicit specialization form
ID:18475 Verilog HDL warning at <location>: unspecialized class resolution operator for parameterized class <string> to access <string>, expected explicit specialization form
ID:18476 Verilog HDL error at <location>: type parameter is not allowed inside checker
ID:18477 Verilog HDL error at <location>: parameter declaration inside checker violates IEEE 1800 syntax
ID:18478 Verilog HDL error at <location>: checker parameter cannot be overridden using defparam
ID:18479 Verilog HDL warning at <location>: empty parameter declaration is only allowed in SystemVerilog mode
ID:18480 Verilog HDL warning at <location>: multi-assignment pattern with zero or negative multiplier
ID:18481 Verilog HDL error at <location>: this or another usage of <string>.<string> inconsistent with <string> object
ID:18482 Verilog HDL info at <location>: using <number> instead of <string>
ID:18483 Verilog HDL error at <location>: sequential udp with edge sensitive set/reset is not supported for synthesis
ID:18484 Verilog HDL error at <location>: invalid expression for ref type port <string>
ID:18485 Verilog HDL error at <location>: parameter <string> has no actual or default value, cannot be used inside instantiated module <string>
ID:18486 VHDL warning at <location>: actual values for generic <string> do not match between package instantiation and interface package
ID:18487 VHDL error at <location>: external name cannot denote object <string> in process <string>
ID:18488 VHDL error at <location>: source of subprogram instantiation is ambiguous
ID:18489 VHDL error at <location>: generic <string> has no actual or default value, cannot be used inside instantiated entity <string>
ID:18490 The width and height of a Logic Lock region must be within the device dimension of <nx> x <ny>.
ID:18492 Illegal programming mode specified for Partial Reconfiguration. Specify JTAG mode for Partial Reconfiguration.
ID:18494 Can't launch web browser
ID:18497 <# of directly competing signals> signal<(s)> <is/are> using the routing resource<(s)> that the unroutable signal can access (direct congestion):
ID:18498 <# of indirectly competing signals> other signal<(s)> prevent<(s)> the above competing signal<(s)> from being re-routed (indirect congestion):
ID:18499 FPLL < <name> > are too close to ATX PLL < <name> >. FPLL with VCO frequencies within 50 MHz of adjacent ATX PLL must be separated by one FPLL. Modify the FPLL location constraints in the Assignment Editor to make FPLLs at least one ATX PLL apart.
ID:18500 The <assignment_type> assignment in the current design does not match the base design (assignment in current design <current_design_assignment_status>, assignment in base design <base_design_assignment_status>).
ID:18501 The current device ("<current_design_device>") does not match the device used in the base design ("<base_design_device>").
ID:18502 The <assignment_type> assignment in the current design does not match the base design (assignment in current design <current_design_assignment_status>, assignment in base design <base_design_assignment_status>). Check that the assignment in the current design is correct.
ID:18503 The selected board's design has been created and stored in <path>.
ID:18504 Error writing Interface Planner floorplan file.
ID:18505 Successfully wrote <filename> Interface Planner floorplan file
ID:18506 You must resolve all configuration pin with AUTO pin selection first.
ID:18509 You have set two or more configuration share the same pin. Please make sure each configuration is using a different pin.
ID:18510 PIPE master channel < <name> > cannot be placed at the HIP channel location < <name> > due to timing requirement. Either change the master channel to a different index to avoid HIP channel locations, or change master channel location to avoid HIP channel locations, or change speed grade to 1.
ID:18513 Child partition "<child_partition>" does not implement output signal "<port_name>" which is required by parent partition "<partition_name>". Modify either the child or parent partitions so that all expected signals are correctly driven from the child partition.
ID:18514 Child partition "<partition_name>" expects its parent to drive input port "<port_name>", but this port is not driven from its parent partition "<driving_netlist>". Modify either the child or parent partitions so that all expected signals are correctly driven from the parent partition.
ID:18515 Attempted to route one dedicated refclk pin, <Dedicated refclk name>, to <Number of IOPLL locations> IOPLLs. In order to feed multiple IOPLLs, this signal must be promoted to a global clock.
ID:18516 Error loading Interface Planner floorplan file.
ID:18517 Successfully loaded <filename> Interface Planner floorplan file
ID:18518 WYSIWYG LCELL COMB primitive "<name>" cannot use the CARRY_IN port when in extended LUT mode
ID:18519 WYSIWYG FF primitive "<name>" cannot use the SCLR1 port
ID:18520 I/O "<name>" uses both input and output termination, but does not have dynamicterminationcontrol connected
ID:18525 Output pin "<name>" is in the dedicated HPS EMIF IO Bank and it will not work. Only HPS EMIF pins or GPIO output pins can be placed on this location. Please place this output pin in a different location.
ID:18527 Perform normal compilation and Fast Forward before opening the Fast Forward Viewer.
ID:18528 Can't open Fast Forward Viewer -- Fast Forward netlist not available
ID:18530 Can't configure device. Expected JTAG ID code 0x<name> for device <name>, but found JTAG ID code 0x<name>. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf).
ID:18531 The <port name> port for DSP block WYSIWYG primitive "<atom name>" should be GND when none of the <input/output/pipeline> registers are enabled. Make sure that the specified registers are enabled or connect the violating port to GND.
ID:18532 Using programming file <name> for device <name>@<number>
ID:18533 Cannot apply placement to existing Interface Planner plan.
ID:18534 At least one fuse must be selected. Please Specify the fuse name in <name>.
ID:18537 Intel Quartus Prime attempted to access a project in a directory path that could cause database files to exceed the maximum file length for the operating system. To resolve this issue, move the project to a directory closer to a root drive. The following path to the project's /qdb directory has <length> characters, but only <maxlength> characters are allowed: "<filename>".
ID:18538 Invalid width combination for mixed width dcfifo. The valid width ratio for mixed width dcfifo are 1, 2, 4, 8, 16 and 32 when device family is set to Stratix 10.
ID:18539 Path name is too long -- must be shorter than "<max length>" characters. Path (length <path length>): <path>
ID:18541 The root partition cannot be exported by itself. Export the entire design using design::export_design, or use --export_pr_static_block to export all static blocks excluding partial reconfiguration partitions.
ID:18542 The base revision MSF file must be specified for preserved partial reconfiguration partition <name>
ID:18543 The base revision SOF file must be specified for preserved logic <name> in partial reconfiguration design
ID:18545 <parameter> parameter is not set, using the default value <parameter>. This value is not compatible when operation_mode is set to <parameter> for device family <device>
ID:18546 <parameter> parameter is not set, using the default value <parameter>. This value is not compatible when operation_mode is set to <parameter> for device family <device>
ID:18547 The routing regions of partial reconfiguration or Reserved Core partitions "<First partial reconfiguration partition>" and "<Second partial reconfiguration partition>" overlap. The overlapping region is <Overlapping region>.
ID:18549 The following partial reconfiguration or Reserved Core partitions contain periphery IP: <failed_partitions>. Modify your design to ensure that no partial reconfiguration or Reserved Core partitions contain periphery logic. Specifically, the periphery IP instances listed below cannot be in any partial reconfiguration or Reserved Core partitions (only the first <max_shown> are shown):
ID:18550 Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example.
ID:18551 Cannot import revision (<revision name>) because a revision with the same name exists in the current project. Specify the --overwrite option to overwrite the existing revision databases.
ID:18552 The instance hierarchy "<name>" specified in the PARTIAL_RECONFIGURATION assignment cannot be found. Specify a valid name that refers to an instance hierarchy.
ID:18553 Requested global signal at "<src>" will route locally to <num> destination(s). Example(s) listed below:
ID:18554 Node "<src>.<port>" will be routed locally because it is not a valid global destination.
ID:18555 Destinations of this type cannot use global routing in a partial reconfiguration or Reserved Core region.
ID:18556 Read-only destination "<src>.<port>" was not flagged as a global destination in a previous compile but is driven by a clock buffer.
ID:18557 Region has no routing region that expand across the whole chip. Setting the Whole-Chip Routing Region to YES will create a routing region that expand across the whole chip.
ID:18558 Region has routing region that expand across the whole chip. Setting the Whole-Chip Routing Region to NO will reset the routing region to its region size.
ID:18559 IOPLL Reference Clock is driven by a source from a different partition. The Reference Clock must be driven from a source in the same partition.
ID:18560 IOPLL "<PLL name>" REFCLK input is driven by: "<Source name>"
ID:18561 The Fitter failed to successfully place Hyper-Registers along a path.
ID:18562 HPS DDR conduit is enabled but the HPS EMIF is not placed in IO bank 2K.
ID:18564 No partitions are available for export.
ID:18565 The SEU sensitivity map (.smh) file for the device cannot support more than <number> groupings for <number> ASD regions in the design. No SMH file will be generated for the design.
ID:18567 Global net "<name>" has multiple drivers
ID:18568 Output port "<port>" in partition "<partition>" was implemented as a device I/O in an earlier compile, but is now being used to drive other logic. Output ports that have previously be implemented as device I/O may only be used as device I/O in future compiles.
ID:18569 Input port "<port>" in partition "<partition>" was implemented as a device I/O in an earlier compile, but is now being driven by logic. Input ports that have previously be implemented as device I/O may only be used as device I/O in future compiles.
ID:18571 The assignment of type "<assignment_type>" has now been deprecated in this version of Quartus Prime Pro Edition.
ID:18572 The operation is invalid because the resulting origin and/or size is illegal.
ID:18573 Partial reconfiguration region verification will be skipped for <name> partition by user request
ID:18575 Timing Analysis mode is specified for importing design. Programming file generation is disabled.
ID:18576 The transceivers with supply "<name>" on the <name> HSSI strip use "<name>". The default voltage for unused HSSI channel(s) has been overridden by "<name>".
ID:18578 Generation of timing simulation data is not currently supported for the <name> device family.
ID:18579 Cannot generate netlist output files because the design includes encrypted source files: "<name>"
ID:18580 Cannot generate netlist output files because the design includes encrypted source files: "<name>"
ID:18583 Export design requires at least a successful synthesis.
ID:18584 There are no transceiver channels used in the design. You must use or instantiate at least 1 transceiver channel to preserve the rest of the unused channels.
ID:18585 The Exported Partition File (.qxp) cannot be opened in Quartus Prime Pro Edition.
ID:18588 "<Region target>" is constrained to the <placement/routing> region <Region bounding box(es)> that is outside the chip bounds of <Chip bounding box>
ID:18590 The imported netlist contains settings that are not supported by the current version of the software. Import using the --timing_analysis_mode option, which ignores the errors and allows Timing Analysis to be run.
ID:18591 Cannot recognize the flash device attached to device <number>. The flash device is not supported by the Intel Quartus Prime software.
ID:18592 The current device (<device>) does not support exporting to a version compatible format.
ID:18597 Missing design revision from import
ID:18598 Multiple design revisions found from import
ID:18600 Can't import design file with no snapshot
ID:18601 Can't import design file with multiple snapshots
ID:18602 Found invalid snapshot '<snapshot_name>' from import design file
ID:18604 A PR region's MSF is expected, but a static region's MSF (<name>) is given.
ID:18605 The <name> device family is not supported by altaccumulate.
ID:18610 The ordered port connection is not supported for the Partition Database File (.qdb) sourced instance <name>
ID:18612 READDATAVALID signal for secondary memory controller's Avalon Memory Mapped bus is not connected for memory interface IP "<IP instance name>". Connect this port to an FPGA core signal.
ID:18613 VSBLOCK "<name>" output datatout[<number>] has fanout. Only data from dataout[11:6] should be used
ID:18615 The current device (<device>) does not support partial reconfiguration.
ID:18616 <requested> requested global clocks exceeds maximum of <available>
ID:18617 The given snapshot '<snapshot_name>' is not supported for version-compatible export. Refer to the argument help menu for supported snapshots.
ID:18618 The given snapshot '<snapshot_name>' is not compiled successfully or is missing. Re-compile your design before export.
ID:18620 TX channel adapter <name> in double data rate transfer mode feeding a 20-bit serializer and with its byte serializer disabled must have its <name> input (tx_coreclkin) fed by an fPLL
ID:18621 WYSIWYG RAM Primitive "<name>" mixed port read during write cannot set "<name>" when enable_coherent_read is true.
ID:18623 Partition "<parent_partition_name>" feeds signal "<driving_signal>" but this signal is ignored by child partition "<partition_name>". Consider modifying your design so that the child partition implements all input ports that are driven by the parent partition.
ID:18624 Partition "<partition_name>" contains output port "<port_name>" that is ignored by its parent partition "<driving_netlist>". Consider modifying your design so that all output ports are connected to their parent partitions.
ID:18625 The archive "<archive>" does not contain a valid block for import.
ID:18626 Assembler cannot use a netlist that has been imported using timing_analysis_mode. Recompile the design before running the Assembler (quartus_asm)
ID:18629 Export design and export partition are not allowed for a netlist that has been imported using timing_analysis_mode. Run full compile before export design or export partition(quartus_cdb).
ID:18630 This congestion may be avoided by moving or disabling promotion of any of the following competing signals:
ID:18631 Reconfigurable or reserved core partition '<string>' has an output '<string>' which is driven by global source '<string>,' but signals from reconfigurable or reserved core partitions may not drive the global networks, even if the original source of the signal is not in the partition. Modify your design to feed the global destinations from outside the partition, or disable global promotion for this signal.
ID:18633 The Quartus Database File "<archive>" contains a full design and cannot be imported with the import_block command, or as a QDB File Partition assignment.
ID:18634 Failed to restore Partition Database File '<qdb_filename>'.
ID:18636 Compilation Report contains advance information. Specifications for device <name> are subject to change. Contact Intel for information on availability. No programming file will be generated.
ID:18637 Rapid Recompile is not supported for the currently selected device family in the Quartus Prime Standard Edition Software.
ID:18639 Skipping database version check for import of database files from '<db_vesion>'. The imported database might be incompatible with current version of the software.
ID:18640 The Quartus Partition Database File '<qdb_file>' was generated using version '<db_version>', which cannot be read by the current version of the Quartus Prime software. Regenerate '<qdb_file>' using the current version of the Quartus Prime Software.
ID:18641 The database files cannot be read with the current version of the Quartus Prime software. The Quartus Prime software can only read files created by the last 3 major Quartus Prime releases.
ID:18642 Cannot import version-compatible database files from future versions of the Quartus Prime software.
ID:18644 Cannot generate simulator setup script for IP because the revision name does not match the project name.
ID:18645 There are multiple Partial Reconfiguration regions occupying the same <name> regions. This feature is not supported in this version of Quartus Prime. The following regions are affected:
ID:18650 Failed to open project "<proj name>", revision "<revision name>".
ID:18654 Preserved <number> unused TX channel(s).
ID:18656 RZQ pin "<name>" connects to multiple OCT blocks in user-mode. Merging user-mode OCT is not supported.
ID:18657 RZQ pin "<name>" connects "<name>" OCT block.
ID:18659 The block '<block_name>' must have PR sub-partitions to be exported with the exclude_pr_subblocks option.
ID:18660 Partition assignment <name> doesn't match any hierarchical instance in the design.
ID:18665 IOPLL < <name> > is used as cascade input of FPLL < <name> >. Intel does not recommend using this cascade path.
ID:18667 Ignored Maximum Fan-Out logic option for node "<name>" in PR region
ID:18668 The parameter "<parameter value>" of DSP block WYSIWYG primitive "<atom name>" should be set to "NONE" when port <port name> is a constant value or disconnected.
ID:18670 Cannot insert clock buffer at "<src>" due to partition boundary violations
ID:18672 Downstream boundary port "<bp>" drives both global and non-global destinations
ID:18673 Source drives other mandatory global destinations not downstream of this boundary port
ID:18674 Destination "<dest>" requires <type> routing
ID:18675 Potential resolution(s):
ID:18676 Duplicate the boundary port and rewire destinations such that each port has only all global or all non-global fanout
ID:18677 Ensure that all destinations downstream of the boundary port have the same global setting
ID:18678 For the affected port, ensure that only downstream nodes require global routing (i.e. no other nodes driven by the source node require a clock buffer)
ID:18679 Manually instantiate a clock buffer driven by the boundary port and another clock buffer at the source node to drive only their respective global destinations
ID:18680 Example node(s):
ID:18681 And <num> other nodes(s) not reported
ID:18686 Cannot use global routing because source is in a partial reconfiguration or Reserved Core region.
ID:18687 The QSF assignment ENABLE_UNUSED_RX_CLOCK_WORKAROUND has been deprecated. It has been superseded by the QSF assignment PRESERVE_UNUSED_XCVR_CHANNEL.
ID:18688 The currently selected device family does not support Rapid Recompile.
ID:18690 The default IO Standard "<assignments>" is no longer valid. The default IO Standard has been updated to "<assignments>".
ID:18691 Generated the EDA functional simulation netlist because it is the only supported netlist type for this device.
ID:18694 The reference clock on PLL "<name>", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.
ID:18695 Could not find a legal chained placement.
ID:18700 The status of CONF_DONE is required for PFL and/or other interfaces used in the device configuration.
ID:18701 Skipped board timing files generation because it is not supported for this device.
ID:18703 ATX PLL or fPLL < <name> > is configured for the OTN or SDI protocol and is not placed in the same bank as its reference clock source.
ID:18707 The Power On Reset scheme value has been changed to "Instant ON", because the previous setting "<name>" is not supported by Max 10 device.
ID:18708 ATX/FPLL < <name> > is not placed in the same bank as the reference clock.
ID:18709 Fitter Physical Synthesis has detected a Partial Reconfiguration or Reserved Core partition in the design. The registers inside this region or partition will not be retimed.
ID:18710 DSP block WYSIWYG primitive "<atom name>" has internal use-only port <port name> connected. Please disconnect this port.
ID:18711 The design ATX PLL < <name> > is configured as a cascade source and uses tank 0 setting. Tank 0 is not a supported setting when the ATX PLL is configured as a cascade source.
ID:18713 <msg>. Refer to --help for more information
ID:18719 RESERVE_PR_PINS QSF assignment and ENABLE_PR_PINS QSF assignment are both enabled.
ID:18723 Custom routing file <name> is malformed: <message>
ID:18724 Cannot open custom routing file <name>
ID:18726 Duplicate parent found for location with ID <id> of type <type>.
ID:18727 Bank location <name> with ID <id> is missing a GID.
ID:18728 The following DSP nodes form a DSP chain that requires <number> contiguous DSP locations. These DSP nodes are constrained to the Logic Lock region <name>, where the longest contiguous group of DSP locations has length <number>.
ID:18729 The following DSP nodes form a chain of length <number>, however these DSP blocks are constrained to more than one Logic Lock region.
ID:18730 The following DSP nodes require <number> DSP locations, but they are all confined to Logic Lock region <name> which only contains <number> DSP locations.
ID:18732 Since "<Command name> -blackbox" command was used, the partition boundary port <Port name> is considered an endpoint for timing paths.
ID:18734 Target Node: <Port Found> is not a partition boundary port, but the -blackbox option was used.
ID:18735 The <Wrong command that was used> command should not be used on an <Port direction of the target boundary port> boundary port of a partition. You can use <Correct command to be used> instead.
ID:18737 Search result for "<find_string>" :
ID:18738 <file_path_name>
ID:18739 <found_line>
ID:18740 <string_report>
ID:18741 No flow template <flow name> could be found. Check the spelling of the flow name and the flow search paths.
ID:18742 An error occurred while attempting to copy flow template <flow name>. Verify the destination file name is valid and the filesystem is writeable.
ID:18743 Successfully wrote flow template <source name> to <dest name>
ID:18744 RZQ_GROUP name "<name>" is invalid
ID:18745 Found multiple flow templates named <flow name>, Ignoring template in <flow path>
ID:18746 Cannot write flow template to directory named <flow path>. Directory exists.
ID:18747 Starting Fast Forward Timing Closure Recommendations analysis.
ID:18748 Completed Fast Forward Timing Closure Recommendations analysis.
ID:18749 Input termination value "<name>" for pad "<name>" is not supported
ID:18750 The Allow Register Merging assignment setting is not available for the targeted device family, and will be ignored.
ID:18751 The Allow Register Duplication assignment setting is not available for the targeted device family, and will be ignored.
ID:18752 Hyper-Retimer failed to place the register <text> at the assigned Hyper-Register location constraint.
ID:18753 Bank location <name1> with ID <id1> (<bbox1>) overlaps with bank location <name2> with ID <id2> (<bbox2>).
ID:18754 There are multiple <sdc_or_tcl> files with the name "<filename>" with differing content in the design. Change your design so that all <sdc_or_tcl> files with the same filename have the same content.
ID:18756 Can't find any boundary ports.
ID:18758 The <sdc_or_tcl> file "<path>" differs from the one stored in the database. It has been copied into the database and re-read.
ID:18759 Failed to copy <sdc_or_tcl> file into the database. File copy from "<src>" to "<dst>" was unsuccessful.
ID:18773 Region is invalid due to overuse of core resources or does not intersect with one or more coupled clocks
ID:18774 Fast Forward Timing Closure Recommendations is not supported for device <name>. This feature is only available for device families with HyperFlex architectures.
ID:18775 Signal "<name>" with routing constraints on line <number> of the routing constraints file (RCF) already has constraints from a previous compile or internal routing requirements and cannot be constrained in an RCF. The RCF for this signal will be ignored
ID:18776 The current design uses hierarchical partial reconfiguration, but hierarchical partial reconfiguration is not supported in the current version of the Quartus Prime Pro Software.
ID:18777 Partition "<partition_name>" is a partial reconfiguration partition.
ID:18778 Partition "<partition_name>" is a hierarchical partial reconfiguration partition.
ID:18779 Contradicting pin assignments found for the HPS dedicated pins. The HPS IP component placed the HPS pin <name> at location <name>, but in the top level assignments, the pin is located at <name>
ID:18780 The Dedicated HPS Pin <name> Does not have proper location assignment Generated by HPS IP component in Platform Designer.
ID:18781 Deterministic overuse of <type> resources in region <region>
ID:18782 ATX PLLs <name> and <name> are <number> ATX PLLs apart. For two ATX PLLs providing the serial clock for PCIe/PIPE Gen3, they must be placed <number> ATX PLL apart (skip <number>).
ID:18783 Port "<name>" does not exist in the current RTL design or the stub file but exists in the snapshot from the provided Partition Database File (.qdb).
ID:18784 Ignore the duplicated QDB file assignment for "<name>" because it already exists.
ID:18786 There is an unused QDB file assignment for <name>.qdb.
ID:18790 WYSIWYG primitive "<lutram name>" and WYSIWYG primitive "<reg name>" are connected to different write clock source. Port Clear is configured as sclear input must be connected to a Hyperflex register with same write clock source.
ID:18791 WYSIWYG primitive "<lutram name>" and WYSIWYG primitive "<reg name>" are connected to different write clock source. Port Clock Enable 1 input must be connected to a Hyperflex register with same write clock source.
ID:18792 WYSIWYG primitive "<lutram name>" and WYSIWYG primitive "<reg name>" are connected to different read and write clock sources. Port Clear is configured as sclear input when connected to a Hyperflex register must be connected with same clock source.
ID:18793 WYSIWYG primitive "<lutram name>" and WYSIWYG primitive "<reg name>" are connected to different read and write clock sources. Port Clock Enable 1 input when connected to a Hyperflex register must be connected with same clock source.
ID:18794 Reading SDC File: '<SDC File Name>' for instance: '<Instance Name>'
ID:18797 Use the context menu (right click) on the previous error message to locate the DSP block locations contained in Logic Lock region "<name>" in Chip Planner.
ID:18798 And <count> more similar nodes (full list omitted for brevity)
ID:18800 WYSIWYG LCELL primitive "<name>" cannot use the SHARE_IN/SHARE_OUT ports
ID:18801 Hard IP for PCI Express block "<name>" with Configuration via Protocol (CvP) enabled is assigned to pin "<name>", which is a non-CvP Hard IP for PCI Express location. Please change to a device with non-CvP Hard IP for PCI Express location.
ID:18803 Failed to use the selected key programming file. Found device database mismatch between key programming file and the target device
ID:18804 Failed to use the selected key programming file. Missing key information to generate encrypted bitstream for Partial Reconfiguration design
ID:18805 No dedicated path available for refclk signal, <Refclk name>. Please promote your refclk to a global clock or move it to a dedicated IOPLL refclk pin.
ID:18806 WYSIWYG primitive "<reg name>" connected to WYSIWYG primitive "<lutram name>" must be a simple Hyperflex-friendly register with only D, CLK, and Q port connected.
ID:18807 The Soft Ram Source Clock "<Soft Ram Source atom name>" has an illegal connection to an IO or a component outside the partition the IO AUX is in.
ID:18808 Unable to preserve hardened routing constraints from a previous compilation stage
ID:18811 Creating a clock is not allowed while reading an Entity SDC. Move the clock creation to the top-level SDC file.
ID:18812 Creating a generated clock is not allowed while reading an Entity SDC. Move the clock creation to the top-level SDC file.
ID:18813 Using <qdb_file>.qdb to replace the module <module_name>.
ID:18814 Parameter assignment "<parameter assignment>" is found with multiple values on "<atom name>". Using value "<current assignment value>" and ignoring "<new assignment value>".
ID:18816 Ignored invalid assignment setting "<parameter value>" for parameter "<parameter name>" found on "<atom name>". This setting is assigned through QSF assignment "<assignment name>".
ID:18817 Timing report command failed: Unable to find requested path(s) due to the -from/-through filters and the complexity of the design.
ID:18818 GPIO WYSIWYG instantiation <name> has specified bitpos <number> that exceeds maximal index <number>
ID:18820 Illegal partition name "<partition_name>".
ID:18821 Fitter Hyper-Retimer operations ending: elapsed time is <time>
ID:18822 Fitter post-routing fixup operations ending: elapsed time is <time>
ID:18824 Fitter is performing the Signal Tap Post-Fit tapping flow.
ID:18825 hdb source file has an entity assignment while compiling without Early Access.
ID:18826 Project name required.
ID:18827 Illegal project name "<name>".
ID:18828 Illegal top-level entity name "<name>".
ID:18830 Running Finalize on routed snapshot which had Hyper-Retimer enabled
ID:18831 Exporting version-compatible databases is not supported for partial reconfiguration or root partition reuse designs.
ID:18832 Skipping Fitter Hyper Aware optimizations and Hyper-Retiming optimizations. Fmax and area optimizations to take advantage of the HyperFlex architecture will be skipped.
ID:18836 Can't make hole to the selected assigned Logic Lock region. <reason>
ID:18837 Make hole to multiple assigned regions is prohibited.
ID:18838 You must perform Analysis and Synthesis before performing this operation
ID:18839 The Tamper Protection Mode fuse has been programmed. Skipping programming of this fuse for device <number>.
ID:18840 Port "<name>" exists in the current RTL design or the stub file but does not exist in the snapshot from the provided Partition Database File (.qdb).
ID:18841 The rst_n port on clock divider <node> should not be connected.
ID:18842 The <port> port on clock gate <node> is connected to a constant. It must be driven by a real signal.
ID:18843 The <port> port on clock divider <node> is disconnected.
ID:18844 The <port> port on clock gate <node> is disconnected.
ID:18845 Invalid node ID <node_id> passed to get_partition
ID:18846 The partial reconfigure feature is only supported for select Cyclone V and Cyclone V SoC devices. Contact your Altera sales representative for information on these devices and access to the partial reconfigure feature.
ID:18849 Running the Fitter on a partial reconfiguration design at the synthesis revision is illegal.
ID:18851 QDB_FILE assignment "<qdb_name>.qdb" matches top-entity name "<entity_name>". Rename your Partition Database File (.qdb) to "root_partition.qdb" to import the root partition.
ID:18852 Failed to reproduce prior preserved placement due to conflicts with hardened constraints
ID:18853 Running Synthesis on a partial reconfiguration design at the implementation revision is invalid.
ID:18855 Atom location conflict. Nodes "<atom_name_1>" and "<atom_name_2>" from partitions "<partition_name_1>" and "<partition_name_2>" are placed in the same location, <location>.
ID:18856 Are you sure that you want to delete the selected Logic Lock region(s)? You will not be able to undo the operation.
ID:18858 Skipping Fast Forward Timing Closure Recommendations analysis because retiming optimizations were disabled. Enable Fast Forward analysis turning on the 'Allow Register Retiming' setting and re-run the Quartus Fitter to fully take advantage of the HyperFlex architecture.
ID:18859 Glitch factor is specified, but the value is invalid. Specify a positive value for glitch factor in the glitch factor assignment.
ID:18860 Glitch factor is specified, but the value is less than '1.0'. This reduces the estimated power for the design.
ID:18861 "<reg name>" Hyperflex register is driving multiple destinations on "<lutram name>" LUTRAM cell's "<lutram port name>" port. Each Hyperflex register shall only connect to a LUTRAM cell's "<lutram port name>" port.
ID:18862 WYSIWYG RAM primitive "<name>" "<name>" and "<name>" must set to ena0 when clock enable 0 is used
ID:18863 When signal ENA0 connected in WYSIWYG RAM primitive "<name>" clk0_input_clock_enable and clk0_output_clock_enable cannot set to none.
ID:18864 ADVANCED_PHYSICAL_OPTIMIZATION must be enabled to run fitter in Pro Edition.
ID:18866 Clock <name> is constrained by a Clock Region assignment to coordinates <given_xy_bottom_left> and <given_xy_top_right>, which are not aligned to clock sector boundaries. To match the closest enclosing sector boundaries Quartus will instead use the coordinates <coord_boundaries>, or <sector_boundaries> in sector coordinates
ID:18867 Clock Region assignment for signal <name> is invalid: "<constraint>". Refer to the Information pane in the Assignment Editor for details on the legal syntax for this assignment. For this device, the maximum allowed sector coordinate is "<max_sector>"
ID:18868 Clock signal <name> was given conflicting Clock Region and Custom Clock Tree assignments: <cons1> and <cons2>
ID:18869 Performing metastability analysis with a pre-fit timing netlist. MTBF values for unplaced blocks are not available, and any reported MTBF values should be treated as an estimate.
ID:18870 Performing metastability analysis with a non-finalized snapshot. MTBF values for unplaced blocks are not available, and any reported MTBF values should be treated as an estimate.
ID:18871 Unable to change the Core-Only property for the Logic Lock region named "<name>" to <value>. <reason>
ID:18872 Unable to change the Routing Expansion property for the Logic Lock region named "<name>" to <value>. <reason>
ID:18873 Unable to change the Routing Region property for the Logic Lock region named "<name>" to <value>. <reason>
ID:18874 Unable to assign "<name>" to Logic Lock region "<name>". <reason>
ID:18875 Unable to remove "<name>" from Logic Lock region "<name>". <reason>
ID:18876 Unable to move the Logic Lock region named "<name>". <reason>
ID:18877 Unable to resize the Logic Lock region named "<name>". <reason>
ID:18878 Clock signal <name> was given an invalid CLOCK_SPINE assignment: <spine>. CLOCK_SPINE must have a value between 0 and <total_layers> inclusive.
ID:18879 SOF <name> for device <name> is not compiled with Early I/O Release option set
ID:18880 Generate combined bitstream. However SOF <name> for device <number> is compiled with Early I/O Release option set. Please use -hps option to generate split bitstream if desired
ID:18881 The fitter will not perform Hyper Aware Register Chain Optimization because the Hyper Retimer has been disabled and optimization depends on that feature.
ID:18882 Design requires <number> <type of ios> I/O pins -- too many to fit in the <number> <type of ios> I/O pin locations available in the selected device
ID:18883 Unable to load "<entity_name>" using QDB_FILE assignment "<qdb_name>.qdb".
ID:18885 Revision type is not specified in this Partial Reconfiguration design.
ID:18886 Assignment for partial reconfiguration partition is not found in the implementation revision.
ID:18887 Assignment for partial reconfiguration partition is not found in the base revision.
ID:18889 QDB_FILE assignment entity "<name>" has multiple instantiations.
ID:18890 The CRC error detection clock divisor has been changed to <number>, because the previous divisor <number> is not supported by the current device.
ID:18891 Feature <name> is only available with a valid license. You can purchase this feature to gain full access to it.
ID:18892 Are you sure that you want to delete the selected Logic Lock region member(s)?
ID:18893 Database format is incompatible with current version of Quartus Prime software -- Synthesis (quartus_syn) must be run first
ID:18895 The TCL command <command> from the design package is not supported while running on the Quartus Graphical User Interface
ID:18897 Rapid Recompile does not support changes to EMIF/PHYLite systems.
ID:18898 Unable to create Logic Lock Region. See the System tab of the Messages window for details.
ID:18901 <atom_name> is constrained to the region <atom_constraint> but is driven by <clock_name> which is constrained to the region <clock_constraint>.
ID:18902 Signal <clock> failed to route in region <region>.
ID:18905 <atom_name>, constrained to the region <region> does not overlap with the intersection of the clock regions driving it.
ID:18906 Could not find usable path between <name> and <name> because routing required for this path is reserved for another source
ID:18908 Custom routing file <name> is malformed: <message>
ID:18909 The SEU sensitivity map (.smh) file for the device cannot support more than <number> ASD regions. No SMH file will be generated for the design.
ID:18911 Rapid Recompile does not support designs with EMIF/PHYLite systems in partitions other than the root_partition.
ID:18914 The Hyper-Retimer was unable to optimize the design due to retiming restrictions. Run Fast Forward Timing Closure Recommendations to see step-by-step suggestions for design changes and show the estimated performance improvement from making these changes.
ID:18915 Quartus-created debug partition <partition> cannot be exported.
ID:18916 Cannot export partition from a design with Intel FPGA IP Evaluation Mode IP without a license.
ID:18918 IP reuse and integration is disabled. Please contact your Intel representative if you'd like to use it
ID:18919 IP reuse/integration is an early access feature. Contact your Intel representative if you'd like to use it.
ID:18922 No nodes available. Run Analysis & Synthesis.
ID:18923 No nodes available. Please complete all fitter stages.
ID:18926 IP reuse and integration is not allowed in a design using Partial Reconfiguration.
ID:18927 <text>
ID:18930 Verify that you have an active Internet connection, and that the Proxy settings are configured correctly in the Options dialog box, on the Internet Connectivity page.
ID:18931 To prevent the Intel Quartus Prime software from connecting to the Internet to check for updates, in the Options dialog box, on the Internet Connectivity page, turn off the options under Startup.
ID:18932 <text>
ID:18933 Unused transceiver channels cannot be preserved since CLKUSR pin location is incorrectly used as an output pin. To fix this warning, either connect the CLKUSR pin location to a 100-125 MHz clock or remove the QSF assignment enabling preservation of unused tranceiver channels.
ID:18934 The Fitter must be run at least through the Plan stage before board-level IBIS output files can be generated.
ID:18935 The bit at <name>, original value: <number>, current value: <number>
ID:18936 Using revision <name> as a baseline for <name> mask verification
ID:18937 Using revision <name> as a baseline for <name> region logic preservation verification
ID:18938 Using revision <name> as a baseline for static mask verification
ID:18939 Unexpected error in JTAG server: <text>
ID:18940 Device <number> contains JTAG ID code 0x<number>
ID:18941 Can't configure device. Expected JTAG ID code 0x<number> for device <number>, but found JTAG ID code 0x<number>. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf).
ID:18942 Configuring device index <number>
ID:18943 Configuration succeeded at device index <number>
ID:18944 CONF_DONE pin failed to go high in device <number>. Make sure all communication cables are securely connected, select a different device, check the power on the target system, or make sure all nCE pins are connected to GND. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
ID:18945 Performing Partial Reconfiguration at device index <number>
ID:18946 Partial Reconfiguration succeeded at device index <number>
ID:18947 Device not responding
ID:18948 Error message received from device: <text>
ID:18950 Device has stopped receiving configuration data
ID:18951 Error occurred when sending configuration data
ID:18952 Error status: <text>
ID:18956 Signal <Source signal name> is constrained to be routed over the global network to port <Destination port name> on destination <Destination atom name>, but this signal must be routed locally
ID:18957 Signal <Source signal name> is constrained to be routed locally to port <Destination port name> on destination <Destination atom name>, but this signal must be routed through the global network
ID:18960 Unable to create Logic Lock Region(s). Make sure the design has been synthesized.
ID:18961 Unable to create Logic Lock Region for <name>. The name could not be found in the design.
ID:18962 Unable to create Logic Lock Region for <name>. <error>
ID:18963 Node not found for "<name>". Make sure you have enter the correct node name.
ID:18964 Dedicated HPS IO Voltage mismatch. The VCCIO_HPS is set as <name> but the HPS dedicated pin <name> is set to an IO standard of <name>.
ID:18967 Cannot run Fitter Retime stage with Fast Forward Emulate INI (rtm_enable_fast_forward_emulate=on)
ID:18968 Cannot run Fitter Finalize stage with Fast Forward Emulate INI (rtm_enable_fast_forward_emulate=on)
ID:18969 IO Banks < <name> > are within same HSSI strip, Transceivers and PLLs placed inside these IO Banks needs to use the same power supply voltage. Transceivers and PLLs are using <name> power supplies.
ID:18972 Signal <Source signal name> is constrained to be routed over the global network to destination(s), but signal must be routed locally
ID:18974 Signal <Source signal name> is constrained to be routed locally to destination(s), but signal must be routed globally
ID:18975 The following location is not a clock pin, and does not have direct connectivity to the global network:
ID:18976 The following <number_of_clocks> global signals have long path lengths from source to clock tree. A long path may limit performance of high-speed signals. Consider revising the clock pin location or use Clock Region and/or Logic Lock Region assignments to constrain the placement of the fan-out closer to the source
ID:18977 The length of the partition name "<partition_name>" exceeds maximum allowed length <number> characters.
ID:18980 <clock_name> uses <path_length> to reach the clock tree.
ID:18981 The same partition name "<block>" is used for partition assignments on instances <partition1> and <partition2>. Multiple partitions cannot have the same name.
ID:18984 Cannot find partition <partition_name> in design.
ID:18985 Missing required license to enable design security feature.
ID:18986 Device family setting has changed from "<prev_device>" to "<curr_device>". Re-run synthesis with this new device family setting.
ID:18987 Warning status: <text>
ID:18990 Clock Region assignment <region> cannot be applied to global signal <signal_name> because all its fanout has already been constrained by the user.
ID:18991 Region has no routing region. Click to set the Routing Region.
ID:18993 Region has routing region. Edit the routing region size and location via the Properties window or Chip Editor.
ID:18994 Configuration Scheme '<name>' is not valid for the device
ID:18995 <fanout> destinations in <sector_description>
ID:18996 <Source of the clock signal> (<fanout> fanout) drives:
ID:18999 Placement cannot find a legal solution.
ID:19000 Inferred <number> megafunctions from design logic
ID:19001 Inferred lpm_counter megafunction (LPM_WIDTH=<number>) from the following logic: "<text>"
ID:19002 Inferred altmult_accum megafunction from the following logic: "<text>"
ID:19003 Inferred altmult_add megafunction from following the logic: "<text>"
ID:19004 RAM logic "<name>" is uninferred due to inappropriate RAM size
ID:19005 RAM logic "<name>" is uninferred due to device family not having RAM hardware
ID:19006 RAM logic "<name>" is uninferred because of a feature that is not supported by MLAB inference
ID:19007 RAM logic "<name>" is uninferred due to too many ports
ID:19010 Location of Partial Reconfiguration wire-LUT '<wirelut_string>' cannot be constrained due to an existing incompatible constraint.
ID:19011 Cannot place carry chain starting with node "<name>" due to invalid transitions of chain into and out of shared arithmetic mode
ID:19012 Logic between pin "<name>" and its register contains a loop -- cannot implement Power-Up Level option
ID:19013 Power-Up Level option on register "<name>" will override Power-Up Level option on pin "<name>"
ID:19014 Pin "<name>" has no register for Power-Up Level option
ID:19015 State machine "<name>" will be implemented as a safe state machine.
ID:19016 Clock multiplexers are found and protected
ID:19017 Found clock multiplexer <name>
ID:19018 Gated clocks are found and converted to use clock enables
ID:19019 Convert gated clock <name>
ID:19021 The same file name "<file_name>" is used for different IP files. The same name cannot be used for more than one IP file. Only directly include the .ip file, not the .qip or .qsys.
ID:19022 A default voltage has been automatically assigned to "<name>". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to <to> -entity <entity name> <value>" to specify the desired voltage.
ID:19023 Invalid snapshot name "<name>".
ID:19028 HPS DDR oct_rzqin pin is placed in a location not supported by HPS Early IO release. If you plan to use Early IO release, place the oct_rzqin in the IO bank 2K. In some circumstances you can place it in IO bank 2J.
ID:19029 HPS DDR pll_ref_clk pin is placed in a location not supported by HPS Early IO release. If you plan to use Early IO release, place the pll_ref_clk in the IO bank 2K. In some circumstances you can place it in IO bank 2J..
ID:19031 '<name>' is not supported in the Quartus Prime Pro edition software.
ID:19032 '<name>' is not supported in the Quartus Prime Pro edition software.
ID:19034 Unable to create at least one region -- see messages in the System tab of the Messages window for details
ID:19036 Can't create region for <instance short path> -- <reason>
ID:19037 Unable to remove at least one region -- <reason>
ID:19043 Unable to perform the requested Logic Lock operation as multiple regions are detected.
ID:19044 Unable to add the specified rectangle shape to a region. <reason>
ID:19045 Unable to subtract the specified rectangle shape from a region. <reason>
ID:19046 Unable to create a new Logic Lock region. <reason>
ID:19048 Signal <Name of signal> has been promoted to use the global clock network, but is placed on a non-dedicated clock pin location. To minimize clock uncertainty, Intel recommends placing all pin clocks on dedicated clock pin locations.
ID:19049 The derive_pll_clocks command is not supported in this family.
ID:19050 This command is deprecated because all PLL clocks are automatically generated by the SDC files generated alongside the PLL IP. No user action is required.
ID:19054 Updated the size and origin of <name> Logic Lock region(s) to match previous Fitter results.
ID:19055 Updated the size and origin of <name> Logic Lock regions to match previous Fitter results. <name> regions were unchanged either because they are already up-to-date, or they have not been compiled. View the message in the System tab of the Messages window for details.
ID:19056 The size and origin of Logic Lock region "<name>" is not updated to match previous Fitter Placed results. <reason>
ID:19062 For recommendations on closing timing for HyperFlex architectures, run Fast Forward Timing Closure Recommendations in the Compilation Dashboard.
ID:19063 Found an IOPLL cascade chain of three or more IOPLLs. The first three IOPLLs found are listed below.
ID:19064 "<PLL 1 name>"
ID:19066 The following region constraints for fanout belonging to <clock_name> overlap. They have been merged into a single clock tree in region <merged_bbox>
ID:19067 <bbox_desc>
ID:19068 CDR PLL < <name> > is used as cascade input of FPLL < <name> >. Intel does not recommend using this cascade path.
ID:19070 Failed to remove file/directory "<name>" (<reason>).
ID:19071 OSCILLATOR WYSIWYG instantiation <name> and instantiation <name> are in different design partitions
ID:19072 OSCILLATOR WYSIWYG instantiation <name> and instantiation <name> have different sim_clkout_period_ps settings <number> != <number>
ID:19077 Number of Hyper-Registers: <count>
ID:19078 Instance assignments in read-only partitions are ignored:
ID:19079 Ignored assignment "<assignment>" because <cause> belongs to a read-only partition "<partition_name>".
ID:19080 Additional <assignment_count> ignored instance assignments are not displayed.
ID:19081 Fitter must be run through to the final stage before running EDA Netlist Writer with --power option
ID:19082 <message>
ID:19083 Detected unfused device. Please contact PE to help to blow the fuses.
ID:19084 Can't run EDA Netlist Writer (quartus_eda) with options "<option1>" and "<option2>" -- options are mutually exclusive
ID:19085 Unable to create project database files because the Entity <type> source file cannot be located: "<filename>".
ID:19086 The Entity <file_type> file "<filename>" has been modified since the compilation started. Quartus is copying the new file into the database.
ID:19087 The Tcl command "<command_name>" is not permitted in SDC files that are bound to a design entity, or in any Tcl files that those SDC files have sourced.
ID:19088 Compilation Report contains advance information. Specifications for device <name> are subject to change. Contact Intel for information on availability. No partial reconfiguration programming files will be generated.
ID:19089 Writing to files is not permitted in SDC files that are bound to a design entity, or in any Tcl files that those SDC files have sourced.
ID:19091 Detecting a preserved partition <preserved_partition>
ID:19092 Failed to load <snapshot> snapshot of partition <preserved_partition> - ensure the block has been compiled through all earlier stages.
ID:19093 Are you sure that you want to delete the selected IP component(s) from project?
ID:19094 Erasing <text> at device index <number>
ID:19095 Blank-checking <text> at device index <number>
ID:19096 Programming <text> at device index <number>
ID:19097 Verifying <text> at device index <number>
ID:19098 Examining <text> at device index <number>
ID:19099 Can't recognize flash's device ID code <text> for device index <number>
ID:19100 An I/O (<name>) with a <iostandard_voltage> I/O standard is connected to a DDIO which is not allowed for Stratix 10 devices. See the Stratix 10 General Purpose I/O User Guide (UG-S10GPIO) for more information.
ID:19101 Cannot place cell with extent in the location since the location does not support partial extents.
ID:19103 Unable to change the Floating property for the Logic Lock region named "<name>" to <value>. <reason>
ID:19104 "<filename>" cannot be found in the Intel Quartus Prime project database files. Ensure that the missing source file is listed as an SDC_ENTITY_FILE or TCL_ENTITY_FILE assignment in the Quartus Settings File (.qsf).
ID:19105 Unable to open "<filename>" for write. Writing to files is not permitted in SDC files that are bound to a design entity, or in any Tcl files that those SDC files have sourced.
ID:19106 Blank-Check failed on <text>
ID:19107 Verification failed on <text>
ID:19111 For recommendations on closing timing for HyperFlex architectures, see the Fast Forward Timing Closure Recommendations report.
ID:19112 Importing a partition with preserved SDC files is only allowed by using the QDB_FILE assignment in the Quartus Settings File (.qsf).
ID:19113 Programming mode (<name>) in configuration file (<name>) of device <name> is mismatched with selected programming mode (<name>).
ID:19115 Response compare size mismatched
ID:19116 Examine failed on <text>
ID:19117 Programming failed on <text>
ID:19118 Erase failed on <text>
ID:19119 JTAG Indirect Configuration File (<size>) is too large for the flash <flash>
ID:19120 The input '<input_port>' to PR partition '<partition>' cannot have both global and local fanouts. Create separate input ports for global and local fanout.
ID:19121 VHDL format is not supported with --pr option for EDA Netlist Writer
ID:19123 Verilog HDL error at <location>: too many indices into <string>
ID:19127 Ignored SDC_ENTITY_FILE assignment "<sdc_entity_file>" that applies to an SDC preserved Partition Database File "<entity>".
ID:19160 Unable to assign "<name>" to Logic Lock region "<name>". <reason>
ID:19161 Cannot find QDB_FILE assignment "<qdb>" with preserved Entity SDC files in the Quartus Settings File (.qsf).
ID:19162 Changes to source files were detected in the current design and one or more partitions are being preserved. Ensure that source files changes do not affect preserved partitions.
ID:19163 Unable to rename the Logic Lock region from "<name>" to "<new_name>". <reason>
ID:19164 Could not set I/O bank <name> to VCCIO <vccio_value> because the following banks must have the same VCCIO setting in the selected device
ID:19165 I/O bank: <name> has VCCIO requirement: <vccio_value>
ID:19166 For IOPLL "<name>", feedback delay chain setting was reduced from "<number>" to "<number>" to keep the IOPLL stable.
ID:19167 <Message String>
ID:19168 This will delete the Logic Lock region "<name>" and you will not be able to undo the operation. Continue?
ID:19169 Transfer between periphery (<periphery atom name>) and DSP or RAM (<DSP or RAM atom name>) will make timing transfer impossible.
ID:19170 Transfer between periphery and DSP or RAM (<DSP or RAM atom name>) through logic cell (<logic cell atom name>) will make timing transfer impossible.
ID:19171 Partition "<partition_name>" was exported with the option to include entity-bound SDC files. The following entity-bound SDC files are included in the Partition Database File (.qdb):
ID:19172 <entity_sdc_name>.
ID:19173 The instance name "<name>" is already in use elsewhere in this scope. If instantiated in a generate block, ensure the block is named.
ID:19174 Cannot generate a Partial Reconfiguration bitstream with the Compression and CvP options enabled.
ID:19175 Partial Reconfiguration compression feature is not supported when CvP feature is enabled
ID:19176 Partition containing instance "<name>" of peripheral type "<name>" can not be emptied.
ID:19177 Detecting partition "<emptied_partition>" ("<inst_name>") to be emptied.
ID:19178 Failed to empty partition "<name>" ("<name>").
ID:19179 The EMIF interface has an input connection from the core (<Unconnected signal name>) that does not connect to a pin. Please review the top-level design to make sure all memory interface signals are connected to the top-level
ID:19180 Partition "<emptied_partition>" ("<inst_name>") has been emptied.
ID:19182 The Entity <filetype> source file cannot be located: "<filename>". Evaluation of this <filetype> file will be skipped.
ID:19185 Programming mode (<name>) in SOF file of device <name> is mismatched with selected programming mode (<name>).
ID:19186 Detected multiple IO_AUX atoms in the same column with their "<IO_AUX port>" port connected.
ID:19188 WYSIWYG primitive "<name>" has clock port <name>[<index>] that is driven by VCC or GND
ID:19189 The <port name> port for DSP block WYSIWYG primitive "<atom name>" should be GND when none of the <input/output/pipeline> registers are enabled. Make sure that the specified registers are enabled or connect the violating port to GND.
ID:19190 DSP block WYSIWYG primitive "<atom name>" has clear type not set as none but the clear port is either disconnected or connected to ground.
ID:19191 IO_AUX atom <IO_AUX atom> has its <IO_AUX port> port connected.
ID:19192 File <name> is <name> - <name>
ID:19203 'Configure device from CFM0 only' option has been turned on in Programming Object File, but the target device does not support this feature. The target device will ignore this option.
ID:19204 WYSIWYG primitive "<name>" has clear port <name>[<index>] that is driven by VCC
ID:19205 DSP block WYSIWYG primitive "<atom name>" has incorrect <port name> port connection -- port must be <number>-bit wide but <number> bits are connected
ID:19206 DSP block WYSIWYG primitive "<atom name>" has one or more registers using clock "<bit index>" but port CLK[<bit index>] is either not connected or driven by VCC or GND.
ID:19207 WYSIWYG primitive "<lutram name>" and WYSIWYG primitive "<reg name>" are connected to different read clock sources. Registered Port B Read Address input when placed as Hyperflex register must be connected with same clock source with output registered LUTROM.
ID:19208 Under QHD flow, Master CGB < <name> > has to be in the same partition with < <name> >, otherwise timing cannot be preserved.
ID:19209 HSSI PLD ADAPT < <name> > will be placed to wrong location, because there is no connection between PLD_ADAPT and other HSSI elements
ID:19213 PLL < <name> > is used as cascade input of PLL < <name> >. Intel does not recommend using this cascade path.
ID:19215 syn_encoding attribute for state machine "<name>" could not be parsed because <name>. Value is ignored.
ID:19216 syn_encoding attribute for entity "<name>" could not be parsed because <name>. Value is ignored.
ID:19218 Auto compute junction temperature is not currently supported for the selected device and family.
ID:19219 The routing element at location "<child_location>" is being sourced by routing elements at locations "<parent_location_1>" and "<parent_location_2>". This can be caused by importing two or more preserved partitions with overlapping routing or global signals.
ID:19220 USE PWRMGT_SCL output pin and USE PWRMGT_SDA output pin must be both configured together.
ID:19237 IBIS writer is not supported for bare die parts
ID:19238 Incomplete power management settings for a VID device. As a result, the tool may not generate device bitstream.
ID:19239 Missing required setting "<name>"
ID:19241 IOPLL "<PLL 1 name>" is driven by a core clock. This configuration is not recommended.
ID:19242 User defined synchronization register chain length set to 0 (Using unlimited chain length).
ID:19243 "<name>" can't start JTAG communication with debug instance. Connected JTAG Server does not support JTAG communication with debug instances within reconfigurable partitions.
ID:19245 Unable to provide further Fast Forward analysis of the design due to retiming restrictions (RTL or timing constraints).
ID:19249 An open Quartus Project is required to create a new IP variation. Please create a new Quartus project or open an existing one.
ID:19250 The PR bitstream ID is illegal.
ID:19252 None of the output clocks of IOPLL "<PLL 1 name>" are connected. Please use at least one
ID:19254 Find <number> master CGB(s) for PMA or PMA/PCS bonding channel: <name>
ID:19256 Fitter Hyper-Retiming optimizations are disabled. Check the 'Optimize Timing' setting to ensure retiming optimizations and analysis are permitted, and re-run the Quartus Fitter to fully take advantage of the HyperFlex architecture.
ID:19257 Fast Forward Timing Closure Recommendations analysis is disabled. Check the 'Optimize Timing' setting to ensure retiming optimizations and analysis are permitted, and re-run the Quartus Fitter to fully take advantage of the HyperFlex architecture.
ID:19258 IOPLL "<PLL 1 name>" is driven by its own output clocks.
ID:19259 Preserve at pre-synthesized snapshot "<snapshot>" is not allowed for partition "<preserved_partition>"
ID:19261 Signal <signal> has been constrained to a location that is a dual purpose pin that can be used by the PCIe HIP as nPERST. If using the signal as nPERST, please select a 3V IO_STANDARD. If you are not using PCIe and are intentionally trying to use a non-3V standard on this pin, please add 'set_instance_assignment -name USE_AS_3V_GPIO ON -to <signal>' to your QSF file. Otherwise, you can move this signal to another location.
ID:19262 Fitter post-routing fixup operations beginning
ID:19264 The case of the port "<name>" in the Partition Database File (.qdb) does not match the case of the port "<name>" in the stub file.
ID:19265 Percentage of connections rerouted to fix hold is <percent> percent.
ID:19268 Perform Analysis and Elaboration before generating data for RTL Viewer and make sure you have the data for any imported partition.
ID:19269 Channel < <name> > is placed within same bank of HIP|PIPE. The data rate cannot exceed 6.5Gbps
ID:19270 There are multiple PR regions in this design that may raise a timing conflict. Run aggregate compilation for all intended persona combinations.
ID:19272 Using <qdb_file> to replace the root partition.
ID:19273 Family <name> is not installed
ID:19274 Cannot find a QDB_FILE_PARTITION assignment for partition "<s>".
ID:19275 Assignment "<name>" is not supported in this edition of the Intel Quartus Prime software. Remove assignment from Quartus Prime Settings file.
ID:19276 Command-line option --preserve only accepts partition name. Use the partition name for your hierarchical instance "<instance_hier_name>".
ID:19279 Applying fix to legalize PCIe Gen1 or PCIe Gen2 IP settings in designs exported between Quartus versions 16.0.2 and 16.1.1
ID:19280 Removing leading or trailing whitespaces for name: <Name>
ID:19281 Found illegal characters in name: <Name>
ID:19282 Value of parameter <param_name> changed from <cur_val> to <new_val>
ID:19283 Value of parameter <param_name> not changed from <cur_val> since it is legal
ID:19284 Value of parameter <param_name> not changed from <cur_val> since it's value was set by QSF assignment <qsf_asgn>
ID:19285 Atom Type: <atm_type>, Atom Name: <atm_name>
ID:19286 No license for family <name>, for self-service licensing visit the Intel FPGA Licensing Support Center at https://www.intel.com/content/www/us/en/support/programmable/licensing/support-center.html
ID:19288 No parameters were changed. The design may not contain the target IPs, the parameter values could be fixed via QSF settings or the design is already legal.
ID:19289 At least one parameter value was legalized in the imported design database. You must regenerate programming files with the Quartus Assembler (quartus_asm) and re-verify timing using the Quartus Timing Analyzer (quartus_sta)
ID:19292 Could not find dynamic reconfiguration settings file "<file>" for block "<name>".
ID:19293 Imported database was exported with a version of Quartus outside the prescribed range. Fix <fix_description> can only be applied to designs exported between Quartus versions <version_lo> to <version_hi>.
ID:19294 Synopsys Design Constraints File file not found for instance '<Instance name>': '<SDC File name>'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
ID:19296 Cannot load <snapshot> snapshot - ensure the design has been compiled through all earlier stages.
ID:19299 PCS Bonding's master channel < <name> > is behind HIP block. This will cause hold time violation
ID:19300 DSP WYSIWYG primitive "<atom name>" has clock setting "<parameter name>" that is not set to "none".
ID:19302 Using dynamic reconfiguration settings file "<file>".
ID:19303 Port "<name>" exists in "<name>" but does not exist in parent entity "<name>" from the Partition Database File (.qdb).
ID:19304 Port "<name>" does not exist in the "<name>" but exists in parent entity "<name>" from the Partition Database File (.qdb).
ID:19305 The width of the port "<name>" in "<name>" does not match the width in parent entity "<name>". The width is <number> in parent entity.
ID:19306 Hyper-Register <name> must be driven by a global clock. Its clock signal is <name>.
ID:19308 The region (<number>, <number>) to (<number>, <number>) is occupied by more than one Partial Reconfiguration region
ID:19309 For IOPLL "<PLL name>" clock "<PLL clock_to_compensate oport name>" on the feedback path is not connected.
ID:19310 EDA Netlist writer does not support power simulation option with <family> family.
ID:19311 You are starting acquisition with the Power-Up Trigger feature in the reconfiguration partition. The Power-Up condition doesn't work.
ID:19312 The following On-Chip Termination blocks are not in the same partition.
ID:19313 On-Chip Termination node "<block_name>" is in partition "<partition_name>".
ID:19315 <ip_name> related IPs are not in the same partition.
ID:19317 No user constrained <name> found in the design. Calling <command>
ID:19318 QDB File Partition assignment "<qdb_filename>" is being applied on the root partition. Importing a root partition using the QDB File Partition assignment is not supported.
ID:19319 IP hierarchy: "<iname>".
ID:19321 Using "<qdb_filename>" to define the partition "<partition>".
ID:19323 The following partitioning on IP hierarchies are affected.
ID:19324 Partition: "<partition>".
ID:19325 One or more QDB File Partition assignments have the "library" argument defined. The "library" argument is not supported for the QDB File Partition assignment.
ID:19326 The partition "<partition>" is assigned to use a Partition Database File (.qdb) and is also assigned a Preservation Level with a PRESERVE assignment. Remove one of these conflicting assignments to either use the QDB file or preserve the previous compilation results.
ID:19327 The Quartus Settings File (.qsf) contains a CREATE_PARTITION_BOUNDARY_PORTS assignment to node: "<target>" in an inappropriate hierarchy. No boundary port(s) will be created.
ID:19329 The Partition Database File "<qdb_filename>" implements a partition that was preserved at the "<snapshot>" snapshot and is assigned to <partitions> design partitions. Only Partition Database Files preserved at the "synthesized" snapshot can be imported into more than one design partition.
ID:19330 Do you also want to set the size and the origin of the selected region to previous Fitter results? (Yes is recommended)
ID:19337 VHDL info at <location>: executing entity "<name>" with architecture "<name>"
ID:19342 QDB_FILE assignment "<qdb_name>.qdb" is not supported for lower-level design entities.
ID:19344 The Entity <type> file assignment for source file "<filename>" does not have the -entity option defined.
ID:19345 The Entity <type> file assignment for source file "<filename>" is targetting the top-level design entity "<top_entity>".
ID:19348 Exporting design partition "<partition_name>" with debug agents. Debug agents exported in a partition from one design will not be functional when compiled into another design.
ID:19349 This design has at least one partition marked as empty. Use extreme caution when using programing file with empty partitions. The removed logic will alter the functionality of the design and may cause damage to the FPGA or other devices. To remove this warning, recompile the design without EMPTY assignment before running the assembler.
ID:19350 The partition <partition_name> or its descendant has been emptied and some logic has been removed. The user must ensure that the removed logic will not create any adverse effects to the FPGA or other devices. To remove this warning, recompile the design without EMPTY assignment on the partition before export.
ID:19352 The instance assignment (<assigment_name>) uses deprecated "entity:inst" style. Instance paths should be specified using only instance names.
ID:19353 User specified to use only one processors but <num_procs_detected> processors were detected which could be used to decrease run time.
ID:19354 Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
ID:19357 An invalid value of '<value>' is specified for the Global Signal assignment.
ID:19359 Channel < <name> > cannot be placed at the HIP channel location < <name> > due to HIP location conflicts. Change the channel to a different location to avoid HIP channel locations.
ID:19360 CVP mode or CVP_CONFDONE pin is supported in Active Serial configuration schemes only. Please turn CVP mode off, uncheck CVP_CONFDONE pin or change the configuration scheme.
ID:19361 Cannot import design revision "<import revision name>" because current active revision "<active revision name>" does not match the imported design database revision name. Before importing, change the active revision to the revision with the same name as the revision that was used to export the design database.
ID:19365 Global preservation of unused transceiver channels is enabled. All unused transceiver channels will be preserved.
ID:19366 Partial Reconfiguration and Reserved Core partitions are not supported for the <family> device family
ID:19370 The design partition "<partition>" is not reconfigurable. For a design with a QDB_FILE applied on the root partition, each design partition has to be set as reconfigurable.
ID:19371 Routing Element parameter changed from <cur_val> to <new_val>
ID:19373 <info>
ID:19374 The REFCLK of PLL < <name> > is sourced from a pin in a different tile.
ID:19375 Cannot import a design compiled with device "<import revision device>". The active revision device is set to "<active revision device>". Update active revision device setting to match the imported design database device setting "<import revision device>" before importing.
ID:19376 PIPE master channel < <name> > has to be placed at second or fifth location of the HSSI tile.
ID:19380 Clock <clock_name> is constrained to <bbox_desc> but has specialized routing requirements for UIB and/or ESRAM destinations that cannot be satisfied. The closest possible legal extent is <legal_bbox_desc>
ID:19381 Clock <clock_name> is constrained to <bbox_desc> but has specialized routing requirements for HSSI destinations that cannot be satisfied. The closest possible legal extent is <legal_bbox_desc>
ID:19382 Entity rebinding has been applied to partition <partition>. The entity has been remapped from <old_node_name> to <new_node_name>.
ID:19383 Quartus Prime <name> was stopped. <number> error<name>, <number> warning<name>
ID:19384 Quartus Prime <name> was stopped. <number> error<name>, <number> warning<name>
ID:19385 Node '<string>' is a MACRO_HEAD
ID:19386 Node '<string>' has -from node '<string>' and this -from node is not recognized as a MACRO_HEAD
ID:19426 EDA Netlist writer supports default VQM generation with synthesized snapshot only. Specify --snapshot=synthesized or do not use the snapshot option.
ID:19427 When over 16 channels on the same HSSI tile are driven from the same PLL < <name> > through MCGB with dynamically reconfigured PLL frequency, the remaining 8 channels on the same die are recommended to be driven by LC-PLL.
ID:19428 The Atom "<atom name>" has an invalid setting of "<setting>" for the "Receiver Variable Gain Amplifier Voltage Swing Select" parameter for the Transceiver IP. Please edit the value in the Quartus Assignment Editor. The allowed values are [0|1|2|3|4]. The parameter is saved as "XCVR_A10_RX_ADP_VGA_SEL" in the Quartus Settings File (.qsf).
ID:19431 Detected large hold constraints. Backing off hold to help converge in a timely fashion, this may cause hold time failures.
ID:19432 Transfer between periphery (<periphery atom name>) and DSP or RAM (<DSP or RAM atom name>) will make timing transfer impossible.
ID:19433 Transfer between periphery and DSP or RAM (<DSP or RAM atom name>) through logic cell (<logic cell atom name>) will make timing transfer impossible.
ID:19434 Ignored initial state "<name>" on state machine "<name>". The state machine powers up to state "<name>" due to asynchronous reset
ID:19436 Unable to create project database files because the source file "<filename>" cannot be located.
ID:19437 "Receiver Variable Gain Amplifier Voltage Swing Select" setting of "<setting>" is being used for Atom "<atom name>". Please refer to the device lifetime guidance in "Errata and Design Guidelines" to ensure system requirements are met.
ID:19438 Detected clock domain crossings between the following signals. To minimize skew, these clock trees will be routed to the same region: <extent>
ID:19439 Global Signal name: <Signal name>
ID:19440 Signal <Signal Name> is user constrained to <extent> and cannot be placed to optimize clock domain crossings. This may detrimentally affect timing closure
ID:19442 More than one <name> option specified
ID:19443 Bootloader input file <name> is not in hex or ihex extension.
ID:19444 Can't generate programming file <name> - <error>.
ID:19445 The VCO frequency for IOPLL "<PLL name>" is outside the allowed range (600 MHz to <VCO frequency's upper limit> MHz). Regenerate the IOPLL IP with a legal VCO frequency.
ID:19446 There are Partial Reconfiguration or Reserved Core partitions that occupy the same Row Clock region. Adjust the <region_type> regions of the following partitions such that they occupy non-overlapping Row Clock regions:
ID:19447 <p1> and <p2> incorrectly occupy the same Row Clock region.
ID:19448 The atom < <name> > is not compatible with current device < <name> >. Please either change the IP or select a compatible device.
ID:19449 Reading SDC files elapsed <Message String>.
ID:19450 CMU < <name> > cannot be placed because CDR 1 and 4 of this transceiver bank are already used.
ID:19451 There are <Number of IOPLLs in design> IOPLLs in this design, but only <Number of I/O banks in design> IOPLL locations with bonded reference clock input pins are available. <Number of IOPLLs with no I/O bank> IOPLLs must be driven from a global clock or cascaded from another IOPLL.
ID:19454 Partition Database File "<NAME>" does not exist
ID:19461 IOPLL "<IOPLL atom name>" is driven by an internal oscillator ("<Oscillator atom name>"). This configuration is not supported.
ID:19462 Verilog HDL error at <location>: synthesis of <string> datatype is not supported. Signal <string> will be ignored
ID:19464 Boundary port(s) of the parent Partial Reconfiguration (PR) region '<pr_parent_region_name>' is incorrectly placed inside the child Partial Reconfiguration (PR) region(s). This placement is invalid because the child PR region is reconfigurable.
ID:19468 Can't open Properties dialog -- see messages in the System tab of the Messages window for details
ID:19469 Can't open Properties dialog for file <name> -- file does not exist
ID:19470 The following SDC_ENTITY_FILE was added, modified or removed after the fitter. It will be reflected in timing analysis, but will not be reflected in any exported database until the design is recompiled.
ID:19471 \t"<SDC_FILE_NAME>"
ID:19472 The following SDC_ENTITY_FILE were added, modified or removed after "<executable>" was run. Changes will not be reflected in any exported database until after rerunning "<executable>".
ID:19473 \t"<SDC_FILE_NAME>"
ID:19475 Partition '<partition_name>' has the preservation level set to '<preserve_snapshot>' which does not exist. Partition '<partition_name>' will be compiled from '<default_snapshot>'.
ID:19478 Can't save or open file <name>
ID:19481 You cannot rename the root partition ("|"). The root partition name must be "root_partition". Remove any setting(s) in the Design Partitions Window or .qsf assignment(s) that alters the name of the "root_partition".
ID:19483 Timing data is not available. Please run command "generate_timing_data_for_dpp" in the Timing Analyzer to generate the timing data.
ID:19484 Design Partition Planner is showing timing data generated on <date">
ID:19488 The partition "<partition_name>" specified for export does not correspond to a valid partition in the design.
ID:19489 The module name argument: "<module_name>" is malformed. The expected format is --module_name=old_name=new_name
ID:19490 File "<name>" is not a valid Root Partition Database file
ID:19491 File "<name>" is not a valid Root Partition Database file
ID:19492 Fast Preservation is enabled for the following partitions.
ID:19493 Partition: <hpath>
ID:19494 Raw Programming Data File <name> contains configuration device programming data for file <name>
ID:19495 File <name> is corrupted
ID:19496 Failed to load the '<model_name>' database model.
ID:19497 Error is not injected - device <number> currently does not support fault injection to the specified sector location.
ID:19498 Error #<number> at sector <name>: <name> <name> in frame <name> at bit <name>. <name>
ID:19499 Device <number> is not in usermode.
ID:19500 The partition "<partition_name>" has both "<partition_type>" and other hierarchical flow options ("Empty", "Preserve") . The combination of the Partial Reconfiguration flow and other hierarchical design flows is not allowed.
ID:19503 Corrected error #<number> at sector <name> : <name> <name> in frame <name> at bit <name>.<name>
ID:19504 File <name> is corrupted. <name>
ID:19507 QDB_FILE assignment "<qdb_file_name>" is not supported.
ID:19508 Verilog HDL or VHDL error at <location>: Net '<name>' has no source. It is referencing a net outside of the current module.
ID:19509 Cannot locate file <name>.
ID:19510 Incomplete command. Use "-h" or "--help" option to display command information.
ID:19511 Unsupported output file type (<name>). Use "-l" or "--list" option to display supported file type information.
ID:19512 Unsupported secondary file type (<name>). Use "-l" or "--list" option to display supported file type information.
ID:19513 Option "<name>" does not belong to any output file or secondary file(s).
ID:19515 Saved Programming File Generator Setup File <name>
ID:19516 Detected Programming File Generator settings error: <reason>
ID:19517 Quartus Prime partially connected Signal Tap or other In-System debug instance "<name>" to <number> of the <number> requested data inputs, trigger inputs, acquisition clocks, and dynamic pins. Please check the compilation report for more details.
ID:19519 The instance assignment "POWER_UP_LEVEL" on register "<register_name>", in reconfigurable partition "<partition_name>", is ignored. Initial condition is not guaranteed during partial reconfiguration.
ID:19523 Preserved <number> unused RX channel(s).
ID:19524 Preserved <number> unused TX channel(s).
ID:19530 Placement failed to find a legal solution for <number> LABs, <number> M20Ks and <number> DSPs in the locations from (<number>, <number>) to (<number>, <number>), additional legalization operations will be performed. This failure may inadvertently affect the timing results.
ID:19531 An empty region has an invalid assignment string "<Assignment string>"
ID:19533 The design contains both Partial Reconfiguration and Reserved Core Partitions, which are incompatible. Remove one of the partition type options from the design.
ID:19534 Using <qdb_file> to replace the partition <partition_name>.
ID:19535 QDB_FILE_PARTITION <qdb_file> is not assigned to a valid target <target>.
ID:19536 <Warning String>
ID:19537 The output port '<to>' of partition '<partition>' connects to the input port '<from>', and passes through the partition with no logic in the path. This creates a loop with no logic and is not valid.
ID:19538 Reading SDC files took <Message String> cumulatively in this process.
ID:19539 Reading the HDL-embedded SDC files elapsed <Message String>.
ID:19542 Channel-specific preservation of unused transceiver channels is enabled
ID:19543 Unused transceiver channel at location '<Pin name for unused transceiver channel location>' will be preserved
ID:19544 Verilog HDL error at <location>: if-condition does not match any sensitivity list edge
ID:19545 Verilog HDL error at <location>: unpacked dimension mismatch between actual expression <string> and formal port '<string>'
ID:19546 Verilog HDL error at <location>: class assignment is not synthesizable
ID:19547 Verilog HDL error at <location>: task or function '<string>' with ref arguments must be automatic
ID:19548 Verilog HDL error at <location>: width <number> of actual differs from width <number> of formal
ID:19549 Verilog HDL error at <location>: width <number> of actual differs from width <number> of formal port '<string>'
ID:19550 Verilog HDL error at <location>: interface '<string>' does not have a parameter named '<string>'
ID:19551 Verilog HDL info at <location>: <string>
ID:19554 Verilog HDL warning at <location>: no netlist generated for <string>
ID:19555 Verilog HDL warning at <location>: genvar '<string>' is already declared
ID:19556 Verilog HDL info at <location>: previous error may be caused by a too long file name
ID:19557 Verilog HDL error at <location>: invalid value for time literal <string>, must be 1, 10 or 100.
ID:19558 Verilog HDL error at <location>: modport '<string>' is selected inside interface array '<string>' <string> indexing
ID:19559 Verilog HDL warning at <location>: method '<string>' of class '<string>' cannot have static lifetime, considering automatic
ID:19560 Verilog HDL error at <location>: invalid use of empty queue operation
ID:19561 Verilog HDL error at <location>: new expression cannot be used as constant expression
ID:19562 Verilog HDL error at <location>: cannot add generic interface type port in non-ansi mode
ID:19563 Verilog HDL error at <location>: wrong number of index dimensions at '<string>', cannot select '<string>'
ID:19564 Verilog HDL warning at <location>: class constructor should not be declared virtual
ID:19565 Verilog HDL error at <location>: wildcard indexed associative array '<string>' is not allowed in foreach loop
ID:19566 Verilog HDL error at <location>: DPI export method '<string>' is already defined
ID:19567 Verilog HDL warning at <location>: initial value of static variable '<string>' ignored for synthesis
ID:19568 Verilog HDL warning at <location>: highz1/highz0 is not allowed as <string> strength
ID:19569 Verilog HDL warning at <location>: invalid <string> strength <string>, requires <string> specification
ID:19570 Verilog HDL error at <location>: invalid use of method <string>
ID:19571 Verilog HDL error at <location>: keyword new is not expected to be used in this context
ID:19572 Verilog HDL warning at <location>: argument name '<string>' for virtual method '<string>' does not match the argument name '<string>' in superclass
ID:19573 Verilog HDL error at <location>: <string> of $cast must be singular
ID:19574 Verilog HDL error at <location>: '<string>' cannot be listed in modport
ID:19575 Verilog HDL warning at <location>: invalid <string> port in function '<string>' used in <string>
ID:19576 Verilog HDL error at <location>: hierarchical reference from package '<string>' into <string> '<string>' is not allowed
ID:19577 Verilog HDL warning at <location>: always_ff procedure inside checker cannot have blocking assignment
ID:19578 Verilog HDL error at <location>: <string> assignment to free checker variable '<string>' is invalid
ID:19579 Verilog HDL error at <location>: invalid syntax for slice-size, needs simple-type or constant-expression
ID:19580 Verilog HDL warning at <location>: target of assignment pattern cannot be string type, must be array/structure
ID:19581 Verilog HDL error at <location>: localparam '<string>' cannot be declared without a default value
ID:19582 Verilog HDL error at <location>: checker variable '<string>' may not be assigned in an initial procedure
ID:19583 Verilog HDL error at <location>: $cast to type '<string>' from '<string>' is invalid
ID:19584 Verilog HDL error at <location>: prefix of <string> cannot be enumeration literal, should be variable of enumeration type
ID:19585 Verilog HDL error at <location>: symbol '<string>' is visible in package '<string>', but has not been exported for re-import in other scopes
ID:19586 Verilog HDL error at <location>: '<string>' uses interface item '<string>' not visible under prefix '<string>' via modport '<string>'
ID:19587 Verilog HDL error at <location>: cannot assign to function name '<string>' from here
ID:19588 Verilog HDL warning at <location>: <string> as 32-bit signed integer overflows, using <number> instead
ID:19589 Verilog HDL error at <location>: hierarchical name is not allowed here
ID:19590 Verilog HDL warning at <location>: formatting with "%c" ignored
ID:19591 Verilog HDL error at <location>: missing argument for format specifier "%c"
ID:19592 Verilog HDL warning at <location>: formal port direction <string> does not match prototype direction <string> for port '<string>'
ID:19593 Verilog HDL error at <location>: package export '<string>::<string>' failed - conflicts with imported '<string>::<string>'
ID:19594 Verilog HDL error at <location>: constraint block never defined for explicit constraint prototype '<string>'
ID:19595 Verilog HDL error at <location>: external constraint '<string>' of class '<string>' is already defined outside the class
ID:19596 Verilog HDL warning at <location>: multiple concatenation without { violates IEEE 1800 syntax
ID:19597 Verilog HDL warning at <location>: non constant expressions are not allowed as array assignment pattern key
ID:19598 Verilog HDL error at <location>: operator <string> is not allowed in a 2005 SystemVerilog mode
ID:19599 Verilog HDL error at <location>: incorrect use of '$<string>', it is valid only as default argument for a property, sequence or a checker
ID:19600 Verilog HDL error at <location>: ansi port '<string>' cannot be redeclared
ID:19601 Verilog HDL warning at <location>: <string> '<string>' having ansi port header should not have non-ansi style port declaration
ID:19602 Verilog HDL error at <location>: signal clocked multiple times is not synthesizable
ID:19603 Verilog HDL error at <location>: <string> is not allowed inside package
ID:19604 Verilog HDL info at <location>: moving out-of-block method '<string>' to container class '<string>'
ID:19605 Verilog HDL error at <location>: weight in randcase must be a non-negative integral value
ID:19606 Verilog HDL warning at <location>: modport '<string>' should not be used in hierarchical reference
ID:19607 Verilog HDL error at <location>: '<string>' is referred in modport expression for modport '<string>', but not declared in interface '<string>'
ID:19608 Verilog HDL error at <location>: invalid <string> qualifier specified for function declaration
ID:19609 Verilog HDL warning at <location>: port '<string>' added as first port of module '<string>', existing instances may need to be updated
ID:19610 Verilog HDL error at <location>: cannot assign value of <string> to <string>
ID:19611 Verilog HDL warning at <location>: use of `" was not closed by another `"
ID:19612 Verilog HDL error at <location>: signing in slice size of streaming concatenation violates IEEE 1800 syntax
ID:19613 Verilog HDL error at <location>: defparam under generate scope cannot be applied
ID:19614 Verilog HDL error at <location>: unnamed <string> port cannot be connected via .*
ID:19615 Verilog HDL warning at <location>: bind to black box module '<string>' is ignored
ID:19616 Verilog HDL warning at <location>: empty logic created for UDP
ID:19617 Verilog HDL error at <location>: pure constraint '<string>' cannot be declared in non-abstract class '<string>'
ID:19618 Verilog HDL warning at <location>: non void function '<string>' is called without empty parenthesis
ID:19619 Verilog HDL warning at <location>: initial value of class/struct member '<string>' ignored for synthesis
ID:19620 Verilog HDL warning at <location>: foreach loop violates IEEE 1800 syntax
ID:19621 Verilog HDL warning at <location>: ignoring non-LRM compliant attribute '<string>'
ID:19622 Verilog HDL warning at <location>: syntax interface::self within an interface is an extension of LRM
ID:19623 Verilog HDL warning at <location>: method empty for queues violates IEEE 1800 syntax
ID:19624 Verilog HDL info at <location>: back to file '<string>'
ID:19625 Verilog HDL error at <location>: incorrect iterator argument in array manipulation method call
ID:19626 Verilog HDL error at <location>: with clause is not specified for iterator argument in array manipulation method <string>
ID:19627 Verilog HDL error at <location>: function call in array name of foreach violates IEEE 1800 syntax
ID:19628 Verilog HDL error at <location>: invalid 4 state constant in constraint
ID:19629 Verilog HDL warning at <location>: $bits system function cannot have argument of type real
ID:19630 Verilog HDL warning at <location>: begin/end is required for <string> in this mode of Verilog
ID:19631 Verilog HDL error at <location>: '<string>' is not a valid constant function
ID:19632 Verilog HDL warning at <location>: indexing without parentheses is invalid here
ID:19633 Verilog HDL error at <location>: invalid argument to <string> randomize call
ID:19634 Verilog HDL warning at <location>: argument '<string>' to randomize call violates IEEE 1800 LRM
ID:19635 Verilog HDL warning at <location>: unsupported use of clock signal '<string>', clock used as data
ID:19636 Verilog HDL error at <location>: cannot elaborate .* port-connection for black box instance '<string>'
ID:19637 Verilog HDL warning at <location>: variable <string> may be used before assigned in always_comb or always @* block : might cause synthesis - simulation differences.
ID:19638 Verilog HDL error at <location>: non integral type is not allowed in range index
ID:19639 Verilog HDL warning at <location>: indexed name in bins expression violates IEEE 1800 syntax
ID:19640 Verilog HDL error at <location>: dynamic types are not allowed in clocking block
ID:19641 Verilog HDL error at <location>: embedded covergroup '<string>' cannot be used as type
ID:19642 Verilog HDL error at <location>: invalid return type for built-in method '<string>'
ID:19643 Verilog HDL error at <location>: invalid argument signature for built-in method '<string>'
ID:19644 Verilog HDL error at <location>: skew can be specified as the specific edge of the signal when clocking event is a single edge
ID:19645 Verilog HDL error at <location>: <string> keyword <string> used in incorrect context
ID:19646 Verilog HDL error at <location>: use of virtual qualifier is not allowed here
ID:19647 Verilog HDL warning at <location>: member '<string>' of unpacked structure containing union may not be declared rand or randc
ID:19648 Verilog HDL error at <location>: compilation unit name can only be specified in MFCU mode
ID:19649 Verilog HDL error at <location>: $finish is not synthesizable
ID:19650 Verilog HDL error at <location>: <string> pragma cannot be specified inside a design unit
ID:19651 Verilog HDL warning at <location>: latch inferred for net <string>
ID:19652 VHDL error at <location>: assignment ignored
ID:19653 VHDL warning at <location>: size mismatch in mixed language port association, Verilog port '<string>'
ID:19654 VHDL error at <location>: unit '<string>' is not yet analyzed
ID:19655 VHDL error at <location>: cannot synthesize access type values
ID:19656 VHDL error at <location>: formal '<string>' remains unconstrained
ID:19657 VHDL error at <location>: expression of matching <string> is not a bit or a std_ulogic or 1-dimensional array of bit/std_ulogic
ID:19658 VHDL warning at <location>: <string> interface subprogram '<string>', actual subprogram '<string>' is <string>
ID:19659 VHDL error at <location>: cannot reference external name inside pure function '<string>'
ID:19660 VHDL info at <location>: <string>
ID:19661 VHDL error at <location>: <string> depends on two different clock edges
ID:19662 VHDL error at <location>: file '<string>' is not open for procedure <string>
ID:19663 VHDL error at <location>: access mode of file object '<string>' cannot be read-only for procedure <string>
ID:19664 VHDL info at <location>: extracting RAM for identifier '<string>'
ID:19665 VHDL warning at <location>: failed to open VHDL file '<string>' in mode '<string>'
ID:19666 VHDL error at <location>: file '<string>' is not open
ID:19667 VHDL info at <location>: library '<string>' is mapped to '<string>'
ID:19668 VHDL error at <location>: parameter '<string>' of protected type must be of mode inout
ID:19669 VHDL error at <location>: <string> '<string>' cannot be associated with formal interface type '<string>'
ID:19670 VHDL error at <location>: FILE declaration must have a subtype indication that is a file type
ID:19671 VHDL error at <location>: formal '<string>' for resolution function '<string>' is not a constant
ID:19672 VHDL error at <location>: initial value for variable declaration is not access value
ID:19673 VHDL error at <location>: interface package element '<string>' cannot contain mapping DEFAULT when generic package <string> contains an interface <string> element '<string>'
ID:19674 VHDL error at <location>: variable <string> of protected type cannot be target of variable assignment statement
ID:19675 VHDL error at <location>: base type of file type definition is not <string>
ID:19676 VHDL error at <location>: '<string>' in value attribute is not a valid numeric literal
ID:19677 VHDL error at <location>: prefix of attribute <string> should be a named entity
ID:19680 VHDL warning at <location>: ignoring block configuration for Verilog module '<string>'
ID:19681 VHDL error at <location>: the external name (<string>) could not be resolved due to too many upscope elements
ID:19682 VHDL error at <location>: signal assignment must be guarded because the target is guarded
ID:19683 VHDL error at <location>: <string> pragma cannot be specified inside a design unit
ID:19684 VHDL warning at <location>: latch inferred for net <string>
ID:19685 Netlist error at <location>: cannot find instance '<string>' in this netlist
ID:19686 Executed Tcl script "<name>" successfully.
ID:19687 Failed to execute Tcl script "<name>". Error message was "<error message>"
ID:19688 Placement failed to find a legal solution due to row legality failure, additional legalization operations will be performed. This failure may inadvertently affect the timing results.
ID:19692 Soft Macro assignments are not valid
ID:19693 In MACRO "<string>", node "<string>" is not a valid <string> due to its unsupported node type at Z location <int>
ID:19694 In MACRO "<string>", node "<string>" is not a valid <string> due to its invalid Z value <int>
ID:19695 Node "<string>" needs to be in the same Soft Macro with node "<string>"
ID:19696 In MACRO "<string>", node "<string>" has invalid <string> value <int> that violates carry chain placement constraints
ID:19697 In MACRO "<string>", <string> "<string>" is a carry chain head
ID:19698 The node is a carry chain node that needs to be aligned with the rest of the chain with X offset value equal to <int>
ID:19699 The node is a carry subchain head node that needs to be placed adjacent to the previous carry subchain
ID:19700 The node is a carry subchain <string> node that is not placed at a legal <string> location inside the LAB, it needs to be placed with Z value equal to <int> or <int>
ID:19701 The node is a carry chain node that needs to be placed adjacent to the previous carry chain node "<string>"
ID:19702 Fitter has implemented the following <number> RAMs using MLAB locations, which can behave differently during power up than dedicated RAM locations
ID:19703 Target device does not support programming file with file extension <name> for Partial Reconfiguration
ID:19704 Partition "<emptied_partition>" ("<inst_name>") or its parent has a Partition Database File (.qdb) or a preservation setting assigned to it and cannot be emptied. To empty this partition, removed the QDB file assignment or preservation setting first, then set the partition to empty and recompile..
ID:19705 The net "<name>" in module "<name>" is assigned outside of its module. Cross-module references are not supported in synthesis.
ID:19707 Node "<string>" is assigned to Soft Macro multiple times
ID:19709 An invalid value of '<value>' is specified for the Global Signal assignment. Valid values for the Global Signal assignment for this device are 'On', 'Global Clock' (equivalent to the value of 'On') and 'Off'.
ID:19710 Please choose a valid instance name for Signal Tap instance "<old_instance_name>". Valid instance names do not contain whitespace, or any of the following characters: ""'*^`,.[]{}<>()&!?@#$%|\\:;-+=
ID:19711 Logic Lock region "<Region name>" includes either a partial reconfiguration or a Reserved Core member along with other region members. Partial reconfiguration or Reserved Core partitions cannot share a Logic Lock region.
ID:19712 Duplication of registers and lcell_comb due to max-fanout constraints caused the netlist to double in size. Synthesis will not process all constraints.
ID:19716 Ignoring the REVISION_TYPE assignment. The root partition reuse flow does not use the REVISION_TYPE assignment.
ID:19718 <Design instance> is the partial reconfiguration or Reserved Core partition within "<Region name>"
ID:19720 <Design instance> cannot share "<Region name>" with a partial reconfiguration or reserved core partition.
ID:19722 Fitter Physical Synthesis has stopped because of an unplaced atom <name>.
ID:19724 Fitter requires <number> LABs for <name> in locations from lower-left (<number>, <number>) to upper-right (<number>, <number>), but only <number> LABs are available exclusively for that region. Fitting has terminated due to high LAB utilization in that region.
ID:19725 Fitter is having difficulty packing the design as it requires <number> LABs but only <number> LABs are available
ID:19726 Fitter is having difficulty packing for <name> in locations from lower-left (<number>, <number>) to upper-right (<number>, <number>), as it requires <number> LABs but only <number> LABs are available exclusively for that region
ID:19727 Fitter will now perform the packing at <name> effort level
ID:19728 Cannot export partition <partition_name> when it contains connections for the Signal Tap Logic Analyzer, Logic Analyzer Interface, or other in-system debugging instance.
ID:19729 <name>
ID:19730 <name>
ID:19731 <string> was imported successfully. Do you want to run the task again?
ID:19732 Sector clock gate <clkgate Name> drives to <fanout name> which is in a different partition. Sector clock gates and their destinations must be in the same partition.
ID:19733 The following instances of <ip_name> periphery IP are not in the root partition. Remove any instances of this IP in a non-root partition.
ID:19736 Exporting the top-level partition (root_partition) is intended for the Partial Reconfiguration and Reserved Core flows. Use Export Design option to export the whole design.
ID:19738 Unused channel preservation is not supported for a non-production device.
ID:19739 <hpath>.
ID:19740 Are you sure that you want to delete the selected partition(s)?
ID:19741 Are you sure that you want to delete all partitions? You will not be able to undo the operation.
ID:19742 Partition "<name>" cannot be preserved a snapshot later than "synthesized" because it contains Post-Fit Signal Tap connections.
ID:19743 The TCL command <command> is supported only by executable quartus_cdb
ID:19744 The given snapshot '<snapshot_name>' is missing for partition(s) in your design. Re-compile your design from original source files before export design.
ID:19746 The LVDS SERDES IP instance "<name>" does not have any valid input or output serial port connections.
ID:19749 VHDL error at <location>: formal port <string> has no actual or default value
ID:19750 VHDL error at <location>: formal generic <string> has no actual or default value
ID:19754 Point to point assignment not supported for value of "<Full clock region assignment string>" for the Clock Region Assignment.
ID:19755 Automatically applied size constraint on clock trees for periphery interfaces
ID:19756 <Clock tree name>
ID:19761 The SEU_ERROR output status is monitored but SEU error detection is not enabled
ID:19762 The SEU fault injection is allowed but SEU error detection is not enabled
ID:19763 The SEU internal scrubbing is enabled but SEU error detection is not enabled
ID:19764 Input port '<input_port>' has <number> <string> fanout(s). <string>:
ID:19765 <string>
ID:19766 Advanced SEU Detection data size is <number> bytes
ID:19767 Device has <number>% critical bits
ID:19768 <number>% device bits are design critical bits, with some bits shared across the <number> Advanced SEU Detection (ASD) regions.
ID:19769 <number>% device bits are critical for ASD region <number>
ID:19772 File "<name>" does not exist.
ID:19773 File "<name>" does not exist.
ID:19774 Recompile could not locate a design database from a previous compilation on disk. Perform a successful Full Compilation before requesting Recompile Analysis & Synthesis and make sure intermediate snapshot writes are enabled with Enable Intermediate Fitter Snapshots assignment.
ID:19775 Recompile does not support RTL changes for the currently specified family. Perform a Full Compilation.
ID:19776 PCS bonding group < <name> > with < <number> > channels is placed from a location without an adjacent PCIe HIP to a location with an adjacent PCIe HIP, which will cause hold time violation.
ID:19785 Reading entity-bound SDC constraints from a Partition Database File (.qdb): '<SDC File Name>'
ID:19786 Reading entity-bound SDC constraints from a Partition Database File (.qdb): '<SDC File Name>' for instance: '<Instance Name>'
ID:19789 Unable to create a clock tree that feeds all core and periphery destinations simultaneously.
ID:19790 Unable to create a clock tree that satifies region constraint of "<Region constraint>" and feeds all core and periphery destinations simultaneously for clock: "<Clock name>"
ID:19791 The "<qdb_filename>" Partition Database File is assigned to the "<partition>" design partition.
ID:19793 User defined partitions are not supported for the current device family.
ID:19794 No user-defined partition found in design. For a design with a QDB_FILE assignment applied to the root partition, there must be at least one user-defined reconfigurable design partition.
ID:19795 The "--exclude_pr_subblocks" flag is required when exporting a top-level partition (root_partition) with a Partial Reconfiguration flow. Either export the entire design or ensure that the "--exclude_pr_subblocks" flag is present in the command that exports the root_partition.
ID:19796 Node '<name>' output port '<output port>' depends on inputs '<expected input>', but has '<connected input>' connected
ID:19797 The following node of the above-mentioned region failed to pack: "<name>"
ID:19798 Cannot run synthesis on Partial Reconfiguration implementation revisions without specifying a correct QDB file partition assignment on the root (|) partition.
ID:19800 ENTITY_REBINDING <new_entity> is not assigned to a valid target <target>.
ID:19803 The QDB_FILE_PARTITION assignment <qdb_file> to target <target> is ignored.
ID:19806 Entity rebinding has been applied to partition "<partition>". The entity has been remapped from "<old_entity_name>" to "<new_entity_name>".
ID:19807 Design contains combinational loop of <number> nodes. The Timing Analzyer cannot estimate delays for such large loops, and all timing paths through this loop will be disabled.
ID:19808 Post-fitting acquisition clocks are not allowed. Please chose a pre-synthesis acquisition clock.
ID:19809 altera_syncram IP does not support the layout specified in the memory initialization file. If parameter <parameter1> is smaller than parameter <parameter2>, then parameter <parameter3> cannot be set to <parameter3_value>
ID:19810 Node "<name>" is dependent on port "<name>" which is not connected
ID:19812 You must select a valid pin for CONF_DONE in Configuration PIN. Click Configuration > Configuration Pin Options to open Configuration PIN dialog.
ID:19814 CONF_DONE pin is automatically set when changing the configuration scheme.
ID:19815 IOPLL "<IOPLL atom name>" coreclk input is selected as the refclk (use_core_refclk), but the coreclk input is disconnected.
ID:19816 For IOPLL "<IOPLL atom name>", <Number of outlks> outclks were exported, but one or more of these outclks is currently disconnected.
ID:19819 Partition '<partition_name>' has preservation level set to '<preserve_snapshot>', however, it imports a QDB_FILE_PARTITION '<qdb_name>' that contains snapshot '<qdb_snapshot>'.
ID:19822 For IOPLL "<IOPLL atom name>", the following parameter was set incorrectly : <Parameter name>. The IOPLL must be instantiated using Qsys, and the IOPLL IP files cannot be changed after generation.
ID:19824 A Preservation Level setting cannot be applied to the root partition. Remove the preservation assignment associated with the root partition before recompiling the design.
ID:19828 The compiled configuration mode <name> does not support multiple bitstreams
ID:19829 <qdb_file> cannot be assigned. The <qdb_file> file is missing Partial Reconfiguration or Reserved Core subpartitions and assigned to the root partition. In order to assign a QDB file to the root partition, it must be created from a design using Partial Reconfiguration or Reserved Core subpartitions. To correct this error, ensure that the creation and assignment of the QDB is correct.
ID:19831 Partition(s) is successfully created.
ID:19834 OTN channels represented by FPLL < <name> > have been placed in the same Tile along with PCIE HIP represented by < <name> > which will cause high jitter rate. Place these channels in a Tile with no PCIE.
ID:19838 A rectangle has been <operation> two or more regions.
ID:19844 Device <number> is a dummy bit in JTAG chain.
ID:19845 <name>
ID:19846 Rapid Recompile engaged for <number> of <number> partitions
ID:19847 You preserved or used a pre-compiled QDB file for partition "<emptied_partition>" ("<inst_name>") which has been previously emptied. Please remove the preservation setting or QDB_FILE_PARTITION assignment and recompile.
ID:19848 <name>
ID:19849 <name>
ID:19850 The source revision is not defined as PR_BASE or PR_IMPL revision type.
ID:19851 The source revision is missing PR partition assignments
ID:19852 The new revision type is not defined upon creation
ID:19853 The new revision type is not defined as implementation revision upon creation
ID:19854 Discovered explicitly defined initial values in Partition <partition_name>. Please refer to the %1!s Partition report folder for more information.
ID:19855 Cannot generate Programming File Generator Setup File (.pfg) for output file type <name>. The output file type can only be supported through the -c or --convert command option. Remove --save command option to avoid this warning.
ID:19856 Cannot generate programming file <name>
ID:19868 Design contains too many EMIF/PHYLite systems with unique logic connected to the debug interface port
ID:19874 External memory and PHYLite interfaces have only one debug toolkit when constrained to the same I/O column. The following IO_AUX/IOSSMs were constrained to the same column, and have a debug interface connected:
ID:19876 Can't open binary file "<name>"
ID:19877 Partial reconfiguration no longer supports synthesis revisions.
ID:19879 Reference clock pin < <name> > cannot be shared or connected to any other logic clock.
ID:19880 Option setting in SOF file is different with current option setting. Do you want to overwrite it?
ID:19881 "<partition type>" partition "<partition>" does not have "<assignment>" assignment.
ID:19882 Automatic debug logic insertion has failed.
ID:19886 Saving IP-XACT for "<org_filemane>" in "<xml_filename>"
ID:19887 Value '<value>' for assignment '<name>' is an invalid value and assignment is being ignored.
ID:19889 Could not find valid LAB location to facilitate routing of core global signal "<name>" near chip coordinates (<x>, <y>).
ID:19890 Rapid Recompile has determined that Fitter (<stage name>) can be skipped
ID:19891 Rapid Recompile has determined that Fitter (<stage name>) will run with Rapid Recompile
ID:19892 Rapid Recompile has determined that Fitter (<stage name>) requires a full compile (unable to re-use previous implementation results)
ID:19894 The "derive_pll_clocks" command was used in an auto-promoted entity SDC File: <SDC Location>
ID:19896 Registered carry chain of length <number> starting at cell "<name>" exceeds the maximum carry length of <number>
ID:19897 At least one specified <metatype> Metadata file was not exported to the generated Partition Database File (.qdb).
ID:19907 File not found: Verify that a Partition Database File (.qdb) exists at "<path>".
ID:19908 Directory not found: Verify that an extraction directory exists at "<path>".
ID:19909 Failed to create an extraction subdirectory at "<path>". Verify that the correct permissions are set on the parent extraction directory before relaunching this shell command.
ID:19910 Failed to copy files to the extraction subdirectory located at "<extract_dir>". Verify that the correct permissions are set on the parent extraction directory before relaunching this shell command.
ID:19920 Specified sector, frame, bit, or both are out of range.
ID:19921 Current design from device <name> does not support HPS bitstream - <name>
ID:19922 There is no metadata type that matches "<option>". A list of supported metadata types can be found in the "--extract_metadata" help text.
ID:19923 There is no Quartus Metadata option that matches "<option>".
ID:19925 The specified Partition Database File (.qdb) does not possess any <metatype> Metadata.
ID:19927 Parameter '<param_name>' is set with a 'set_parameter' command in the QSF but does not exist in the entity definition
ID:19928 Can't view binary file "<name>"
ID:19929 Please add the Partition Database file "<name>" in Design Partition Window.
ID:19930 Unable to create directory at: "<name>", check write permissions
ID:19934 Partition '<partition_parent>' cannot use a PRESERVE assignment because its child partition '<partition_child>' is imported as a Partition Database File. To fix this error, remove the preservation setting on partition '<partition_parent>' or remove the Partition Database File (QDB_FILE_PARTITION assignment) on child partition '<partition_child>'.
ID:19935 Partition Database File '<qdb_name>' was exported at a pre-synthesized snapshot '<snapshot>'.
ID:19936 Partition '<partition_name>' is assigned to a Partition Database File '<qdb_name>' that was exported at the '<qdb_snapshot>' snapshot. This partition also has a preservation setting of '<preserve_snapshot>'. The preservation setting must be removed or changed to a snapshot later than '<qdb_snapshot>'.
ID:19937 Partition '<partition_name>' is assigned to a Partition Database File '<qdb_name>' that was exported at the '<qdb_snapshot>' snapshot. This partition also has a preservation setting of '<preserve_snapshot>'. The Partition Database File '<qdb_name>' will be ignored and partition will be preserved at '<preserve_snapshot>' from the preserved results.
ID:19938 The "<snapshot>" snapshot is too early in the compilation flow to derive meaningful resource utilization statistics.
ID:19939 Could not find any resource utilization statistics for the "<partition>" partition during the "<snapshot>" snapshot.
ID:19941 QSF command 'set_parameter' can only apply to the top-level design and cannot include '-to' or '-entity' arguments.
ID:19942 The following clock trees are routing to a region that overlaps the failing signal. To reduce congestion try disabling promotion or providing clock region constraints for clocks in this region.
ID:19943 Additional global routing demand includes these signals:
ID:19945 Illegal programming mode specified for trace log. Specify JTAG mode for trace log.
ID:19946 Target device at device index <number> does not support trace log.
ID:19947 File not found: Verify that a User Metadata configuration file exists at "<path>".
ID:19948 Unexpected path "<token>" found on line <line_number> of the User Metadata configuration file. No more than two paths are allowed to appear on each line of a User Metadata configuration file.
ID:19949 The destination path "<path>" does not represent a directory. All destination paths in the User Metadata configuration file must be relative directory paths.
ID:19950 The destination path "<path>" is not a relative path. All destination paths in the User Metadata configuration file must be relative directory paths.
ID:19951 Failed to copy one or more User Metadata files from the source path "<src_path>" to the destination path "<dst_path>". Verify that the source path exists and the correct permissions are set on the source path before including this line in a User Metadata configuration file.
ID:19952 The path "<path>" does not represent a file or a directory. Change the suffix of the specified path such that it represents either a file (i.e., no trailing "/" or "...") or a directory (i.e., a trailing "...").
ID:19953 The path "<path>" is illegal. The use of "." or ".." directories in a source or destination path is prohibited. Sources can be specified as absolute paths to include files outside of the current directory hierarchy. Destinations require the extraction directory to be in the current hierarchy.
ID:19954 Device <number> does not support for external scrubbing
ID:19955 Quartus Prime is unable to infer placement of Signal Tap instance "<instance>". Signal Tap instance "<instance>" will be placed within partition "<partition>".
ID:19957 Clock trees are sized automatically to reach fan-out locations from Early Placement. To see the current fan-out placement, locate any of the signals below in Chip Planner, and use the Generate Fan-Out Connections command.
ID:19958 User-defined initial register values cannot be respected in the "Disable Register Power-up Initialization" flow; please refer to the synthesis report panel "Registers with Explicit Power-Up Settings" for partition "<partition_name>" for more details.
ID:19959 Fitter has early exit during placement as the design is too difficult to route with <number>%% peak congestion
ID:19960 ATX PLL < <name> > is being used in GT mode. The adjacent master CGB < <name> > cannot be used. Please use x1 clock line or make location assignments in QSF for PLL < <name> >.
ID:19961 Your design contains IP components that must be regenerated and run through synthesis. To regenerate your IP, use the upgrade IP Components dialog box, available on the Project menu in the Quartus Prime software.
ID:19962 Your design contains IP components that must be regenerated and run through synthesis. To regenerate your IP, use the upgrade IP Components dialog box, available on the Project menu in the Quartus Prime software.
ID:19963 You must upgrade the IP component instantiated in file <instance> to the latest version of the IP component.
ID:19964 You must upgrade the IP component instantiated in file <instance> to the latest version of the IP component.
ID:19965 <design_name> with version <design_version> is outdated.
ID:19966 <design_name> with version <design_version> is outdated.
ID:19967 <note>
ID:19968 <note>
ID:19970 The cs_hwevents_fpga port in the hps_interface_jtag WYSIWYG is deprecated. Regenerate your HPS IP or HPS Signal tap IP
ID:19971 Partial reconfiguration or Reserved Core partition "<emptied_partition>" ("<inst_name>") can not be emptied.
ID:19972 Parent partition "<emptied_partition>" ("<inst_name>") has one or more hierarchical children, therefore, it cannot be assigned as EMPTY. Either remove the EMPTY assignment on the partition, or remove the PARTITION assignment on all its hierarchical children.
ID:19973 Child partition "<emptied_partition>" ("<inst_name>") can not be emptied. Its parent is preserved or has a Partition Database File (.qdb) assignment.
ID:19974 The top-level design partition "|" can not be emptied.
ID:19978 The input data at temporary directory <qdb_path> from unarchiving input QDB file does not have version-compatible data models.
ID:19979 The input data at temporary directory <qdb_path> from unarchiving input QDB file does not have required <model> data model.
ID:19980 Failed to extract your input QDB file <qdb_file>. Make sure your input QDB file was exported with "--compatible" option from the same or older version of the software and there is enough disk space.
ID:19981 Failed to convert the version-compatible QDB file <qdb_file> to current version. Make sure your input QDB file was exported with "--compatible" option from the same or older version of the software and there is enough disk space.
ID:19982 Failed to archive converted QDB model files to <qdb_file>. Make sure you have the permission and enough disk space to write the file.
ID:19983 Successfully converted <in_qdb_file> to <out_qdb_file>.
ID:19988 The following signals overlap the failing region, but were not yet routed:
ID:19989 SDM_IO <number> has conflicting assignments of <name> and <name>
ID:19990 The atom port definition has changed for "<atom_name>" (id:<atom_id>) in the current version of Quartus Prime software. The following port has been removed from the design.
ID:19991 The atom port definition has changed for "<atom_name>" (id:<atom_id>) in the current version of Quartus Prime software. The port "<port_name>" is in use and cannot be removed from the design. The database cannot be restored to this version of Quartus Prime.
ID:19992 The imported file does not contain a full design. Use this import option only for an exported full design
ID:19993 "<port_name>"
ID:19995 The atom port definition has changed for "<atom_name>" (id:<atom_id>) in the current version of Quartus Prime software. The following ports have been removed from the design.
ID:19996 The ENTITY_REBINDING assignment is on an invalid target "<target>". The assignment cannot target on a pre-compiled partition.
ID:19998 RAM '<name>' of size <number> bits is larger than the maximum size possible on device (max <number>).
ID:19999 HIP < <name> >'s PIN_PERST_N pin cannot be inverted.
ID:20000 Overriding device family setting <name> -- part <name> belongs to device family <name>
ID:20001 Ignored setting <name> -- value "<name>" is illegal. Refer to --help for legal values.
ID:20002 Character <name> is illegal
ID:20003 Directory "<name>" does not exist
ID:20004 Your design targets the device family "<name>". The specified family is not a valid device family, is not installed, or is not supported in this version of the Quartus Prime software. If you restored a project from an archived version, your project was successfully restored, but you still must specify or install a supported device family.
ID:20005 Cannot compile your design for one of the devices in the <name> family of devices. A license file is required
ID:20006 Ignored <name> section -- assignment <name> will be made in the <name> section
ID:20007 Assignment to <name> currently not supported -- assignment requires a target
ID:20008 Assignment to <name> currently not supported -- this assignment requires a source and a destination node
ID:20009 Can't make assignment <name> -- no assignment value specified
ID:20010 Can't make assignment <name> -- assignment is not supported
ID:20011 Can't make assignment <name> -- device "<name>" is illegal
ID:20012 Can't import assignments in Quartus Prime Settings File <name>
ID:20013 Ignored <count> assignments for entity "<name>" -- entity does not exist in design
ID:20014 Assignment for entity <name> was ignored
ID:20015 Project contains unresolved partitions
ID:20016 Unresolved partition "<name>"
ID:20017 Can't continue with atom netlist from Incremental Synthesis (quartus_map --incr_synth) without first completing design by running Partition Merge (quartus_cdb --merge).
ID:20018 Device family <name> is not supported by the EDA formal verification tool <name> in combination with the selected synthesis tool
ID:20019 Synthesis netlist optimization gate-level register retiming is not supported by Formal Verification tool <name>
ID:20020 Physical Netlist Optimization Register retiming is not supported by Formal Verification tool <name>
ID:20021 Timing-Driven Synthesis is not supported by Formal Verification tool <name>
ID:20022 SDC constraint protection is not supported by Formal Verification tool <name>
ID:20023 Physical Synthesis for combinational logic is not supported by Formal Verification tool <name>
ID:20024 Physical Synthesis tool <name> is not supported by Formal Verification tool <name>
ID:20025 Project "<name>" does not exist
ID:20026 Invalid assignment for NUM_PARALLEL_PROCESSORS: <setting>
ID:20027 Cannot detect the number of processors available - disabling parallel compilation
ID:20028 Parallel compilation is not licensed and has been disabled
ID:20029 Only one processor detected - disabling parallel compilation
ID:20030 Parallel compilation is enabled and will use <num_procs_used> of the <num_procs_detected> processors detected
ID:20031 Parallel compilation is enabled for <num_procs_used> processors, but there are only <num_procs_detected> processors in the system. Runtime may increase due to over usage of the processor space.
ID:20032 Parallel compilation is enabled and will use up to <num_procs> processors
ID:20034 Auto device selection is not supported for <name> device family. The default device, <name>, is set.
ID:20035 The QDB_FILE_PARTITION assignment, PRESERVE assignment, or EMPTY assignment is assigned to an invalid non-partition target "<target>".
ID:20036 IO bank < <name> > has GT channel with data rate > 26.6G, so the bank can have up to 4 GX/GT channels due to jitter performance implication.
ID:20037 This version of the EDA Netlist Writer does not support System Verilog output with the simulation tool. Use the --help=format command option to see supported simulation output formats.
ID:20038 Instance "<hpath>" instantiates entity "<name>" cannot be elaborated because it has the same name as the top-level entity.
ID:20042 File <text> is not a valid binary file
ID:20044 The serial pin <name> for the LVDS SERDES IP instance <serdes_inst> must be pulled up to the top level and cannot fanout to anything else.
ID:20045 Can't find the stub file for /"<qdb_file>/".
ID:20046 Parent partition "<emptied_partition>" ("<inst_name>") cannot be assigned as EMPTY, because it has the following child partition or partitions:
ID:20047 Child partition "<child_partition>" ("<inst_name>")
ID:20050 The "<partition>" partition is assigned to an entity that does not have any ports. Verify that the entity associated with the "<instance>" instance defines at least one port before recompiling the design.
ID:20051 All partitions in the design are imported or preserved.
ID:20053 Can't initialize Timing Analyzer (quartus_sta) with given command.
ID:20054 Channel < <name> > has rsfec enabled, < <name> > is not a legal rsfec location, < <name> > are possible rsfec locations.
ID:20055 IO bank < <name> > has GXT channels, the bank can have up to 4 GX/GXT channels due to jitter performance implication.
ID:20056 Logic module atom "<name>" has its "<name>" port connected to a non-register source: "<name>".
ID:20059 MIF file '<mif_name>' specified in RAM initialization assignment could not be found.
ID:20060 The snapshot "<snapshot>" is invalid.
ID:20061 Can't generate test bench files -- select a valid simulation tool
ID:20062 The device type in your input QDB file ("<family1>" "<device1>") does not match the device type in your project setting file ("<family2>" "<device2>").
ID:20063 The I/O standard High Speed Differential I/O cannot be assigned to the reference clock < <name> > of IO PLL.
ID:20064 Error status: <text>
ID:20065 Partition Database File '<qdb_name>' is not compatible with the current software version. Use 'quartus_cdb --convert_partition' command to convert it for reuse.
ID:20066 Transceivers and PLLs placed inside these IO Banks < <name> > needs to use the same power supply voltage. IPs are using < <name> > power supplies.
ID:20067 Preserved_partition <name> compilation results will not be archived. To preserve the compilation database files, use Advanced Archive Settings.
ID:20068 Configuration error, you must power-cycle the device to recover from this condition. To avoid this error you must ensure that the device is configured within 18 seconds after completion of the power-on sequence.
ID:20069 USE PWRMGT_SCL output pin, USE PWRMGT_SDA output pin and USE PWRMGT_ALERT output pin must be all configured together.
ID:20070 Transceivers PAM4 channels < <name> > must be placed at locations starting with even index.
ID:20073 "<name>" is one of the multiple drivers.
ID:20075 The permit_cal input port of IOPLL "<Downstream IOPLL atom name>" is not connected correctly. Enable and export the permit_cal port of downstream IOPLL "<Downstream IOPLL atom name>" with the Platform Designer GUI and connect to the locked output of upstream IOPLL "<Upstream IOPLL atom name>"
ID:20076 The extclk output of IOPLL "<IOPLL atom name>" is connected to virtual pin "<Extclk destination name>". IOPLL extclk outputs can not connect to virtual pins.
ID:20077 The following global signals each drive HSSI as well as UIB and/or ESRAM interfaces, which have specialized global routing requirements that cannot be satisfied simultaneously. Revise the design to have separate global signals for these interfaces.
ID:20078 <name>
ID:20079 The input pipeline register of dynamic control input "<parameter value>" of the DSP block WYSIWYG primitive "<name>" is enabled without having input pipeline register enabled or it is using different clock enable source as the input pipeline register.
ID:20080 The second pipeline register of dynamic control input "<parameter value>" of the DSP block WYSIWYG primitive "<name>" is enabled without having second pipeline register enabled or it is using different clock enable source as the second pipeline register.
ID:20081 Ensure that the input registers for all used ports of the DSP block WYSIWYG primitive "<atom name>" are either enabled or disabled.
ID:20082 Input pipeline register for DSP block WYSIWYG primitive "<atom name>" can only be enabled when (1) Pre-adder and/or Internal coefficient feature and input register and output register are used, OR (2) Input register and second pipeline register are used, OR (3) Input register, second pipeline register and output register are used.
ID:20083 Second pipeline registers for DSP block WYSIWYG primitive "<atom name>" can be enabled only under one of the following conditions: An input register is used; Neither the pre-adder feature or the internal coefficient feature are not used but both an input register and an output register are used; An input register and an input pipeline register are used; An input register, an input pipeline register, and an output register are used.
ID:20084 When SYSTOLIC mode is used, please ensure all the input registers for the used ports of DSP block WYSIWYG primitive "<atom name>" are always enabled.
ID:20085 The parameter "<parameter value>" of DSP block WYSIWYG primitive "<atom name>" should be set to "no_reg" when port <port name> is a constant value or disconnected.
ID:20086 The port <port name> for DSP block WYSIWYG primitive "<atom name>" is currently connected to VCC. This signal will be fed to a register which is susceptible to any clear signal from the CLR[0] input port.
ID:20087 When ACCUMULATE port is used and input pipeline register is enabled, accum_pipeline_clken for the DSP block WYSIWYG primitive "<atom name>" must be set as the same value as input_pipeline_clken.
ID:20088 When LOADCONST port is used and input pipeline register is enabled, load_const_pipeline_clken for the DSP block WYSIWYG primitive "<atom name>" must be set as the same value as input_pipeline_clken.
ID:20089 When ACCUMULATE port is used and second pipeline register is enabled, accum_2nd_pipeline_clken for the DSP block WYSIWYG primitive "<atom name>" must be set as the same value as second_pipeline_clken.
ID:20090 When LOADCONST port is used and second pipeline register is enabled, load_const_2nd_pipeline_clken for the DSP block WYSIWYG primitive "<atom name>" must be set as the same value as second_pipeline_clken.
ID:20091 Programming public key on device <number>
ID:20092 When CHAINOUT port is connected, the output register of DSP block WYSIWYG primitive "<atom name>" must be enabled before input registers.
ID:20093 Programmable pre-emphasis option is set to <number> for pin <name>, but setting is not supported by I/O standard <name> with Slew Rate <number>
ID:20094 Error at <location>(<number>): Name "<name>" is invalid. Avoid using "|", "*", and "~" in instance name.
ID:20095 Importing Logic Lock region routing constraints from "<name>" for entity "<name>"
ID:20096 Can't import Logic Lock region assignments -- Quartus Prime Settings File <name> is read-only
ID:20097 Import completed. <name> assignments were written (out of <name> read). <name> non-global assignments were skipped because of entity name mismatch.
ID:20098 The specified filename "<name>" does not have a .QSF extension. You will not be able to import this file.
ID:20099 Export completed. <name> of <name> non-Logic Lock assignments and <name> of <name> Logic Lock Regions were exported.
ID:20100 The Import options specified require that the design be elaborated
ID:20101 If IOPLLs "<merged IOPLL atom>" and "<merged IOPLL atom>" merge, the design becomes non-routable. To rotate the ports, manually combine these IOPLLs or turn off automatic IOPLL merging.
ID:20103 Removed <name> from device index <number> after reconfiguration.
ID:20104 Added <name> at device index <number> after configuration succeeded.
ID:20105 Attempting to place "<name>" with IO standard "<name>" and termination "<name>" in a 3V IO bank which does not support termination. The following locations are affected:
ID:20106 Unable to change the visibility for the Logic Lock region named "<name>"!. <reason>.
ID:20109 This information is not available for clocks defined using a list of edges.
ID:20110 Auto-generation of IP "<ip_name>" for instance "<inst_name>" failed. See previous errors for reason/mitigation.
ID:20138 The following imported or preserved partitions have conflicting Row Clock usage: <partition>. Use Logic Lock regions to constrain all preserved partitions to non-overlapping Row Clock Regions.
ID:20139 <partition>.
ID:20140 <cell>
ID:20141 Started reading Signal Activity File <name>
ID:20142 Finished reading Signal Activity File <name>
ID:20143 Signal Activity File <name> is specified, but the file was not found
ID:20144 Signal Activity File <name> is specified but was not found. No signal activity will be used.
ID:20145 Attempting to read Signal Activity File <name>, but the file could not be opened
ID:20146 Expected keyword <name> was not found
ID:20147 Expected keyword <name>, but instead found keyword <name> on line number <number>
ID:20148 Illegal keyword <name> found on line number <number>
ID:20149 Invalid format found on line <number>
ID:20150 Invalid float value found on line <number>
ID:20151 Unsupported file format version found on line <number>
ID:20152 Expected to find keyword <name>, but instead found end of file at line <number>
ID:20153 Created Signal Activity File <name>
ID:20154 Attempting to write to Signal Activity File <name>, but the file could not be opened
ID:20155 Invalid signal flag definition
ID:20156 Invalid signal flag name "<name>"
ID:20157 Duplicate definition for signal flag "<name>"
ID:20158 Integer value "<number>" assigned to flag name "<name>" is not a power of two
ID:20159 Signal Activity File defines signal flag "<name>" with the same value as a previously defined signal flag
ID:20160 Signal Activity File contains invalid flag mask "<number>" with undefined bits "<number>"
ID:20161 Signal Activity File contains a <type> user assignment to a node, but the node has already been assigned by the user.
ID:20162 Signal Activity File contains invalid flag mask "<number>". This mask contains multiple sources for either static probability or toggle rate.
ID:20163 Power input file setting is applied to invalid entity name "<name>"
ID:20164 Power input file setting is missing a VCD or signal activity file name
ID:20165 Cannot apply VCD File Start and End Time Settings to Signal Activity File "<name>"
ID:20166 Importing gate level simulation results for entities other than the top level may result in name mismatches if incremental compilation was not used
ID:20167 VCD File parser will not perform glitch filtering because device family <name> does not support it
ID:20168 Starting conversion of VCD file <name> to TBL file <name>
ID:20169 Finished conversion of VCD file <name> to TBL file <name>
ID:20170 Starting scan of VCD file <name> (<name> to <name>) for signal static probabilities and transition densities
ID:20171 Finished scan of VCD file <name> (<name> to <name>) for signal static probabilities and transition densities
ID:20172 VCD Reader start time cannot be greater than end time
ID:20173 VCD file <name> was not found
ID:20174 VCD file <name> was not found. No VCD file will be used.
ID:20175 Parse error in VCD file <name> near line <name>
ID:20176 VCD file <name> has an invalid upscope command on line <name>
ID:20177 VCD file "<name>" has an invalid EVCD command on line <name>
ID:20178 EVCD file "<name>" has an invalid VCD command on line <name>
ID:20179 Can't parse VCD file "<name>"
ID:20180 VCD file timestamps are not in sequential order on line <name>
ID:20181 The permit_cal input port of IOPLL "<Downstream IOPLL atom name>" is not connected correctly. Enable and export the permit_cal port of downstream IOPLL "<Downstream IOPLL atom name>" with the Platform Designer GUI and connect to the locked output of upstream IOPLL "<Upstream IOPLL atom name>"
ID:20186 <msg>.
ID:20189 Atom '<name>' (atom id: <id>): has an illegal arithmetic lutmask. The lutmask should be of form <format>
ID:20190 Access permission denied for assignment "<string>" value "<string>" when accessing the specified file. Check for file write permission if file exists, or directory write and access permission if file does not exist.
ID:20192 Inferred optimized multiplier from the following logic: "<name>"
ID:20193 Applied dense packing to "<name>". Area: <number> LABs / <number> ALMs. Logic density: <number>.
ID:20194 Access to flash interface is denied. Potential errors: <text>
ID:20196 Location(s) already occupied and the components cannot be merged.
ID:20198 This action may significantly increase memory usage.
ID:20200 Can't extract user files to "<path>"
ID:20201 User files are extracted to <path> successfully.
ID:20202 The script based Partial Reconfiguration compilation flow is no longer supported. The <flow name> flow script will not be generated. Please use the simplified Partial Reconfiguration compilation flow
ID:20203 Multiple modes assigned to OCT. OCT "<name>" is assigned modes "<name>" and "<name>", but each OCT can only have one mode. Remove extra OCT block mode assignments.
ID:20205 Incompatible IO standard combination for OCT. OCT "<name>" is assigned IO standards "<name>" and "<name>", but IO Standard "<name>" can only be calibrated with IO standard "<name>" in the same block.
ID:20206 Conflicting IO standards assigned to buffers calibrated by the same OCT. OCT "<name>" is attempting to calibrate IO standards "<name>" and "<name>", but each OCT can only calibrate one IO standard. Remove extra OCT IO standard assignments.
ID:20207 More than two Rs impedances assigned to OCT. OCT "<name>" is assigned Rs impedances "<name>", "<name>", and "<name>". Remove extra OCT Rs impedance assignments.
ID:20208 More than two Rt impedances assigned to OCT. OCT "<name>" is assigned Rt impedances "<name>", "<name>", and "<name>". Remove extra OCT Rt impedance assignments.
ID:20213 <name> <logical width>x<logical depth> is not supported in RAM blocks "<atom name>" when ASIC_PROTOTYPING .qsf assignment is set to ON.
ID:20214 The address width <logical width> bit is not supported in LUTRAM blocks "<atom name>" when ASIC_PROTOTYPING .qsf assignment is set to ON.
ID:20215 Router estimated peak <length> interconnect demand : <percent>% of <direction> directional wire in region <location> to <location>
ID:20216 The largest congested region has <number> grid units of <string> wire in the <string> direction
ID:20217 (<number>, <number>) has <number> % utilization
ID:20218 <name> must be as same <name> when ASIC_PROTOTYPING .qsf assignment is set to ON.
ID:20219 True dual port RAM or ROM, '<ramname>', cannot be implemented as LUTRAM. Setting RAM type to 'AUTO'
ID:20222 One or more registers failed to be packed into a DSP bank because they are identified as synchronizers. For more information on synchronizer identification, refer to the Managing Metastability section of the Design Recommendations User Guide.
ID:20223 Read address register '<reg>' has been absorbed into RAM '<ram>' and its power up value of <val> cannot be guaranteed.
ID:20224 Reading entity-bound SDC constraints from a Partition Database File (.qdb): '<SDC File Name>' for instance: '<Instance Name>' from '<QDB File Name>'
ID:20225 To use the <register parameter name> register in the DSP block WYSIWYG primitive "<atom name>", you must enable the <register parameter name> register(s).
ID:20226 Intel Quartus Prime software has encountered an unexpected error. Partition "<hpath>" contains an output port, "<port>" that is driving a Hyper-Register.
ID:20227 Intel Quartus Prime software has encountered an unexpected error. Partition "<hpath>" contains an input port, "<port>" that is driving a Hyper-Register.
ID:20228 The design contains inconsistent routing graphs. This can be caused by importing two or more preserved partitions with overlapping routing or global signals.
ID:20229 Time spent reading SDC file <SDC file name>: <elapsed time>
ID:20231 Input port <name> on the atom <inst>, is not connected to a valid source.
ID:20232 Automatically pupolute latest signing settings from <name> to <name>.
ID:20233 Automatically inherit signing settings from <name> to <name>.
ID:20234 Failed to add <sofname> that contains bitstream of <soffamily> device. The existing SOF contains bitstream of <targetdevice> device and it does not support cross family cascaded bitstream.
ID:20235 Could not find file '<Filename>'<Source of filename>.
ID:20236 Could not read/parse file '<Filename>'<Source of filename>.
ID:20237 Changed value of parameter '<Parameter>' from '<Old value>' to <New value>', atom <Atom name> (<Atom type>).
ID:20238 Port <port> on clock gate <node> cannot be driven by clock gate <node>.
ID:20240 Unused transceiver channel(s) corresponding to the following pins have been preserved: <name>
ID:20241 The exported partition preserved the following global signals. These signals may cause routing conflicts in team-based design and bottom-up compilation flows.
ID:20242 <hpath>.
ID:20243 QIP file "<name>" does not exist
ID:20244 The PR POF ID could not be recovered.
ID:20245 <string> has already run successfully. Do you want to run the task and possibly prerequisite tasks again?
ID:20246 Device family <name> not supported
ID:20247 <text>
ID:20248 Preserved <partition_type> partition '<partition_name>' is missing one or more wire LUT(s). Ensure the given partition was marked as a <partition_type> partition during initial compilation.
ID:20249 Coherent Read is not supported in RAM blocks "<atom name>" when ASIC_PROTOTYPING .qsf assignment is set to ON.
ID:20250 ECC is not supported in RAM blocks "<atom name>" when ASIC_PROTOTYPING .qsf assignment is set to ON.
ID:20251 Ignoring global SDC file located at "<filename>".
ID:20252 Ignoring SDC file "<filename>" which belongs to the "<library>" IP.
ID:20253 This project includes Synopsys Design Constraint (.sdc) files that will not be exported to the Partition Database File (.qdb). Only entity-bound SDC files that affect the exported partition will be included in the QDB file.
ID:20254 Failed to find a valid thermal solution for the given 'POWER_THERMAL_SOLVER_MODE' at the specified operating conditions.
ID:20257 Failed to find a valid thermal solution for a +/-5 degree junction temperature offset. The failing solution will not be shown in the temperature and cooling report.
ID:20259 Command-line arguments missing <name> option
ID:20260 Internal registers cannot be used in DSP block WYSIWYG primitive "<atom name>" when ASIC_PROTOTYPING .qsf assignment is set to ON.
ID:20261 Coefficient mode cannot be used in DSP block WYSIWYG primitive "<atom name>" when ASIC_PROTOTYPING .qsf assignment is set to ON.
ID:20262 Cannot add unrecongnized bitstream to device chain when in current programming mode
ID:20263 Placement failed to find a legal solution for <number> LABs, <number> M20Ks and <number> DSPs in the locations from (<number>, <number>) to (<number>, <number>).
ID:20264 Placement failed to find a legal solution due to row legality failure.
ID:20265 Estimated peak <length> <direction> directional wire demand : <percent>% in region <location> to <location>
ID:20266 Exporting a database file with the '<snapshot>' snapshot is not supported.
ID:20267 The HPS Handoff information generated by the HPS IP component in Platform designer was not found.
ID:20271 <port name> in <block name> block "<atom name>" need to be set to "none" when ASIC_PROTOTYPING .qsf assignment is set to ON.
ID:20273 Intermediate fitter snapshots will <state> because <reason> during compilation.
ID:20274 Successfully committed <snapshot_name> database.
ID:20276 Secure Partial Reconfiguration Mask will not be generated because the current license file does not support this feature.
ID:20277 The bitstream that generated by Quartus Prime software v18.0 or earlier will no longer be available on the device after you program the root key (*.qky) of the target device. Do you want to continue the operation?
ID:20278 WYSIWYG declaration error at line <location>: "<entity_name>" has name "NULL", which is a reserved word. Rename your WYSIWYG.
ID:20279 Rapid Recompile could not locate a design database from a previous compilation on disk. Perform a successful Full Compilation before requesting Rapid Recompile and make sure intermediate snapshot writes are enabled with the Enable Intermediate Fitter Snapshots assignment.
ID:20280 FPLL REFCLK select node < <name> > has no clock source.
ID:20282 One or more devices configured in the device chain do not support the reconfiguration with factory SDM helper image. Do you want to skip the reconfiguration and continue the operation?
ID:20283 Blank-checking fuses on device <number>
ID:20284 Examining fuses on device <number>
ID:20285 Verifying public key on device <number>
ID:20286 The family "<family>" specified in the Root Partition Database file "<qdb>" is not a valid family. Please select a Root Partition Database file with a valid family.
ID:20287 The device "<device>" specified in the Root Partition Database file "<qdb>" is not a valid device. Please select a Root Partition Database file with a valid device.
ID:20288 The Fitter could not convert one or more RAM instances into MLABs automatically because auto MLAB conversion requires the Read-During-Write mode set to Don't Care. Change the Read-During-Write mode to Don't Care in the affected RAMS. Alternatively, to keep the current Read-During-Write mode, change the RAM type to MLAB instead of AUTO. For information on which RAM instances are affected, refer to the 'Fitter RAM Summary' table in the Fitter Report.
ID:20289 One or more devices have been configured in the device chain. Are you sure you want to reconfigure the configured devices with <name>?
ID:20290 Unable to change the Route Reserved property for the Logic Lock region named "<name>" to <value>. <reason>
ID:20292 The instance hierarchy path "<hpath>" specified by a "<assignment>" assignment does not match any partition in the design. Specify a valid partition hierarchy path for this assignment.
ID:20293 Depromoted clock that drives split fanout in PR partition: "<pr partition name>" on node ("<atom name>"). Depromoted clock: ("<clock name>")
ID:20294 EXPORT_PARTITION_SNAPSHOT_FINAL cannot be used on hierachical path "<hpath1>" because it also has a QDB_FILE_PARTITION or PRESERVE assignment targetting on.
ID:20295 EXPORT_PARTITION_SNAPSHOT_FINAL cannot be used on hierachical path "<hpath1>" because its <relationship> partition hierachical instance "<hpath2>" has QDB_FILE_PARTITION or PRESERVE assignment targetting on.
ID:20296 The cell named <name> with ID <id> is (partially) placed. Choose an unplaced cell.
ID:20297 Cascading IOPLL "<Illegally placed IOPLL name>" was placed between IOPLLs of a different cascade pair ("<Upstream cascaded IOPLL>","<Downstream cascaded IOPLL>"). It is not possible for cascading IOPLL pairs to be interleaved. Constrain IOPLL locations so that there are no IOPLLs between other cascading IOPLL pairs.
ID:20298 Created raw binary file of QSPI programming helper image <name>
ID:20300 WYSIWYG LCELL_COMB primitive "<name>" cannot use carry-out or sum-out when extended mode is on.
ID:20301 Node "<name>" is dependent on port "<name>" which is not connected
ID:20302 Programmer cannot recognize the bitstream. Do you want to continue to attach the bitstream to the target device in current programming mode?
ID:20304 Programmer cannot recognize the bitstream in the programming file you specified. You can use --force option to give authorization to continue configure the target device if this is your intention.
ID:20305 Target device at device index <number> does not support root key file (.qky), encryption key file (.qek), fuse file (.fuse), and compact certificate (.ccert) programming.
ID:20306 FPLL REFCLK source < <name> > is not routed.
ID:20311 Size of file(s) in partition <partition> exceeds memory capacity. The file requires end at address <required_end_address>, however, the available end address is <actual_end_address>
ID:20312 WYSIWYG declaration error at line <location>: "<entity_name>" has name "<wys_name>" that already exists in the design. Choose an unique name for the WYSIWYG instance.
ID:20313 Byte enable width of <width> on RAM '<ram_name>' port <port_name> is invalid for the selected family. This may prevent the RAM from being inferred.
ID:20314 Invalid collection filter: <Collection filter>
ID:20315 Note that the router may use short wires to implement long connections at higher delay
ID:20316 Select at least one optimization mode.
ID:20318 Missing PR POF ID for partition <name>
ID:20319 Incorrect number of delay arguments specified in the set_edge_delay command.
ID:20320 The set_edge_delay command cannot be used to create a new edge to or from a keeper.
ID:20321 The Quartus Prime Software could not perform auto discovery for entity "<entity>", possibly defined in "<file>". If the definition is correct, add the design file with a global assignment in the QSF file
ID:20322 Fractal sub-design "<name>" is too big. Skip dense packing.
ID:20323 Conflicting global signal device requirements detected: Destination port "<iterm name>" on node ("<atom name>")
ID:20324 Instance "<hpath>" cannot be set as Entity Re-binding. The Entity Re-binding assignment is only valid for instances that exist on Partial Reconfiguration or Reuse Core Partitions imported with the QDB_FILE_PARTITION assignment.
ID:20325 <name>
ID:20326 <name>
ID:20327 <name>
ID:20329 This Error has been downgraded to Warning: Block "<atom name>" is configured to use address width <logical width> bit which does not support Readback/Writeback for ASIC Emulation flow.
ID:20330 This Error has been downgraded to Warning: Block "<atom name>" is configured to use <name> <logical width>x<logical depth> which does not support Readback/Writeback for ASIC Emulation flow.
ID:20331 This Error has been downgraded to Warning: Block M20K is configured to use unequal <name> and <name> which does not support Readback/Writeback for ASIC Emulation flow.
ID:20332 This Error has been downgraded to Warning: Block "<atom name>" is configured to use mode Coherent Read which does not support Readback/Writeback for ASIC Emulation flow.
ID:20333 This Error has been downgraded to Warning: Block "<atom name>" is configured to use mode ECC which does not support Readback/Writeback for ASIC Emulation flow.
ID:20334 This Error has been downgraded to Warning: Block "<atom name>" is configured to use clocked internal register which does not support Readback/Writeback for ASIC Emulation flow.
ID:20335 This Error has been downgraded to Warning: Block "<atom name>" is configured to use mode Coefficient which does not support Readback/Writeback for ASIC Emulation flow.
ID:20336 This Error has been downgraded to Warning: Block "<atom name>" is configured to use registered <port name> which does not support Readback/Writeback for ASIC Emulation flow.
ID:20339 The Quartus Prime software does not support exporting version-compatible database for the top-level partition (root_partition). To export the full design, you can execute quartus_cdb with --export_design or select Export Design from Project menu.
ID:20340 The product of the -multiply_by/-divide_by options for generated clock '<Clock Name>' and its ancestors results in a value larger than the maximum allowed. This clock will be ignored.
ID:20341 A process is currently running and must be stopped before closing the window
ID:20343 Failed to sign the bitstream. <reason>
ID:20344 Failed to add Quartus Root Key File <file> to Programmer. The file is corrupted.
ID:20347 Failed to authenticate the bitstream. Please verify the bitstream is signed with the correct key.
ID:20348 Non-volatile key programming mode is selected. However, this feature is not supported by Intel Stratix 10 device at device index <number>.
ID:20351 Fail to execute function <name> in file <name>
ID:20352 Failed to <operation> the bitstream through python script <file>
ID:20353 <name>
ID:20354 Fail to execute file <name>
ID:20355 <reason>
ID:20357 Partial reconfiguration region PMSF file "<name>" was generated in an older Quartus version and is missing required information. Regenerate the PMSF file with the current version of the Intel Quartus Prime software.
ID:20358 Failed to generate PR bitstream.
ID:20359 Global signal "<clock>" that feeds port "<port>" on partition "<partition>" does not have a clock region constraint.
ID:20360 <wirelut_count> wire LUT(s) were inserted to tie-off unconnected <port_type> partition boundary ports in the design.
ID:20361 A large number of wire LUT(s) were inserted for unconnected <port_type> partition boundary ports in the design. This may result in increased logic utilization and reduced design performance.
ID:20367 Unable to perform region <name> security mask verification. Reference SMSF file "<name>" could not be located.
ID:20368 One or more registers required for periphery IP timing closure are constrained by an unsupported placement constraint. Remove location constraints from the registers listed in the Submessages, and ensure that any Place Region or Clock Region constraints fully cover the periphery interface these registers connect to. Refer to submessages for a list of affected registers.
ID:20369 List of registers constrained to region with bottom-left corner (<number>, <number>) and top-right corner (<number>, <number>): (Only the first 10 registers are listed)
ID:20370 <name>
ID:20371 The destination is read-only and its global setting cannot be changed
ID:20372 Unable to remove at least one member from the region -- <reason>
ID:20373 In Logic module atom "<name>", the "<name>" parameter is enabled, but the "<name>" port is not connected. Either disable the parameter or connect the port.
ID:20374 Cannot generate SMSF files for partial reconfiguration design because the current license file does not support this feature.
ID:20375 Invalid connection in output port "<IOPLL output port name>[<IOPLL output port bit index>]". In IOPLL "<IOPLL instance name>" instances, lvds_clk and loaden output ports can only connect to an LVDS Serdes IP.
ID:20376 This design has enabled bitstream verification. To generate programming file from partially-masked SRAM Object (.pmsf) file for a PR region use the Quartus Programmer, and include the region verification (.smsf) file from base compile.
ID:20377 Unable to save assignments. <reason>
ID:20378 Unable to change the visibility for the Logic Lock region! <reason>
ID:20379 Time borrowing was specified for non-latch node(s), for example <Node> - will be ignored on such nodes
ID:20380 Unable to read database file "<name>". Database error: <text>.
ID:20381 Unable to read database file from stream.
ID:20382 Verifying fuses on device <number>
ID:20383 Programming fuses on device <number>
ID:20386 Revision name "<new_revision>" conflicts with the existing revision name "<existing_revision>". Choose a different name.
ID:20387 The specified file <name> contains root key information (.qky). However, the programming file is not signed because signing feature is disabled.
ID:20388 The <Constraint> constraint has no effect, based on your current project configuration, and will be ignored
ID:20389 Two or more set_max_time_borrow assignments apply to the same latch(es). Later assignments will override earlier ones.
ID:20390 The signing feature is enabled. However, programming file is not signed because the specified file <name> does not contain root key information (.qky)
ID:20392 Unable to write databases to stream.
ID:20393 The design has enabled authentication. It must also have ENABLE_PR_POF_ID option ON.
ID:20394 Can't open the parameter editor because a process is currently running.
ID:20395 xN line from IO < <name> > to IO < <name> > have different voltage supplies.
ID:20396 Run synthesis before executing the "Update Memory Initialization File" command.
ID:20397 Created <type> file <name>
ID:20398 Failed to create <type> file <name>. <reason>
ID:20399 Failed to parse <type> file <name>. <reason>
ID:20400 Unable to write to database file "<name>". Database error: <text>.
ID:20401 Maximum attempts at opening a temporary file in directory "<directory>" for database writing has been exceeded.
ID:20402 Maximum attempts at getting a temporary filename for database writing in directory "<directory>" has been exceeded.
ID:20404 Failed to add <file> to Programmer. The file is corrupted.
ID:20409 AHDL <flie> is not supported for the selected family (<family>)
ID:20410 Hardware frequency is auto-adjusted to <frequency>
ID:20411 PR and/or EDCRC usage detected. To ensure reliable operation of these features on the targeted device, certain device resources must be disabled.
ID:20412 You must create a floorplan assignment to block out the unusable device resources at row Y=59 to ensure reliable operation with PR and/or EDCRC. Use the Logic Lock Regions Window to create an empty reserved region, or add "set_instance_assignment -name EMPTY_PLACE_REGION "X0 Y59 X<number> Y59-R:C-empty_region" -to |" directly to your Quartus Settings File. Also review any existing Logic Lock regions that overlap that row to ensure they account for the unusable device resources.
ID:20413 Failed to parse <type> file <name>. <reason>
ID:20414 Synthesis found <number> latches and converted <number> from LUT to HiPI implementation.
ID:20416 Failed to parse <type> file <name>. <reason>
ID:20417 The file "<string>" is imported by the QDB_FILE_PARTIITON assignment but is also specified for exporting the synthesized or final snapshot. Choose different file names to save exported partitions.
ID:20419 Hardware frequency is auto-adjusted to <frequency>
ID:20420 Hardware frequency is auto-adjusted to <frequency>
ID:20422 Multiple partitions specify the file name "<string>" to export the synthesized or final snapshot. Choose different file names to save exported partitions.
ID:20423 The implementation of the following bidirectional port is split across partitions: "<hpath>".
ID:20424 A set_max_time_borrow -exact assignment of <Assignment Value> for "<Assignment Target>" at <Assignment SDC Source> exceeds the maximum physically possible borrow amount in at least one case. For example, it is not possible to borrow more than <Max Possible Borrow Example> at <Example Node> for clock <Example Clock Domain>, <Example Corner>. In all such cases, the borrow amount will be limited to what is possible on the device.
ID:20425 Attempted to fit <Number of IOPLL subtype 1 merge groups> <IOPLL subtype 1> IOPLL merge groups into <Number of IOPLL subtype 1 locations> locations. There are <Number of free subtype 2 locations> free <IOPLL subtype 2> IOPLL locations remaining.
ID:20426 At least one level-sensitive latch in the design has a negatively-sized latching window, making it impossible for it to function as a latch and potentially leading to metastability. For example, negative slack of <Negative Slack> in the latching window at <Example Node> for clock <Example Clock Domain>, <Example Corner>.
ID:20428 When OTU2e/2 is used with band 0/1, need 7 spacing. Otherwise space 5. Refer to OTN UG for more information. ATX PLL < <name> >, ATX PLL < <name> >
ID:20429 Failed to generate compilation reports. Please ensure you have enough disk space.
ID:20430 Failed to generate compilation reports for the <stage> stage. Please ensure you have enough disk space.
ID:20431 Failed to add <file> to Programmer. The file contains root key information (.qky). However, Programmer does not support bitstream signing feature. You can use Programming File Generator to convert the file to the signed Raw Binary File (.rbf) for configuration.
ID:20432 The file <file> contains root key information (.qky). However, Programmer does not support bitstream signing feature. You can use Programming File Generator to convert the file to the signed Raw Binary File (.rbf) for configuration.
ID:20433 Interface Planner failed to start : <error_str>.
ID:20434 The Timing Analyzer is analyzing <number of hard latches> hard latches. For more details, run the Check Timing command in the Timing Analyzer.
ID:20435 Pin <name> is assigned with I/O STANDARD <iostd> other than 1.8V I/O Standard.
ID:20437 '<text - value entered>' is not a valid value for property <text - property>. Please re-enter.
ID:20439 Failed to save flash into database.
ID:20440 Failed to delete flash from database.
ID:20442 Write denied for assignment "<string>" value "<string>" when accessing the specified file. Check for file write permission if file exists, or directory write and access permission if file does not exist.
ID:20444 This design is signed, and the HPS Debug Access Port (DAP) has been enabled. No integrity claim could be made with HPS DAP enabled. After usage, this generated bitstream should be properly disposed and preferably, its signing key should be cancelled to guarantee no open access for the silicon. The options to enable HPS DAP will have different behavior in future releases.
ID:20445 The reference clock on PLL "<name>", which feeds an LVDS SERDES IP instance, is not driven by a clock pin from an IO bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.
ID:20447 Parameter "<param>" is set to "<value>" on module "<module>" by Partition Database File (.qdb) "<flie>".
ID:20448 Atom "<name>" is part of a carry chain that forms a loop. Please disconnect and reconnect the carry out of one of the atoms in the chain.
ID:20451 <text - title of tab> tab has invalid property values.
ID:20452 Action '<text - action's name>' in <text - title of tab> tab has invalid property values.
ID:20454 -- '<text - value entered>' is not a valid value for property <text - property>.
ID:20456 Database files were created using version "<prev_version>" of the Quartus Prime software. The current version is "<curr_version>"
ID:20457 Deprecated entity:instance collection filter pattern matches <Collection type>s: <Filter>
ID:20458 <Object name>
ID:20459 The bitstream encryption is not supported on current device
ID:20460 Logic module atom "<name>" in position "<number>" of the propagate carry chain has an invalid propagate tie off property.
ID:20461 The <type> <name> is corrupted. <reason>
ID:20462 Missing key storage option or the specified value is illegal. Refer to --help=key_storage for legal key storage value.
ID:20464 ECO: Node with name <node name> cannot be found in the netlist.
ID:20465 ECO: Could not find WYSIWYG port <port name> on node <node name>.
ID:20466 ECO: Output signal with name <oterm> cannot be found in the netlist.
ID:20467 Avalon Memory-Mapped Interface "<text>" must connect to at least one valid input port of another Transceiver component.
ID:20473 Device name '<name>' is invalid as it contains either an empty string or special characters.
ID:20474 Device name '<name>' is invalid as it conflicts with the reserved name for the programming flow template.
ID:20475 Device name '<name>' is invalid as it already exist in the device database.
ID:20476 Device I/O voltage '<name>' is invalid.
ID:20477 Device ID '<name>' is invalid. It either contains an empty string or special characters, or it is not in the list of byte formats.
ID:20478 Device density '<name>' is invalid.
ID:20479 Total device die '<number>' is invalid.
ID:20481 Programming flow template '<name>' is invalid.
ID:20482 Found duplicate flash device names '<name>' in the <path> directory.
ID:20483 Evaluation of ECO TCL script failed.
ID:20485 Action name '<name>' is invalid as it contains an empty string or special characters.
ID:20486 Action command '<name>' is invalid. It either contains an empty string or special characters, or it is not in the list of byte formats.
ID:20494 Action data mask '<name>' is invalid. It either contains special characters or is not in the list of byte formats.
ID:20495 Action expected data '<name>' is invalid. It either contains special characters or is not in the list of byte formats.
ID:20496 Action data '<name>' is invalid. It either contains special characters or is not in the list of byte formats.
ID:20497 Action data length '<name>' is invalid. It either contains an empty string or special characters, or has a value of 0.
ID:20498 Action attempt count '<name>' is invalid. It either contains an empty string or special characters, or has a value of 0.
ID:20499 Action erase size '<name>' is invalid. It either contains an empty string or special characters, or has a value of 0.
ID:20500 Action delay '<name>' is invalid. It contains either an empty string or special characters.
ID:20501 Action page size '<name>' is invalid. It either contains an empty string or special characters, or has a value of 0.
ID:20502 Action address '<name>' is invalid. It contains either an empty string or special characters.
ID:20503 Action addressing mode '<name>' is invalid. It either contains an empty string or special characters, or has a value of 0.
ID:20504 Action dummy clock cycle '<name>' is invalid. It contains either an empty string or special characters.
ID:20505 Action bus width '<name>' is invalid.
ID:20507 Action custom direction '<name>' is invalid.
ID:20509 Action custom description '<name>' is invalid due to an empty string.
ID:20510 Failed to parse the user XML file '<name>' in the <path> directory.
ID:20511 <plugin module>: <message>
ID:20512 <plugin module>: <message>
ID:20513 <plugin module>: <message>
ID:20514 Cannot load <plugin module> plugin object. The specific plugin object is not loadable.
ID:20515 Cannot find <path>. Make sure the file is located at the expected location.
ID:20516 Cannot find <function> function in <plugin module> plugin object.
ID:20517 Maximum number of attempts allowed to create a directory "<directory>" for database writing has been exceeded.
ID:20519 '<assignment_str>' assignment is not supported for the Intel Agilex device family.
ID:20520 QDB_FILE_PARTITION assignment is supported only in Partial Reconfiguration flow for the Intel Agilex device family.
ID:20521 The input refclk of IOPLL <IOPLL instance name> is driven by an illegal source: <Refclk source name>. An IOPLL refclk's source must be either another IOPLL or a dedicated refclk input pin.
ID:20524 Imported Partition '<partition_name>' has type '<imported_type>' but it is specified as '<user_specified_type>' in the current project.
ID:20526 SOF <name> for device <name> is compiled with HPS First configuration order option. The CvP feature will be disabled.
ID:20527 Cannot retrieve encryption key from <path>. Make sure the encryption key file (*.qek) is valid and you enter the correct passphrase.
ID:20528 Target device <device> at index <index> does not support fuse examination.
ID:20529 Specify a entity for Synopsys Design Constraints File with entity binding
ID:20530 Design Partition Planner can't locate the specified object.
ID:20531 <text>
ID:20532 Snapshot "<snapshot>" is not supported for the Report DRC dialog. The following snapshots are supported: <supported_snapshot>
ID:20535 Flash device I/O voltage '<name>' is incompatible with the selected FPGA device family.
ID:20536 Programming file generation feature has been removed from the compilation flow and the corresponding legacy settings in the Intel Quartus Prime Setting File (.qsf) have been ignored: <list>. Use Programmer File Generator or Convert Programming File tool to generate a programming file.
ID:20537 Failed to add <file> to Programmer. The programming file was generated with bitstream encryption option enabled. You must use the Programming File Generator to convert the file to an encrypted Raw Binary File (.rbf) for configuration.
ID:20539 Cannot finalize the encryption for the file <name> because it was compiled with the bitstream encryption option disabled.
ID:20540 <SDC Assignment> (located at <SDC Location>)
ID:20543 Device dummy clock cycle '<number>' is invalid.
ID:20544 Following options "<option1>" must be exclusive to each other for a successful file generation.
ID:20545 Created <helper_type> programming helper image RBF file <helper_rbf>
ID:20546 The routing element at location "<child_location>" is being sourced by routing elements at locations "<parent_location_1>" and "<parent_location_2>". This can be caused by importing two or more preserved partitions with overlapping routing or global signals.
ID:20547 The design contains inconsistent routing graphs. This can be caused by importing two or more preserved partitions with overlapping routing or global signals.
ID:20548 Current module <name> terminated because of lack of memory. Verify that you have sufficient memory available to compile your design. You can view disk space and physical RAM requirements on the System and Software Requirements page of the Intel FPGA website (https://fpgasoftware.intel.com/requirements/).
ID:20549 Current module <name> was unexpectedly terminated by signal <signal_number>. This may be because some system resource has been exhausted, or <name> performed an illegal operation. You can view system resource requirements on the System and Software Requirements page of the Intel FPGA website (https://fpgasoftware.intel.com/requirements/).
ID:20552 The width of port <port name> for DSP block WYSIWYG primitive "<atom name>" should match the value given by the parameter <parameter name>.
ID:20553 Using <name> Hash <name>
ID:20554 You have specified <odd_memory_word_size> odd size of memory words in Altera Syncram IP. Altera Syncram IP does not allow odd size memory words and auto corrected to <even_memory_word_size> memory words.
ID:20555 Initializing <text> at device index <number>
ID:20556 Terminating <text> at device index <number>
ID:20557 The SRAM Object File <name> is signed, and the HPS Debug Access Port (DAP) has been enabled. No integrity claim could be made with HPS DAP enabled. After usage, this generated bitstream should be properly disposed and preferably, its signing key should be cancelled to guarantee no open access for the silicon. The options to enable HPS DAP will have different behavior in future releases.
ID:20560 Failed to update the device database in the <path> directory.
ID:20561 IOPLL <IOPLL name> could not be placed in location <Location name> becuase this location cannot be used by IOPLLs using <Feature name>.
ID:20562 Device family does not support board-level IBIS output file generation.
ID:20569 The imported design contains illegal routings. Recompile your design in the latest version of the Intel Quartus Prime software.
ID:20572 Fast Preservation cannot be enabled if intermediate Fitter snapshots are being committed. Intermediate snapshots were committed because <reason> during compilation.
ID:20577 Encryption key verify operation is selected. However, this feature is not supported by Intel Stratix 10 device at device index <number>
ID:20578 You have specified <odd_memory_word_size> odd size of memory words in altera_syncram IP. altera_syncram IP does not allow odd size memory words and auto corrected to <even_memory_word_size> memory words.
ID:20580 Imported Partition '<partition_name>' has type '<imported_type>' but it is not specified in the current project.
ID:20581 Cannot find a valid Memory Initialization File to process.
ID:20582 Cannot find the Memory Initialization File <name>. Skipped updates for this file.
ID:20583 Processed the following Memory Initialization File(s):
ID:20584 Processed Memory Initialization File <name>
ID:20585 The file <name> was compiled with the bitstream encryption feature enabled but the encryption finalization option is not enabled.
ID:20586 The <type> partition "<partition_name>" does not have <llr_assignment> assigned to it, or the assignment is turned off.
ID:20587 HSSI clock port "<text>" of these nodes "<text>" can be shared to reduce clock congestion.
ID:20588 The specified file "<name>" for programming bitstream authentication cannot be located.
ID:20589 This design has enabled programming bitstream encryption. You must also enable authentication by specifying a valid QKY file
ID:20591 The following global signal has special routing requirements for its periphery interfaces and cannot use a sector-level gate: <clock_name>
ID:20592 Performed hierarchical tree duplication for <number> register chains on partition "<name>". <number> register chains could not be duplicated. See "Hierarchical Tree Duplication" report for details.
ID:20593 The sign later option is enabled but the file <name> does not contain root key information (.qky).
ID:20594 Cannot skip bitstream encryption finalization for the file <name> because it was compiled with the bitstream encryption option disabled.
ID:20595 The generated bitstream for the file <name> will only be partially encrypted.
ID:20596 The generated bitstream for the file <name> will not be signed.
ID:20597 Are you sure that you want to delete all report panels? This action cannot be undone.
ID:20599 A valid 'External Memory Interface for HPS Intel Agilex FPGA IP' component is required when using the EMIF conduit in HPS - Add a HPS-EMIF IP component or, if you do not intend to use the EMIF component, set the HPS AXI slave interface 'Enable/Data width' to Unused and disable the 'EMIF_CONDUIT_Enable'.
ID:20600 The HPS_EMIF handoff information generated by the EMIF IP component in Platform Designer has an illegal HPS DDR width: <number>. HPS DDR width must be chosen from 16, 32 or 64 bits if engaged in Agilex devices.
ID:20608 The <type> partition "<partition>" does not have the <assignments> assigned to it, or the assignment is turned off.
ID:20609 I/O Standard value "<name>" for pad "<name>" is not supported for OCT.
ID:20612 <feature> is not enabled.
ID:20613 An invalid option is set for get_collection_info when called for <Collection Type> collection type. This collection type supports only -type and -size options.
ID:20615 Use the Reset Release IP in Intel Stratix 10 FPGA designs to ensure a successful configuration. For more information about the Reset Release IP, refer to the Intel Stratix 10 Configuration User Guide.
ID:20617 A valid Quartus key file must be supplied to enable bitstream encryption.
ID:20618 Invalid Quartus key file. Please correct the file path or remove the entry.
ID:20619 Global signal "<signal name>" with no physical fanout is not routed.
ID:20620 There are <number> set of 3V I/Os. The device can have only <number> sets of 3V I/Os.
ID:20621 3V I/O <text> has <number> enable signals and is locked at pins <text> of the same 3V I/O set. Only two enable signals are allowed.
ID:20622 <text> are a set of 3V I/Os that allow two different enable signals.
ID:20623 Unable to create project database files because the source file "<filename>" cannot be located.
ID:20624 <text> inputs are driven by two different nodes <text>, <text>.
ID:20625 Channels <text> are PMA bonding. These channels must be constrained in a continuous location.
ID:20626 Channels <text> are PCS bonding. They must be constrained to a continuous location.
ID:20627 Exporting <snapshot> database...
ID:20631 WYSIWYG LCELL_COMB primitive "<name>" in extended mode needs DATAH to be connected.
ID:20634 Your imported design has been fully compiled. Running Intel Quartus Prime software Fitter (quartus_fit) on such design data is not supported.
ID:20636 Parameter <parameter> can only be set to <parameter_value> for device family <device>.
ID:20637 The <type> boundary port "<hpath>" is unused. Partial Reconfiguration and Root Partition Reuse guidelines recommend that all reconfigurable or reserved core partition ports be used in the base revision compile, to ensure good timing driven placement of logic on the path.
ID:20638 Maximum warning count for dangling <type> boundary ports exceeded.
ID:20639 Invalid source-level "<assignment>" assignment.
ID:20641 The Entity <file_type> file "<filename>" has been modified since the compilation started. Intel Quartus Prime software is copying the new file into the database.
ID:20642 Unable to create project database files because the Entity <type> source file cannot be located: "<filename>".
ID:20643 Unrecognized configuration device <name>. If this is a custom-defined configuration device, ensure that you have set the correct custom database directory.
ID:20644 Unrecognized configuration device <name>. If this is a custom-defined configuration device, ensure that you have set the correct custom database directory.
ID:20645 Cannot place <name> in bank <name> because bank used for placement can place only a maximum of four LVDS SERDES channels in soft-CDR mode.
ID:20647 Cannot recognize the flash device <name> that is attached to the device index <number>. If this is a custom-defined flash device, ensure that you have set the correct custom database directory.
ID:20649 Clock signal <name> has an invalid maximal routing length constraint: <max_routing>. The maximal routing length must be a non-negative integer.
ID:20650 Pin "<name>" is requesting termination but it is not linked to an explicitly instantiated OCT. Fitter will attempt to automatically group with other OCTs or create new OCT if necessary.
ID:20651 Parameter(s) <parameter name> for DSP block WYSIWYG primitive "<atom name>" must be <value> when <atom setting condition>.
ID:20652 Failed to add <sofname>. The target device <targetdevice> does not support programming files with multiple bitstreams.
ID:20653 <msg>
ID:20654 EDA Netlist writer does not support power simulation option for the tool <tool> and the format <format>.
ID:20656 Target device at index <index> does not support Black Key Provision feature.
ID:20658 <Message String>
ID:20659 Maximal routing length constraint <max_routing> is not supported for the following clock signal routing into separate clock trees: <name>
ID:20660 An EMIF IP's reference clock network spans <Number of tiles> adjacent I/O banks due to placement constraints. Reference clock networks can span at most eight I/O banks.
ID:20661 <Message String>
ID:20662 Thermal solver is not currently supported for the selected device and family.
ID:20663 There is no Intel Quartus Prime software metadata option that matches "<option>".
ID:20664 File not found: Verify that a Partition Database File (.qdb) exists at "<path>".
ID:20665 Directory not found: Verify that an extraction directory exists at "<path>".
ID:20666 The specified Partition Database File (.qdb) does not possess any <metatype> metadata.
ID:20667 Failed to create an extraction subdirectory at "<path>". Verify that the correct permissions are set on the parent extraction directory before relaunching this shell command.
ID:20668 Failed to copy files to the extraction subdirectory located at "<extract_dir>". Verify that the correct permissions are set on the parent extraction directory before relaunching this shell command.
ID:20669 More than one Rs impedances assigned to a single calibration of an SSTL/POD OCT. OCT "<name>" with calibration "<name>" is assigned Rs impedances "<name>" and "<name>". Remove the extra OCT Rs impedance assignments.
ID:20670 More than one Rt impedances assigned to a single calibration of an SSTL/POD OCT. OCT "<name>" with calibration "<name>" is assigned Rt impedances "<name>" and "<name>". Remove the extra OCT Rt impedance assignments.
ID:20672 For HSSI E-tile, there is no path between HSSI REFCLK and core. HSSI REFCLK divider "<text>" has core fanouts.
ID:20673 Template name '<name>' is invalid as it contains either an empty string or special characters.
ID:20674 Template name '<name>' is invalid as it conflicts with the reserved name for the programming flow template.
ID:20675 Template name '<name>' is invalid as it conflicts with existing device name in the device database.
ID:20676 Template name '<name>' is invalid as it already exist in the template database.
ID:20686 Convert Programming Files support for the target device <name> will be defeatured in the future. Please use Programming File Generator to generate the programming file for the target device for long-term.
ID:20687 Convert Programming Files does not support the target device <name>. Please use Programming File Generator to generate the programming file for the target device.
ID:20688 Unable to load <name>. See the System tab of the Messages window for more details.
ID:20692 The Intel Quartus Prime software is unable to create the directory "<dirname>".
ID:20693 The Intel Quartus Prime software is unable to move the directory "<source>" to "<destination>".
ID:20694 The Intel Quartus Prime software is unable to remove the directory "<dirname>".
ID:20695 The Intel Quartus Prime software is unable to remove the file "<dirname>".
ID:20696 <Message String>
ID:20697 Initialize Interface Planner before running command
ID:20698 The node <name> is in the design file. Update the top-level design file after deleting.
ID:20699 Open project before running command in Interface Planner
ID:20701 OCT "<name>" is instantiated, but not used. Remove unused OCTs from the design.
ID:20702 The \'Enable device security using a volatile security key\' option has been disabled. The operation will perform real eFuses programming and this is an irreversible operation. Do you want to continue the operation?
ID:20703 OCT "<name>" is connected to "<name>", which is not an I/O buffer. OCTs can only be connected to I/O buffers.
ID:20705 I/O buffer node "<name>" has port "<name>" connected, but does not use calibrated on-chip termination.
ID:20706 The default IO Standard "<assignments>" is no longer valid. The default IO Standard has been updated to "<assignments>".
ID:20709 Instance assignment 'PRESERVE_UNUSED_XCVR_CHANNEL' is specified with invalid transceiver pin location(s)
ID:20712 Pin location <text> is not a valid transceiver location and will be ignored.
ID:20713 Atom "<atom name>" has clear port tied off when clear signal is enabled
ID:20714 OCT "<name>" requests I/O standard "<name>" and Rt resistance "<name>", but this I/O standard only supports Rt resistance "<name>".
ID:20715 The programming file integrity check failed. <reason>
ID:20716 Invalid argument "<info>" specified for the assignment.
ID:20718 Serial Vector Format file (.svf) generation for the target device <name> is not supported. Please use Jam STAPL file (.jam or .jbc) for the target device for long-term.
ID:20719 Command <Command name> requires a single set of operating conditions to be selected.
ID:20720 Multiple clock assignments are selected. Only one clock assignment can be <text> at a time.
ID:20721 No open project exists
ID:20723 Are you sure that you want to delete the selected clock assignment(s)? You will not be able to undo the operation.
ID:20724 No dedicated path available for refclk signal, <Refclk name>. Please indicate in the IOPLL Parameter Editor that this IOPLL refclk is a global clock.
ID:20727 The design contains Partial Reconfiguration or Reserved Core partitions with unused input ports. Intel recommends to assign unused inputs within the partition to registers with the synthesis noprune attribute.
ID:20728 The input port <port> is dangling on partition <partition>.
ID:20731 For HSSI pin "<text>", I/O standard "<text>" is the only legal value.
ID:20732 I/O pin "<text>" is a GPIO, but "<text>" has no GPIO resource.
ID:20733 Automatically applying the floorplan "<floorplan>" to the whole design for selected device: <device>
ID:20734 Fast Preservation will not be enabled while performing an Incremental Optimization flow.
ID:20735 The bus '<new_bus>' has member '<member_name>' whose name overlaps with a member in bus '<old_bus>'. Provide unique names for your buses and their members.
ID:20737 Bus '<old_bus>' originally declared here.
ID:20739 In altera_syncram Intel FPGA IP core, set parameters <parameter name> and <parameter name> to the same value when you have set <operation mode name> to <operation mode value> for <device family> device family.
ID:20740 The 'Hard Processor System Intel Agilex FPGA IP' component and HPS-EMIF IP component has inconsistent settings with respect to the EMIF DQ width: <number>. The 'HPS EMIF DQ width' defined in the HPS component must match the EMIF component 'DQ width' to ensure correct configuration.
ID:20741 Sending certificate to device index <number>
ID:20742 WYSIWYG RAM primitive "<name>" must have the "<name>" port and "<name>" port connected to the identical clock source with identical clock unateness.
ID:20743 WYSIWYG RAM primitive "<name>" cannot have parameter "<name>" set to "<name>" when using coherent read mode.
ID:20746 The "<type> <new_value>" assignment specified on the target "<target>", which belongs to a Partial Reconfiguration or Reserved Core partition, does not match the imported value "<preserved_value>". The assignment is ignored.
ID:20747 Cannot merge CPA instance <name> with the SERDES IP instances placed in the same bank.
ID:20749 System process ID: <number>
ID:20750 System process ID: <number>
ID:20751 Slew Rate logic option is set to <number> for pin <name>, but the option is not supported by I/O standard <name> in GPIO mode.
ID:20752 Programmable de-emphasis option is set to <name> for pin <name>, but the option is not supported by I/O standard <name>.
ID:20756 Importing partition "<partition_name>" that was compiled with device:"<partition_part_name>", which does not match the current device:"<project_part_name>".
ID:20759 Use the Reset Release IP in Intel <device string> FPGA designs to ensure a successful configuration. For more information about the Reset Release IP, refer to the Configuration User Guide.
ID:20760 Output directory "<outputdirectory>" doesn't exists. Please specify a valid output directory.
ID:20762 QSF instance assignment source or target '<target>' uses an escaped identifier containing a colon (':'). If this is a VHDL name corresponding to a 'generate' construct, note that as of Intel Quartus Prime software version 19.3, such names use period ('.') instead of colon. Replace this escaped identifier with the new instance name, which does not need to be escaped.
ID:20763 Opening '<name>' requires closing '<name>'
ID:20773 No location of type <text> was found on the device.
ID:20774 Defaulting to skew computation without high-accuracy CCPP as there are <Number of Paths> paths within a single skew constraint, which exceeds the internal limit of <Number of Paths Limit>.
ID:20776 Register <name> is targeted with a <assignment> assignment, but also has an incompatible core location constraint. Remove at least one of these assignments.
ID:20777 Register <name> is targeted with both FORCE_HYPER_REGISTER_FOR_PERIPHERY_CORE_TRANSFER and FORCE_HYPER_REGISTER_FOR_CORE_PERIPHERY_TRANSFER assignments. A core register can only be implemented as a Hyper-Register for a single periphery transfer. Remove at least one of these assignments.
ID:20780 Current device family does not support Rapid Recompile. NOTE: Rapid Recompile requires 'Enable Intermediate Fitter Snapshots' to be ON for full compilation.
ID:20782 Rapid Recompile database does not exist. Run a full compilation. NOTE: Rapid Recompile requires 'Enable Intermediate Fitter Snapshots' to be ON for full compilation.
ID:20783 Open Drain option is set to 'ON' for pin <name>, but setting is not supported by I/O standard <name>.
ID:20784 Bus-hold option is set to 'ON' for pin <name>, but setting is not supported by I/O standard <name>.
ID:20785 Weak pull-up option is set to 'ON' for pin <name>, but setting is not supported by I/O standard <name>.
ID:20792 REFCLK "<text>" mixes high frequency (>500MHz) and low frequency inputs.
ID:20794 To force an SDM clock to the Internal Oscillator, you must specify the Internal Oscillator on the General menu.
ID:20795 To disable HPS debug, you must disable the HPS debug access port (DAP) on the Configuration menu.
ID:20796 When you disable eFuses for encryption key storage, you must specify Battery Backup RAM or Physical Unclonable Function option for the Encryption Key Storage Select parameter on the Security menu.
ID:20797 When you disable Battery Backup RAM for encryption key storage, you must specify the eFuses or Physical Unclonable Function option for the Encryption Key Storage Select parameter on the Security menu.
ID:20798 The exported Reconfigurable or Reserved Core partition "<partition>" should only be reused in the same Partial Reconfiguration implementation context, along with the same root_partition as this compile.
ID:20799 Cannot <child_assignment> partition "<pname>" with a snapshot later than Synthesized when the root partition is not <parent_assignment> with a Final snapshot.
ID:20800 Fast Preservation will not be enabled for <family> device family.
ID:20802 Design contains combinational loop that has more than <Number of Paths> paths. Approximating delays through the loop.
ID:20803 The following nodes are in an invalid ALM configuration after applying ECO modifications:
ID:20804 Node <name>
ID:20805 Unable to query host CPU information. Certain optimizations may be disabled.
ID:20806 The host CPU may not be supported in future versions of the Intel Quartus Prime software. Intel recommends that you upgrade to a more recent processor that supports SSE 4.2 and the POPCNT instruction.
ID:20807 Automatic Gated Clock Conversion is enabled, but no clocks are explicitly identified and this family does not support automatic clock recognition during synthesis. Add "<assignment name>" assignments targeting each base clock.
ID:20808 The clock input "<clock_port>" to the preserved partition "<partition>" was compiled with the clock region "<previous_clock_region>", which is different than the current clock region "<current_clock_region>". This may cause timing closure problems.
ID:20809 Can't generate programming file <name> - <error>.
ID:20810 ECO command failed: <command>.
ID:20811 There are <number> elements of <name>. There are only <number> on the device.
ID:20812 To force an SDM clock to the Internal Oscillator, you must specify the Internal Oscillator as configuration clock source
ID:20813 To disable HPS debug, you must disable the HPS debug access port (DAP).
ID:20814 When you disable eFuses for encryption storage, you must specify Battery Backup RAM or PUF option for the Encryption Key Select.
ID:20815 When you disable Battery Backup RAM for encryption key storage, you must specify the eFuses or PUF option for the Encryption Key Select.
ID:20816 Clock <clock_name> is constrained to sectors <bbox_desc> but it must drive destination <dest_name> which is outside the constrained region.
ID:20818 When you force encryption key update, you must specify the Encryption Update Ratio.
ID:20819 Unsupported input file type (<name>). Use "--help=i" option to display supported input file type(s).
ID:20820 ECO: Unable to modify lutmask on node <node name>.
ID:20821 ECO: Failed to process ECO command at line <script name> of TCL script <line number>.
ID:20822 ECO: Cannot make connection from <source signal> to <dest node> because they are not in the same partition.
ID:20823 ECO: Cannot remove the connection because the path from <source signal> to <dest signal> does not exist.
ID:20824 ECO: Cannot remove the connection with Hyper-Registers on the path.
ID:20825 ECO: The specified node <node> does not have a LUT mask.
ID:20826 ECO: Cannot make changes to global signal <node>.
ID:20827 ECO: Invalid LUT mask value <lutmask>.
ID:20830 ECO: Cannot make routing changes on dedicated connections from <oterm> to <iterm>.
ID:20831 ECO: Cannot tie the specified input port to <vcc_gnd>.
ID:20832 ECO: Cannot change the <IO_Setting> setting on a node that is not an <direction>.
ID:20833 ECO: The specified Current Strength value is invalid.
ID:20834 When you enable the CvP setting, you must make sure design is CvP capable.
ID:20835 Design is ready for CvP.
ID:20836 Preserved <partition_type> partition '<partition_name>' is missing one or more wire LUT(s). Ensure that the given partition is marked as a <partition_type> partition during initial compilation.
ID:20837 The loaded file has changed and Programmer updated the file. Do you want to continue the operation?
ID:20838 Starting a flow requires closing the Snapshot Viewer. Do you want to close the Snapshot Viewer and proceed?
ID:20839 Starting a flow requires closing the Snapshot Viewer. Do you want to close the Snapshot Viewer and proceed?
ID:20840 An illegal value <number> is specified for <name> tamper detection.
ID:20841 When the HPS EMIF is used in x16 or x32 modes (with or without ECC), bank 2L can only be used for LVDS without DPA and without CPA engaged or for FPGA GPIO. <text> are found at bank 2L.
ID:20843 Current device family does not support Fitter ECO Compile.
ID:20846 The entity name "<entity>" specified on the assignment "<assignment> does not exist in the design".
ID:20847 IO <text> is locked at a HIP location. But it is not connected to any HSSI design element.
ID:20848 Partition "<partition_name>" was generated with device:"<partition_part_name>", which does not match the current device:"<project_part_name>" set in this project. Regenerate the partition in a project with the device set to "<project_part_name>".
ID:20850 Partition "<partition_name>" was generated with device:"<partition_part_name>", which does not match the current device:"<project_part_name>" set in this project. Either ensure the snapshot of partition "<partition_name>" is of type SYNTHESIZED or regenerate the partition in a project with the device set to "<project_part_name>".
ID:20851 Partition "<partition_name>" was generated with device:"<partition_part_name>", which does not match the family of the current device:"<project_part_name>" set in this project. Ensure the device family of the partition matches the device family of the project or regenerate the partition in a project with the device set to "<project_part_name>".
ID:20853 Cannot change device part from <originalPart> to <newPart> after using a non-final snapshot. To use the requested part, close and reopen the Intel Quartus Prime software and create the timing netlist with the required part.
ID:20854 Rename imported partition from "<old_pname>" to "<new_pname>". This may create a pmsf file name mismatch during Quartus Assembler Stage.
ID:20856 '<file name>' has been modified. Do you want to save your changes?
ID:20858 <text>
ID:20862 The specified device "<partition_name>" is either not installed or not allowed with the current software license.
ID:20863 There are "<number of siblings>" partial reconfiguration partitions under "<partition name of encompassing pr region>". Bitstream verification does not support more than "<maximum supported number of pr child partitions>" partial reconfiguration partitions.
ID:20864 There are "<pr hierarcy depth>" levels of partial reconfiguration partitions. Bitstream verification does not support more than "<maximum depth>" levels.
ID:20867 OCT cannot calibrate across different IO columns. Ensure that: \t\t1) All buffers requesting OCT are connected to an explicitly instantiated OCT. \t\t2) Buffers connected to the same OCT are not location-constrainted to different columns. \t\t3) The OCT and the buffers are not pin-constrained to different columns.
ID:20868 The ENABLE_RUNTIME_MOD LPM_HINT is no longer used to enable the In-System Memory Content Editor. Please refer to the RAM_1PORT and ROM_1PORT IPs to generate a memory suitable for use with ISMCE.
ID:20869 The ENABLE_RUNTIME_MOD LPM_HINT is no longer used to enable the In-System Memory Content Editor. Please refer to the RAM_1PORT and ROM_1PORT IPs to generate a memory suitable for use with ISMCE.
../../msgs/msgs/yncsetdq_prompt_to_save_changes_with_cancel.htm
ID:20871 The ENABLE_RUNTIME_MOD LPM_HINT is no longer used to enable the In-System Memory Content Editor. Please refer to the RAM_1PORT and ROM_1PORT IPs to generate a memory suitable for use with ISMCE.
ID:20872 The ENABLE_RUNTIME_MOD LPM_HINT is no longer used to enable the In-System Memory Content Editor. Please refer to the RAM_1PORT and ROM_1PORT IPs to generate a memory suitable for use with ISMCE.
ID:20874 ECO: Node with name <node name> cannot be found in the netlist.
ID:20875 ECO: Could not find WYSIWYG port <port name> on node <node name>. Use the report_ports command to see the valid ports for this node.
ID:20876 ECO: Output signal with name <oterm> cannot be found in the netlist.
ID:20877 ECO: Unable to modify lutmask on node <node name>
ID:20878 ECO: Failed to process the ECO command at line <script name> of the TCL script <line number>.
ID:20879 ECO: Cannot make connection from <source signal> to <dest node> because they are not in the same partition.
ID:20880 ECO: Cannot remove the connection because the path from <source signal> to <dest signal> does not exist.
ID:20881 ECO: Cannot remove the connection with Hyper-Registers on the path. Use the make_connection command to make connection changes to Hyper-Registers.
ID:20882 ECO: The specified node <node> does not have a LUT mask.
ID:20883 ECO: Cannot make changes to global signal <node>.
ID:20884 ECO: Invalid LUT mask value <lutmask>.
ID:20885 Cannot find a valid Memory Initialization File to process.
ID:20886 Cannot find the Memory Initialization File <name>. Skipped updates for this file.
ID:20887 Processed the following Memory Initialization File(s):
ID:20888 Processed Memory Initialization File <name>
ID:20889 ECO: Cannot make routing changes on dedicated connections from <oterm> to <iterm>.
ID:20890 ECO: Cannot tie the specified input port to <vcc_gnd>.
ID:20891 ECO: Cannot change the <IO_Setting> setting on a node that is not an <direction>.
ID:20892 ECO: The specified Current Strength value is invalid.
ID:20894 Fitter has determined that multiple input signals have been mapped to the same physical port, but not all are sourced by the same output signal.
ID:20895 The current LAB location expects either a register or a LUTRAM node but <atom1> is not of those types.
ID:20896 Node <atom1> is not placed in a LAB location.
ID:20897 Node: <node>, port: <port>
ID:20898 The following problems were detected while converting SDC assignments to a format compatible with an external tool:
ID:20899 Collection <Collection string> is not compatible with the external tool.
ID:20900 Collection <Collection string> contains a TCL command instead of a wildcard specification and so it cannot be exported to an external tool.
ID:20901 Original collection <Collection string> contains node <Node name> which doesn't exist in the exported collection.
ID:20902 Exported collection <Collection string> contains node <Node name> which doesn't exist in the original collection.
ID:20903 Skipping the <Command name> constraint in the report because the SDC conversion failed. See warnings above.
ID:20904 The design has <actual> Partial Reconfiguration partitions. The maximum number of Partial Reconfiguration regions supported for PR authentication is <maximum>.
ID:20905 Secondary top-level design entity "<name>" is undefined.
ID:20910 The host CPU is not supported in this version of the Intel Quartus Prime software. Intel requires that you upgrade to a more recent processor that supports SSE 4.2 and the POPCNT instruction.
ID:20916 Cross-module reference between partition "<name>" and its parent "<name>" is not allowed. Connect signals using partition boundary signals, or merge the partitions that require shared signals.
ID:20917 The device has changed. Closing the Snapshot Viewer.
ID:20919 You have selected Military grade device. Refer to Intel Arria 10 Military Temperature Range Support Technical Brief for supported features and specification.
ID:20920 User has specified PRESERVE_UNUSED_XCVR_CHANNEL QSF assignment at pins "<text>", but the tile "<text>" is completely empty. You must instantiate one dummy channel in the Tile and connect to a stable reference clock in order to preserve unused transceiver channels. See E-Tile Transceiver PHY User Guide for more information.
ID:20921 User has specified PRESERVE_UNUSED_XCVR_CHANNEL global QSF assignment, but the tile "<text>" is completely empty. You must instantiate one dummy channel in the Tile and connect to a stable reference clock in order to preserve unused transceiver channels. See E-Tile Transceiver PHY User Guide for more information.
ID:20922 An illegal value <number> is specified in the PERMITTED_OWNER_CANCELLATION_ID assignment <name>. A valid ID is an integer between 0 and 31
ID:20925 Port "<name>" is of type <name> but is used as type <name> on instance "<name>"
ID:20926 Skipping DSP inference because "<skip_reason>"
ID:20927 Found <number> multipliers that should either be hardened or marked for logic.
ID:20928 Multiplier <string> with input widths <number> and <number> and output width <number> should be hardened or marked explicitly for logic.
ID:20930 Cannot place one or more nodes assigned to a Logic Array Block (LAB) because: <text>
ID:20931 Cannot place combinational or register nodes in Logic Array Block (LAB): LAB_X<number>_Y<number>
ID:20934 The Calibration IP node (<Calibration IP node>) is not connected to any EMIF interface. Review the top-level design to make sure it is connected to an EMIF interface.
ID:20937 Detected an unexpected number of Calibration IP connected to the EMIF interface containing node (<EMIF Interface node>). Expected one Calibration IP but detected <Number of IOSSM Detected>. Review the top-level design to make sure the EMIF interface connects to exactly one Calibration IP.
ID:20938 Module instance "<Atom>", which is a <Atom Wysiwyg Type> primitive, has an unexpected number of connections on port <Atom Port Name>. Expected <Expected number of connection> but detected <Detected number of connection>.
ID:20939 <text>
ID:20941 Correcting WYSIWYG RAM primitive "<name>" <name> parameter value to 1 since using <name> port
ID:20942 Unable to launch the RTL Analyzer without an RTL netlist. Go to Processing > Start > Start Analysis & Elaboration menu to generate the RTL netlist.
ID:20943 - <Operation condition name>
ID:20944 - <Clock name>
ID:20945 Optimal time borrowing values have not been computed for the clock(s) listed below. Timing results may be suboptimal (pessimistic). You can run 'update_timing_netlist -recompute_borrow' to compute optimal time borrowing values or 'update_timing_netlist -dynamic_borrow' to use time borrowing values correct for your current clock frequencies.
ID:20946 Optimal time borrowing values have not been computed for the operating condition(s) listed below. Timing results may be suboptimal (pessimistic). You can run 'update_timing_netlist -recompute_borrow' to compute optimal time borrowing values or 'update_timing_netlist -dynamic_borrow' to use time borrowing values correct for your current clock frequencies.
ID:20947 Optimal time borrowing values have not been computed for this design. Timing results may be suboptimal (pessimistic). You can run 'update_timing_netlist -recompute_borrow' to compute optimal time borrowing values or 'update_timing_netlist -dynamic_borrow' to use time borrowing values correct for your current clock frequencies.
ID:20948 Illegal programming mode specified for Black Key Provision feature. Specify JTAG mode for Black Key Provision feature.
ID:20949 All the logic in partial reconfiguration regions was already compiled into the SOF "<name>" by the base project revision.
ID:20952 Secondary top-level entity '<text>' is also instantiated in another entity '<text>'. This is not allowed.
ID:20953 Secondary top-level entity '<text>' has ports. This is not allowed.
ID:20954 The "<export_snapshot>" snapshot for partition "<partition>" cannot be exported because it is loaded at the "<partition_snapshot>" snapshot.
ID:20955 Secondary top-level entity '<text>' uses instance name '<text>'.
ID:20958 WYSIWYG IO_PAD primitive "<name>" must feed an IO_IBUF WYSIWYG or be fed by an IO_OBUF WYSIWYG
ID:20959 Module instance "<Atom>", which is a <Atom Wysiwyg Type> primitive, has unexpected connections on port <Atom Port Name>.
ID:20960 Module: <Atom name> Port: <Port name>
ID:20961 The value <number> specified in the PWRMGT_ADV_VOUT_READING_ERR_MARGIN assignment. The recommended value range is between 0 and 8
ID:20962 The device family has changed. Do you want to remove family-specific assignments, I/O standard assignments, location assignments, and region assignments that are no longer valid?
ID:20964 The EDA Netlist Writer Resynthesis tool only supports use of the synthesized snapshot. Output will be produced using the synthesized snapshot.
ID:20966 Outside of constrained clock region for global signal "<name>": <region>
ID:20968 Top-level LVDS SERDES IP ports have been left disconnected. Connect the top-level IP ports either to pins or to other components in order to ensure correct placement of the LVDS SERDES IP.
ID:20969 Wharf Rock TILE reset pin < <text> > cannot has fanout to PLD.
ID:20971 Option --<name> is no longer supported by the Intel Quartus Prime software. Run the --place option instead.
ID:20975 When you disable PUF wrapped encryption key, you must specify the Battery Backup RAM or eFuses option for the Encryption Key Select.
ID:20976 When you disable PUF wrapped encryption key, you must specify the Battery Backup RAM or eFuses option for the Encryption Key Storage Select parameter on the Security menu.
ID:20978 Do you want to save your changes?
ID:20980 Partition "<partition>" is exported.
ID:20984 Missing data file argument in the bRAM option <option>.
ID:20986 Incorrect number of arguments in the bRAM option <option>.
ID:20987 Missing options file argument.
ID:20988 Missing input file setting.
ID:20989 Missing output file setting.
ID:20990 Netlist error at <location>: found an unknown netlist type during database binary restore
ID:20991 Netlist error at <location>: failed to restore <string> during database binary restore
ID:20993 Netlist warning at <location>: partial non-constant address in write-port is not yet supported for blasting
ID:20994 Netlist warning at <location>: input port '<string>' remains unconnected for this instance
ID:20995 Verilog HDL warning at <location>: <string> does not expect any parameters
ID:20996 Verilog HDL warning at <location>: too many parameters for <string> instance '<string>'
ID:20997 Verilog HDL warning at <location>: functions cannot contain time-controlled statements
ID:20998 Verilog HDL error at <location>: invalid recursive design instantiation, instance name '<string>'
ID:20999 Verilog HDL warning at <location>: invalid defparam '<string>' in module '<string>'
ID:21000 The phasectrlin[<number>] input of output phase alignment primitive "<name>" must be driven by dqsoutputphasesetting[<number>] output of a DQS configuration primitive when USE_PHASECTRLIN parameter is true and OPERATION_MODE parameter is set to either "rtena" or "extended_rtena"
ID:21001 The enaoutputcycledelay input of output phase alignment primitive "<name>" must be driven by enaoutputcycledelaysetting or enaoctcycledelaysetting output of a DQS configuration primitive when ADD_OUTPUT_CYCLE_DELAY parameter is set to "dynamic" and OPERATION_MODE parameter is set to either "out", "ddio_out", "oe" or "extended_oe"
ID:21002 The enaoutputcycledelay input of output phase alignment primitive "<name>" must be driven by enaoctcycledelaysetting output of a DQS configuration primitive when ADD_OUTPUT_CYCLE_DELAY parameter is set to "dynamic" and OPERATION_MODE parameter is set to either "rtena" or "extended_rtena"
ID:21003 The clk input of output phase alignment primitive "<name>" should not be connected to VCC/GND
ID:21004 The dataout output of output phase alignment primitive "<name>" must drive dynamicterminationcontrol input of an I/O output buffer (directly or indirectly through up to 2 delay chain primitives) when OPERATION_MODE parameter is set to "rtena" or "extended_rtena"
ID:21005 The dataout output of output phase alignment primitive "<name>" must drive oe input of an I/O output buffer (directly or indirectly through up to 2 delay chain primitives) when OPERATION_MODE parameter is set to "oe" or "extended_oe"
ID:21006 The dataout output of output phase alignment primitive "<name>" must drive an output pin (directly or indirectly through up to 2 delay chain primitives) when OPERATION_MODE parameter is set to "out" or "ddio_out"
ID:21007 USE_PRIMARY_CLOCK parameter of output phase alignment primitive "<name>" must be set to "true" when OPERATION_MODE parameter is set to "rtena" or "extended_rtena"
ID:21008 USE_PRIMARY_CLOCK parameter of output phase alignment primitive "<name>" must be set to "true" when USE_PHASECTRL_CLOCK parameters is set to "false"
ID:21009 USE_DELAY_CLOCK parameter of output phase alignment primitive "<name>" must be set to "false" when USE_PRIMARY_CLOCK parameter is set to "false"
ID:21010 PHASE_SETTING parameter of output phase alignment primitive "<name>" must be set to an integer value between 0 and 7 inclusive when USE_PRIMARY_CLOCK and USE_PHASECTRLIN parameters are set to "false"
ID:21011 The enaphasetransferreg input of output phase enable primitive "<name>" can only be driven by either the enaoutputphasetransferreg or the enaoctphasetransferreg output of a DQS configuration primitive
ID:21012 The enaphasetransferreg input of output phase enable primitive "<name>" must be connected when ADD_PHASE_TRANSFER_REG is set to "dynamic"
ID:21013 The phaseinvertctrl input of output phase enable primitive "<name>" can only be driven by either the dqsoutputphaseinvert or the dqoutputphaseinvert output of a DQS configuration primitive
ID:21014 The datain[1] input of output phase alignment primitive "<name>" must be unconnected or connected to GND if the OPERATION_MODE parameter is not set to DDIO_OUT
ID:21015 ADD_PHASE_TRANSFER_REG parameter of OUTPUT_PHASE_ALIGNMENT primitive "<name>" must be set to the opposite setting of INVERT_PHASE parameter
ID:21016 ADD_PHASE_TRANSFER_REG parameter of OUTPUT_PHASE_ALIGNMENT primitive "<name>" must be set to TRUE
ID:21017 ASYNC_MODE parameter of input phase alignment primitive "<name>" must be set to NONE or CLEAR when POWER_UP parameter is set to LOW
ID:21018 ASYNC_MODE parameter of input phase alignment primitive "<name>" must be set to NONE or PRESET when POWER_UP parameter is set to HIGH
ID:21019 The delayctrlin[<number>] input of input phase alignment primitive "<name>" may only be connected to an uninverted delayctrlout[<number>] output of a DLL
ID:21020 The delayctrlin[<number>] input of input phase alignment block "<name>" must be connected when USE_PHASECTRLIN parameter is set to true or PHASE_SETTING parameter is not equal to 0
ID:21021 DELAY_BUFFER_MODE parameter of input phase alignment primitive "<name>" does not match that of DLL "<name>" that is driving the delayctrlin inputs of the input phase alignment primitive
ID:21022 PHASE_SETTING parameter of input phase alignment primitive "<name>" should be less than the value of the DELAY_CHAIN_LENGTH parameter of DLL "<name>" that is driving the delayctrlin inputs of the input phase alignment primitive
ID:21023 The phasectrlin[<number>] input of input phase alignment primitive "<name>" must be driven by resyncinputphasesetting output of a DQS configuration primitive when USE_PHASECTRLIN parameter is set to TRUE.
ID:21024 The enainputcycledelay input of input phase alignment primitive "<name>" must be driven by enainputcycledelaysetting output of a DQS configuration primitive
ID:21025 The clk input of input phase alignment primitive "<name>" should not be connected to VCC/GND
ID:21026 The enaphasetransferreg input of input phase enable primitive "<name>" can only be driven by enaoutputphasetransferreg output of a DQS configuration primitive
ID:21027 The enaphasetransferreg input of input phase enable primitive "<name>" must be connected when ADD_PHASE_TRANSFER_REG is set to "dynamic"
ID:21028 The phaseinvertctrl input of input phase enable primitive "<name>" can only be driven by resyncinputphaseinvert output of a DQS configuration primitive
ID:21029 ADD_PHASE_TRANSFER_REG parameter of INPUT_PHASE_ALIGNMENT primitive "<name>" must be set to the opposite setting of INVERT_PHASE parameter
ID:21030 ASYNC_MODE parameter of half-rate input primitive "<name>" must be set to "none" or "clear" when POWER_UP parameter is set to "low"
ID:21031 ASYNC_MODE parameter of half-rate input primitive "<name>" must be set to "none" or "preset" when POWER_UP parameter is set to "high"
ID:21032 The datain[<number>] input of half-rate input primitive "<name>" cannot be inverted
ID:21033 The datain[<number>] input of half-rate input primitive "<name>" must be driven by a source that only has one fanout
ID:21034 datain[<number>] input of half-rate input primitive "<name>" must be fed by the <name> output port of a DDIO_IN primitive either directly or indirectly via an input phase alignment primitive
ID:21035 One of the non-dataout outputs of the DQS_CONFIG primitive "<name>" must be connected
ID:21036 The enadataoutbypass output of DQS configuration primitive "<name>" may only drive dataoutbypass input of a half-rate input primitive
ID:21037 The enadqsenablephasetransferreg output of DQS configuration primitive "<name>" can only drive enaphasetransferreg input of a DQS enable control primitive.
ID:21038 The enaoctphasetransferreg output of DQS configuration primitive "<name>" can only drive enaphasetransferreg input of a output phase alignment primitive.
ID:21039 The enaoutputphasetransferreg output of DQS configuration primitive "<name>" can only drive enaphasetransferreg input of a output phase alignment primitive
ID:21040 The enainputphasetransferreg output of DQS configuration primitive "<name>" can only drive enaphasetransferreg input of a input phase alignment primitive
ID:21041 The dqsenablectrlphaseinvert output of DQS configuration primitive "<name>" can only drive phaseinvertctrl input of a DQS enable control primitive.
ID:21042 The dqsoutputphaseinvert output of DQS configuration primitive "<name>" can only drive phaseinvertctrl input of an output phase alignment primitive.
ID:21043 The dqoutputphaseinvert output of DQS configuration primitive "<name>" can only drive phaseinvertctrl input of an output phase alignment primitive.
ID:21044 The resyncinputphaseinvert output of DQS configuration primitive "<name>" can only drive phaseinvertctrl input of an input phase alignment primitive or an I/O clock divider primitive.
ID:21045 dataoutbypass input of half-rate input primitive "<name>" must be fed by a DQS configuration enadataoutbypass output
ID:21046 directin input of half-rate input primitive "<name>" must be fed by buffer out output from an I/O input buffer primitive
ID:21047 dataoutbypass input of half-rate input primitive "<name>" must be fed by a DQS configuration enadataoutbypass output or left unconnected
ID:21048 directin input of half-rate input primitive "<name>" must be fed by buffer out output from an I/O input buffer primitive or left unconnected
ID:21049 Port <name> of the atom <name> must be connected to a DQS delay chain atom
ID:21050 Found more than one netlist cell or signal with the name <name> on object <name>
ID:21051 MLAB cell "<name>" has a mixed port read during write setting that is inconsistent with the connectivity on its <name> port
ID:21053 The value set for parameter "<name>" on cell <name> is invalid.
ID:21054 Two or more logical RAMs use the same name
ID:21055 Following RAMs have the same logical RAM name "<name>":
ID:21056 RAM name "<name>"
ID:21057 Implemented <number> device resources after synthesis - the final resource count might be different
ID:21058 Implemented <number> input pins
ID:21059 Implemented <number> output pins
ID:21060 Implemented <number> bidirectional pins
ID:21061 Implemented <number> logic cells
ID:21062 Implemented <number> DSP elements
ID:21063 Implemented <number> macrocells
ID:21064 Implemented <number> RAM segments
ID:21065 Implemented <number> PLLs
ID:21066 Implemented <number> delay-locked loops
ID:21067 Implemented <number> tri-state elements
ID:21068 Verilog HDL error at <location>: non-static generate-for loop. Unroll failed
ID:21069 Verilog HDL error at <location>: invalid duplicate name created during elaboration, multiple declarations created for '<string>'
ID:21070 Implemented <number> User Flash Memory blocks
ID:21071 Implemented <number> partitions
ID:21073 Implemented <number> shareable expanders
ID:21074 Design contains <number> input pin(s) that do not drive logic
ID:21075 The <core supply voltage, junction temperature range> value of '<name>' is illegal for the currently selected part.
ID:21076 <text> operating condition is not set. Assuming a default value of '<name>'.
ID:21077 <Core supply voltage, High junction temperature, Low junction temperature> is <name>
ID:21078 Verilog HDL warning at <location>: the actual is invalidly connected to inout/output port of <string> '<string>', instance '<string>'
ID:21081 Military temperature grade has been selected. Intel recommends that careful thermal analysis and power management be required for device military temperature operation. System testing should be performed at extreme operating temperature points (low and high). Please refer to the following link for more information: http://www.altera.com/products/devices/military/mil-temp.html
ID:21082 An invalid adaptive equalization mode has been selected for receiver <name>
ID:21083 Ignored virtual pin assignment on DLL pin "<name>"
ID:21084 Parameter "<name>" must have the same value
ID:21085 Assignment "<name>" must have the same value
ID:21086 Atom "<name>" has a value of "<name>"
ID:21087 Input port "<name>" must be driven by the same source
ID:21088 Input port "<name>" must be driven by a consistent source
ID:21089 "<name>" must be driven by the same source. Connections across partition boundaries need to be sourced by the same port to guarantee that the source remains the same over subsequent incremental compilations.
ID:21090 Atom "<name>" is driven by source "<name>"
ID:21091 Atom "<name>" is driven by source "<name>" in partition "<name>"
ID:21092 Instantiation blocks of the following are not equivalent due to inconsistent partition assignments
ID:21093 "<name>" in partition "<name>"
ID:21094 Illegal ERROR_CHECK_FREQUENCY_DIVISOR value (<number>) detected in Quartus Prime Settings File. The valid setting for the current device is a power of two in the range of <number> to 256.
ID:21095 TX channels using the "<name>" protocol cannot be placed in the same quad with TX channels that use different protocols
ID:21096 TX channel "<name>" using the "<name>" protocol cannot be placed in the same quad with TX channels that use different protocols
ID:21097 GXB using the "<name> <name>" protocol cannot be placed in the same quad with other GXBs
ID:21098 GXB "<name>" using the "<name>" channel bonding cannot be placed in the same quad with other GXBs
ID:21099 Transmitter PMAs using High-Speed LC PLLs cannot be placed in the same quad with other transmitter PMAs using other HSSI PLLs
ID:21100 Transmitter PMA node "<name>"
ID:21101 Assignment "<name>" must have an assigned value
ID:21105 Input port <name> of GXB receiver channel atom "<name>" must be connected to output port <name> of a GXB receiver channel atom in channel <number>
ID:21106 Input port <name> of GXB transmitter channel atom "<name>" must be connected to output port <name> of a GXB transmitter channel atom in channel <number>
ID:21107 <name> port <name> of GXB transmitter channel atom "<name>" must be connected to <name> port <name> of a <name> atom
ID:21108 <name> port <name> of GXB transmitter channel atom "<name>" must be connected
ID:21109 PCI Express hard IP block "<name>" is either not connected to, or is connected to an improperly configured GXB block on channel number <number>
ID:21110 PCI Express hard IP block "<name>" is not configured with a valid lane_mask
ID:21111 "pllfixedclk" input to the PCI Express hard IP block "<name>" is not connected correctly
ID:21112 Signal "<name>" feeds the INCLK[<number>] input port of GXB Transceiver PLL "<name>", but this signal can be fed only from an input pin
ID:21113 Signal "<name>" feeds the inclk[<number>] input port of the GXB transceiver PLL "<name>", but the HSSI PLL can have only <number> direct cascade path from GPLL clock
ID:21114 Signal "<name>" feeds the inclk[<number>] input port of the GXB transceiver PLL "<name>", but the HSSI PLL can have only <number> clock signal through clock control
ID:21115 Signal "<name>" feeds the inclk[<number>] input port of the GXB transceiver PLL
ID:21116 PLL Signal "<name>" feeds the inclk[<number>] input port of GXB transceiver PLL "<name>" through a clock control
ID:21117 PLL "<name>" type "<name>" cannot cascade to PLL "<name>" type "<name>"
ID:21118 PLL "<name>" is cascaded, but the bandwidth type is set to "<name>". Intel recommends setting the cascaded PLL bandwidth type to "<name>" to better track the PLL reference clock source.
ID:21119 PLL "<name>" has too many fan-outs to the clock dividers. The PLL can support up to only <number> dividers.
ID:21120 HSSI ATX PLL "<name>" has too many connections from the refclk dividers. The HSSI ATX PLL can support up to <number> refclk dividers only.
ID:21121 Output port <name> and <name> of <name> atom "<name>" cannot be connected at the same time <text>
ID:21122 Output port <name>[<number>] of <name> atom "<name>" has illegal fan-out to input port <name>[<number>] of atom "<name>". The output port can drive only input port <name>[<number>] of atom "<name>".
ID:21123 Input port <name> of <name> atom "<name>" has illegal fan-in from output port <name> of atom "<name>". The input port can be driven only by <text>.
ID:21124 DELAY_CHAIN "<name> " whose datain is fed by a DQS_DELAY_CHAIN must have its delayctrlin input fed by a DQS_CONFIG dqsbusoutdelaysetting output
ID:21125 DELAY_CHAIN "<name> " that feeds the dqsenable input of a DQS_ENABLE atom must have its delayctrlin input fed by a DQS_CONFIG dqsenabledelaysetting output
ID:21126 DELAY_CHAIN "<name> " whose dataout feeds a DELAY_CHAIN datain that feeds a IO_OBUF dynamicterminationcontrol input must have its delayctrlin input fed by a DQS_CONFIG octdelaysetting1 output
ID:21127 DELAY_CHAIN "<name> " whose dataout feeds an IO_OBUF dynamicterminationcontrol input and whose datain is fed by a DELAY_CHAIN must have its delayctrlin input fed by a DQS_CONFIG octdelaysetting2 output
ID:21128 DELAY_CHAIN "<name> " whose dataout feeds a DELAY_CHAIN datain which feeds a IO_OBUF i or oe input must have its delayctrlin input fed by an IO_CONFIG outputdelaysetting1 output
ID:21129 DELAY_CHAIN "<name> " whose dataout feeds an IO_OBUF i or oe input and whose datain is fed by a DELAY_CHAIN must have its delayctrlin input fed by an IO_CONFIG outputdelaysetting2 output
ID:21130 DELAY_CHAIN "<name> " whose datain is fed by a IO_IBUF must have its delayctrlin input fed by the IO_CONFIG padtoinputregisterdelaysetting output
ID:21131 DELAY_CHAIN "<name> " whose dataout feeds an IO_OBUF i or oe input must have its delayctrlin input fed by the IO_CONFIG outputdelaysetting, outputdelaysetting1 or outputdelaysetting2 output
ID:21132 DELAY_CHAIN "<name> " whose dataout feeds an IO_OBUF dynamicterminationcontrol input must have its delayctrlin input fed by the DQS_CONFIG octdelaysetting, octdelaysetting1 or octdelaysetting2 output.
ID:21133 Verilog HDL warning at <location>: the actual is invalidly connected to inout/output port of gate '<string>'
ID:21134 DELAY_CHAIN "<name> " that feeds the datain input of DELAY_CHAIN "<name> " must have the delayctrlin fed by the same DQS_CONFIG atom
ID:21135 DELAY_CHAIN "<name> " that feeds the datain input of DELAY_CHAIN "<name> " must have their delayctrlin fed by the same IO_CONFIG atom
ID:21136 DELAY_CHAIN "<name> " that feeds the i input of IO_OBUF and DELAY_CHAIN primitive "<name> ", which feeds the oe input of IO_OBUF must have their delayctrlin fed by the same IO_CONFIG atom
ID:21137 DELAY_CHAIN "<name> " which feeds the i input of IO_OBUF which feeds IO_PAD , which feeds IO_IBUF , which feeds DELAY_CHAIN primitive "<name> ", must have their delayctrlin fed by the same IO_CONFIG atom
ID:21138 DELAY_CHAIN "<name> " which feeds the oe input of IO_OBUF that feeds IO_PAD, which feeds IO_IBUF, which feeds DELAY_CHAIN primitive "<name> ", must have their delayctrlin fed by the same IO_CONFIG atom
ID:21139 DDIO_OUT half rate input "<name>" mode must be set to TRUE when feeding dynamicterminationcontrol or oe inputs of IO_BUF
ID:21140 DDIO_OUT half-rate input "<name>" mode must be set to TRUE when feeding dynamicterminationcontrol or oe inputs of IO_BUF
ID:21141 "<name>" parameter of <name> atom <name> is set to "<name>", but should be set to only "<name>" when targeting <name> devices
ID:21143 The <name> input of <name> atom "<name>" cannot be inverted when fed by a <name> atom
ID:21144 Verilog HDL warning at <location>: dimension for '<string>' is out of bounds
ID:21145 <name> parameter <name> of <name> has a length of <number>, which does not match its corresponding <name> of <number>
ID:21146 Verilog HDL warning at <location>: <string> is not supported for static elaboration
ID:21147 MLAB RAM blocks such as "<name>" may fail to operate correctly in the chosen ES device with the CRC Error Detection feature enabled
ID:21148 MLAB RAM block "<name>" cannot be used to implement the design
ID:21149 DLLs "<name>" and "<name>" share a common clock source - this is an unsupported netlist configuration
ID:21150 RX or TX or PLL is not connected to CMU <name>
ID:21151 Input port <name>[] of GXB transmitter channel atom "<name>" has a width of <number>, but the width cannot exceed <number>
ID:21152 Unknown OUTPUT_PIN_LOAD section "<name>"
ID:21153 Port <name> of atom <name> is connected, but this connection is not allowed because physical coding sublayer (PCS) no longer supports generic FIFO mode
ID:21154 Port <name> of <name> atom "<name>" cannot be connected because parameter <name> is <name>
ID:21155 Device migration enabled -- compilation may have failed due to additional constraints when migrating
ID:21156 <name> port <name> of the PCI Express hard IP block <name> has a width of <name>, but the correct width should be <name>
ID:21157 Atom <name> has incorrect <name>=<name> and <name>=<name> parameter settings
ID:21158 Port <name> of <name> Atom <name> cannot be connected to <name> Atom <name>
ID:21159 <name> port of Atom <name> and <name> port of Atom <name> must have the same input source
ID:21160 Design node <name> is not supported on the specified device <name>
ID:21161 Compensation clock for PLL atom "<name>" is set to "<name>", but the PLL is not in normal compensation mode.
ID:21162 The compensation clock for PLL atom "<name>" is set to "<name>", which can be used in "<name>" protocol only.
ID:21163 The Spread Spectrum Clocking (SSC) feature is no longer supported in Cyclone IV GX EP4CGX75, EP4CGX50 and EP4CGX30CF23 devices.
ID:21164 The fitter is unable to create the complement pin "<name>" automatically because the same name has been used in some I/O pin user assignment(s)
ID:21165 Pin "<name>" has a pseudo-differential I/O standard, but does not have its complement pin. Because the output enable of the differential buffer is in use, the Fitter will not split the differential buffer to create a negative path without a complement output enable path.
ID:21166 Pins "<name>" and "<name>" have pseudo differential I/O standard, but are fed by a differential buffer. The Fitter automatically splits this differential buffer into a pseudo-differential atom driving 2 single-ended output buffers, which in turn drive the pseudo-differential output pins.
ID:21167 Output enable ports of the bidirectional pins <name> and <name> with pseudo_differential I/O standards do not have the same inversion
ID:21168 Bidirectional pin <name> with a pseudo-differential I/O standard must use the <name> port of the node <name>
ID:21169 Complement pins obtained for the bidirectional differential pin <name> via the input and output paths are different -- the configuration is invalid
ID:21170 True differential output buffer <name> cannot connect to the output port of a pseudo-differential output node
ID:21171 Pins <name> and <name> form a pseudo-differential pair, but they do not have the same pin direction
ID:21172 <name> port of the single-ended output buffer <name> is not connected to the <name> port of the pseudo-differential output node <name>
ID:21173 Pins <name> and <name> have values <number> and <number> respectively for the output enable group assignment. These two pins form a pseudo-differential pair but they belong to a different output enable group
ID:21174 <name> port of the pseudo-differential output node <name> is not connected to a single-ended output buffer
ID:21175 Pins <name> and <name> form a differential pair and use true differential input buffer <name>. However, the pins also have an I/O standard <name> which cannot be supported by a true differential input buffer.
ID:21176 Pins <name> and <name> form a differential pair and use a true differential output buffer <name>. However, these pins also have an I/O standard <name> which cannot be supported by a true differential output buffer.
ID:21177 Pins <name> and <name> form a differential pair. However, <name> has an I/O standard <name> and <name> has an I/O standard <name>.
ID:21178 Pin <name> has a differential I/O standard <name>. However, the complement pin is missing.
ID:21179 Pins <name> and <name> form a differential pair and uses pseudo-differential output node <name>. However, these pins also have an I/O standard <name> that cannot be supported by the pseudo-differential output node.
ID:21180 Can't find the legal settings for PLL node "<name>" with reference clock frequency "<name>" and output clock frequency "<name>"
ID:21181 <name> "<name>" has <name> set to <name>, but it can only be set to <name>
ID:21182 DSP block WYSIWYG primitive "<name>" input port <name> has <index> width, which is larger than specified <index> natural width.
ID:21183 DSP block WYSIWYG primitive "<name>" does not support the chainout feature in the current operation mode.
ID:21184 DSP block WYSIWYG primitive "<name>" clock "<name>" and clock "<name>" should not be used simultaneously
ID:21185 DSP block WYSIWYG primitive "<name>" port "<name>" and port "<name>" register should not be driven by different clock sources
ID:21186 DSP block WYSIWYG primitive "<name>" coefficient select port "<name>" should not be connected when the DSP internal coefficient is not used
ID:21187 DSP block WYSIWYG primitive "<name>" does not have its chainin port "<name>" connected, but the dedicated chainout port is used in this DSP mode
ID:21188 DSP block WYSIWYG primitive "<name>" does not have its chainin port "<name>" connected by the correct chainout port in this DSP mode. Leave the chainin port unconnected if the port is not being used.
ID:21189 Chain in port "<name>" for DSP block WYSIWYG primitive "<name>" is fed by "<name>" which is illegal for this mode
ID:21190 Chain in port "<name>" for DSP block WYSIWYG primitive "<name>" is fed by "<name>" and "<name>" or more atoms
ID:21191 Supply voltage value <value> set to the '<name>' power rail is illegal for the selected device.
ID:21192 The core junction temperature range of [<user_low>C, <user_high>C] is modified from the supported core junction temperature range of [<acceptable_low>C, <acceptable_high>C] for the currently selected part. Intel does not guarantee timing, power, or functionality at this non-standard temperature range. Intel provides this compilation result only as an estimate of design performance.
ID:21193 DSP block WYSIWYG primitive "<name>" clock "<name>" and clock "<name>" must be driven by the same clock source when you are using this preadder feature.
ID:21194 Clock Buffer Block "<name>" with clock_type "Auto" is automatically promoted to "Global Clock" because the ENAOUT port is connected.
ID:21195 ENAOUT port of Clock Buffer Block is not supported for clock_type "<clock type>".
ID:21196 Coreclk source from <name> atom <name> does not have the same 0 ppm source with respect to PCS internal clock because of <text>.
ID:21197 LVDSIN port of LVDS DPA atom "<name>" must be fed by input pin that does not feed any other logic
ID:21198 DDIO_OUT half-rate input "<name>" mode must be set to TRUE when the halfratebypass input port is connected.
ID:21199 LVDSOUT port of LVDS DPA atom "<name>" must be fed by output pin that does not feed any other logic
ID:21200 Bandwidth assignments for LC PLL are ignored in the ES silicon.
ID:21201 Output port <name> of DDIO_OE primitive "<name>" must drive input port <name> of an I/O OBUF primitive, or <name> of a PSEUDO_DIFF_OUT primitive.
ID:21202 Can't find the legal settings for PLL node "<name>" with reference clock frequency "<name>" and output clock frequency "<name>" because ES silicon LC output counter is restricted to a value of 2 (for example, values of 1, 4 and 8 are invalid)
ID:21203 Can't find the legal settings for PLL node "<name>" with reference clock frequency "<name>" and output clock frequency "<name>" because ES silicon LC 14G VCO is not currently supported.
ID:21204 <name> parameter "<name>" is set to an illegal value of "<name>" on atom <name>. In "<name>", use ATX-PLL for data rates more than 11.3 G, which corresponds to PLL output clock frequency of 5650 MHz.
ID:21205 When using "<name>" and ATX-PLL with VCO greater than 11.3 Gbps (5650 MHz), boost the VCCR/VCCT to 1.2 V.
ID:21206 The setting of parameter "<name>" on MLAB <name> is being changed from "<name>" to "<name>". This might change the behavior of the MLAB.
ID:21207 "<name>" port of the single-ended output buffer "<name>" is not connected
ID:21208 Input register clock enable port (ena2) is not supported for MLAB cell "<name>" on the selected device family.
ID:21210 Termination calibration block atom "<name>" has <name> port, which must be connected to a top level input port.
ID:21211 TXLOCALFCLK port of LVDS DPA atom "<name>" must feed WRITECLK port of arriav_ir_fifo_userdes atom.
ID:21212 Arria V DSP block WYSIWYG primitive "<name>" does not support "CLOCK2" in <name> register for ES devices.
ID:21213 RAM Primitive "<name>" cannot use the pipeline registers when output is unregistered.
ID:21214 Placement of some of the LVDS pin or pins related to the instance "<name>" may not comply to the existing ALTLVDS DPA mode (with or without Soft CDR) pin restriction guidelines.
ID:21215 Error resolving parameter "<pname>" value on instance "<aname>": <err>.
ID:21216 Cannot enable error detection cyclic redundancy check without instantiating the ALTERA_CRCERROR_VERIFY megafunction for this device.
ID:21217 ALTERA_CRCERROR_VERIFY megafunction is not instantiated for <pname> primitive instance "<iname>".
ID:21218 Verilog HDL error at <location>: <string> is not supported for static elaboration
ID:21219 Verilog HDL error at <location>: cannot operate on uninitialized genvar
ID:21220 Verilog HDL warning at <location>: formal port '<string>' expects a modport or interface instance actual
ID:21221 Verilog HDL error at <location>: formal port '<string>' cannot connect to a modport or interface instance
ID:21222 Verilog HDL error at <location>: value <arg> is out of range
ID:21223 Verilog HDL warning at <location>: unknown qualifier <string> in `default_discipline <string> ignored
ID:21224 Verilog HDL error at <location>: '<string>' attribute of this nature is already declared
ID:21225 Verilog HDL warning at <location>: invalid context for genvar '<string>'
ID:21226 Verilog HDL error at <location>: incompatible number of unpacked dimensions in instantiation
ID:21227 Verilog HDL warning at <location>: invalid concat label for <string>
ID:21228 Verilog HDL error at <location>: invalid recursive design specified through configuration '<string>'
ID:21229 Verilog HDL warning at <location>: cannot index into unpacked base of '<string>'
ID:21230 Verilog HDL error at <location>: cannot index into unpacked base of '<string>'
ID:21231 Verilog HDL warning at <location>: incorrect number of port association in instantiation of VHDL entity '<string>'
ID:21232 Verilog HDL warning at <location>: binding VHDL entity '<string>' does not have port '<string>'
ID:21233 Verilog HDL warning at <location>: size mismatch in mixed language port association, VHDL port '<string>'
ID:21234 Verilog HDL error at <location>: '<string>' expects at least <number> arguments
ID:21235 Verilog HDL warning at <location>: top-level design unit '<string>' specified more than once, ignoring '<string>' of library '<string>'
ID:21236 Verilog HDL warning at <location>: invalid operand for operator <string>
ID:21237 Verilog HDL error at <location>: element index <number> into '<string>' is out of bounds
ID:21238 Verilog HDL warning at <location>: port '<string>' is not connected to this instance
ID:21239 Verilog HDL error at <location>: same genvar '<string>' cannot control this nested for generate loop
ID:21240 Verilog HDL error at <location>: invalid output port connection to '<string>'
ID:21241 Verilog HDL error at <location>: class '<string>' does not expect any parameter
ID:21242 Verilog HDL error at <location>: too many parameters for class instance
ID:21243 Verilog HDL error at <location>: invalid assignment value for genvar '<string>'
ID:21244 Verilog HDL warning at <location>: enum literal '<string>' width (<number>) must match enum width (<number>)
ID:21245 Verilog HDL error at <location>: enum literal '<string>' width (<number>) must match enum width (<number>)
ID:21246 Verilog HDL error at <location>: recursive analog function call '<string>' is not permitted
ID:21247 Verilog HDL error at <location>: second argument of '<string>' must be either global or instance
ID:21248 Verilog HDL error at <location>: port has different sizes in different instances of this array
ID:21249 Verilog HDL error at <location>: call to access function '<string>' with repeated argument '<string>'
ID:21250 Verilog HDL error at <location>: multiple exports of '<string>'
ID:21251 Verilog HDL error at <location>: only branch/analog net can be assigned in contribution statement
ID:21252 Verilog HDL error at <location>: branch contribution is only allowed in analog domain
ID:21253 Verilog HDL warning at <location>: inconsistent dimension in declaration, allowing under AMS mode
ID:21254 Verilog HDL warning at <location>: instantiation of paramset is not yet supported in elaboration
ID:21255 Verilog HDL error at <location>: '<string>' is not valid in branch terminal
ID:21256 Verilog HDL warning at <location>: invalid access of '<string>' inside class '<string>'
ID:21257 Verilog HDL error at <location>: type comparison cannot be done with non-type expressions
ID:21258 Verilog HDL error at <location>: invalid operator <string> for type operand
ID:21259 Verilog HDL error at <location>: cannot assign to analog net '<string>'
ID:21260 Verilog HDL error at <location>: invalid reference to program variable '<string>' from outside program block
ID:21261 Verilog HDL error at <location>: analog net '<string>' is not valid in an expression
ID:21262 Verilog HDL error at <location>: cannot replace genvar expression like genvar_ref[non_const_index]
ID:21263 Verilog HDL error at <location>: name conflict during elaboration for '<string>'
ID:21264 Verilog HDL error at <location>: first argument of $<string> is invalid, expecting 0, 1 or 2
ID:21265 Verilog HDL error at <location>: '<string>' is not assigned in this analog event control
ID:21266 Verilog HDL warning at <location>: cross language complex defparam, not supported yet
ID:21267 Verilog HDL error at <location>: invalid index value for '<string>'
ID:21268 Verilog HDL error at <location>: ground '<string>' should have continuous discipline
ID:21269 Verilog HDL warning at <location>: width <number> of actual differs from width <number> of formal port '<string>'
ID:21270 Verilog HDL warning at <location>: variable '<string>' is driven by invalid combination of procedural drivers
ID:21271 Verilog HDL warning at <location>: select index <number> into '<string>' is out of bounds
ID:21272 Verilog HDL error at <location>: invalid interface based typedef
ID:21273 Verilog HDL error at <location>: hierarchical name in type reference is not allowed
ID:21274 Verilog HDL warning at <location>: type identifier '<string>' is not visible from <string> '<string>', pretty-printed output will be invalid
ID:21275 Verilog HDL warning at <location>: '<string>' driven by this <string> block should not be driven by any other process
ID:21276 Verilog HDL info at <location>: another <string> driver of '<string>' is from here
ID:21277 Verilog HDL error at <location>: export/import task/function '<string>' is not defined
ID:21278 Verilog HDL error at <location>: module instantiation cannot be converted to interface instantiation
ID:21279 Verilog HDL warning at <location>: value of parameter '<string>' cannot contain a hierarchical identifier
ID:21280 Verilog HDL warning at <location>: <string> does not expect any ports
ID:21281 Verilog HDL error at <location>: multiple dimensions in instance '<string>' is not supported yet
ID:21282 Verilog HDL error at <location>: no name for scope owner: hier tree creation aborted
ID:21283 Verilog HDL warning at <location>: ignoring black box marking in configuration '<string>'
ID:21284 Verilog HDL error at <location>: element of assignment pattern has <number> bits; expected <number>
ID:21285 Verilog HDL warning at <location>: type parameter '<string>' cannot be overridden with a defparam statement
ID:21286 Verilog HDL error at <location>: type reference expression may not have hierarchical references
ID:21287 Verilog HDL warning at <location>: type reference expression may not have references to elements of dynamic objects
ID:21288 Verilog HDL error at <location>: task/function '<string>' is not exported/externed in interface '<string>'
ID:21289 Verilog HDL warning at <location>: connection to port '<string>' has a dimension of width <number>, but instance array dimension is <number>
ID:21290 Verilog HDL error at <location>: array port '<string>' is of size <arg>, must be passed an identical array
ID:21291 Verilog HDL error at <location>: named elements cannot be used in <string> used as left-hand side of assignment-like context
ID:21292 Verilog HDL warning at <location>: Verilog expression cannot be converted to VHDL expression
ID:21293 Verilog HDL warning at <location>: too many ports for <string> instance '<string>'
ID:21294 Verilog HDL error at <location>: binding interface instances inside VHDL entity is not yet supported for RTL synthesis
ID:21295 Verilog HDL error at <location>: unresolved external task/function reference '<string>'
ID:21296 Verilog HDL error at <location>: '<string>' is not an interface
ID:21297 Verilog HDL error at <location>: modport '<string>' is not defined inside interface '<string>'
ID:21298 Verilog HDL error at <location>: interface '<string>' does not expect any parameter
ID:21299 Verilog HDL error at <location>: too many parameters for virtual interface
ID:21300 <name> port on the PLL is not properly connected on instance "<name>". The <name> port on the PLL should be connected when the <name> port is connected. Although it is unnecessary to connect the <name> signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready.
ID:21301 Verilog HDL error at <location>: failed to resolve '<string>' in hierarchical name '<string>'
ID:21302 Verilog HDL warning at <location>: cannot instantiate extern <string> '<string>'
ID:21303 Verilog HDL warning at <location>: target is array instance slice, ignoring bind directive
ID:21304 Verilog HDL error at <location>: target not found, bind not done
ID:21305 Verilog HDL error at <location>: <string> argument of '<string>' should be <string>
ID:21306 Verilog HDL warning at <location>: standard attribute '<string>' must be assigned a string
ID:21307 Verilog HDL warning at <location>: invalid value for attribute '<string>', must be <string>
ID:21308 Verilog HDL error at <location>: invalid value range syntax for parameter '<string>'
ID:21309 Verilog HDL error at <location>: net '<string>' with non-continuous discipline cannot have initial value
ID:21310 Verilog HDL error at <location>: size mismatch in terminals of vector branch
ID:21311 Verilog HDL warning at <location>: branch declaration is not allowed inside generate
ID:21312 Verilog HDL error at <location>: access function can have one hierarchical unnamed branch reference
ID:21313 Verilog HDL error at <location>: disciplines for branch terminals should be compatible
ID:21314 Verilog HDL warning at <location>: non-blocking assignment is not allowed in analog block
ID:21315 Verilog HDL warning at <location>: analog event function 'absdelta' can only be used in initial or always block
ID:21316 Verilog HDL warning at <location>: enable argument of 'absdelta' cannot be analog filter function
ID:21317 Verilog HDL error at <location>: System function '<string>' cannot be used outside <string>
ID:21318 Verilog HDL warning at <location>: unsupported format specifier <string>
ID:21319 Verilog HDL error at <location>: invalid format specifier <character>
ID:21320 Verilog HDL error at <location>: exported task/function '<string>' is not defined in <string> '<string>'
ID:21321 Verilog HDL error at <location>: breaking of non-ansi interface port having part select in port expression is not yet supported
ID:21322 Verilog HDL error at <location>: breaking of interface port having multiple dimensions is not yet supported
ID:21323 Verilog HDL warning at <location>: configuration configuring VHDL design hierarchy is not fully supported, considering only design construct
ID:21324 Verilog HDL error at <location>: nature '<string>' can be derived only from another nature
ID:21325 Verilog HDL error at <location>: '<string>' is not a discipline identifier
ID:21326 Verilog HDL error at <location>: hierarchical identifier specified in use clause cannot include scopes of generate or array of instances
ID:21327 Verilog HDL error at <location>: hierarchical identifier must be the only term in use clause specified parameter assignment
ID:21328 Verilog HDL error at <location>: parameter override in a configuration can only refer to a built-in constant system function
ID:21329 Verilog HDL warning at <location>: configuration '<string>' contains more than one <string> for <string> '<string>'
ID:21330 Verilog HDL warning at <location>: branch declaration with same node as branch terminals
ID:21331 Verilog HDL error at <location>: analog operator <string> cannot be used outside analog block
ID:21332 Verilog HDL error at <location>: analog operators cannot be used in <string>
ID:21333 Verilog HDL error at <location>: <string> cannot be used inside analog block
ID:21334 Verilog HDL error at <location>: contribution statement cannot be used inside an event control block
ID:21335 Verilog HDL error at <location>: <string> cannot be used inside analog function '<string>'
ID:21336 Verilog HDL error at <location>: invalid access function '<string>' for node/branch '<string>'
ID:21337 Verilog HDL error at <location>: multiple declaration of '<string>'
ID:21338 Verilog HDL error at <location>: connect module '<string>' should have two ports
ID:21339 Verilog HDL error at <location>: invalid discipline for the ports in connect module '<string>'
ID:21340 Verilog HDL error at <location>: invalid direction for the ports in connect module '<string>'
ID:21341 Verilog HDL warning at <location>: '<string>' is not a connect module
ID:21342 Verilog HDL error at <location>: <string> nature '<string>' is not defined
ID:21343 Verilog HDL error at <location>: <string> nature is not specified in discipline, attribute '<string>' cannot be overridden
ID:21344 Verilog HDL error at <location>: attribute '<string>' cannot be overridden from discipline '<string>'
ID:21345 Verilog HDL error at <location>: nature '<string>' cannot be specified for both potential and flow in discipline '<string>'
ID:21346 Verilog HDL warning at <location>: size of dynamic array dimension must be a positive number
ID:21347 Verilog HDL error at <location>: discipline '<string>' is not compatible to discipline '<string>' of connect module port '<string>'
ID:21348 Verilog HDL error at <location>: invalid port direction override for connect module '<string>'
ID:21349 Verilog HDL warning at <location>: connect resolution specified discipline '<string>' is not compatible to discipline '<string>'
ID:21350 Verilog HDL error at <location>: analog event <string> is not allowed in digital context
ID:21351 Verilog HDL warning at <location>: invalid use of ground net '<string>'
ID:21352 Verilog HDL error at <location>: analog operator <string> is not allowed on the left hand side of equality operator
ID:21353 Verilog HDL error at <location>: all required attributes (abstol, access and units) are not specified for base nature '<string>'
ID:21354 Verilog HDL error at <location>: derived nature '<string>' cannot define or change attribute units
ID:21355 Verilog HDL error at <location>: derived nature '<string>' cannot change attribute access
ID:21356 Verilog HDL warning at <location>: invalid value for parameter '<string>' - not in permissible range of values
ID:21357 Verilog HDL warning at <location>: valid/invalid values should be provided in value range using assignment pattern for string parameter '<string>'
ID:21358 Verilog HDL error at <location>: '<string>' is not a port
ID:21359 Verilog HDL error at <location>: index value containing x or z is invalid for associative array with wildcard index type
ID:21360 Verilog HDL error at <location>: instance name '<string>' already declared in scope
ID:21361 Verilog HDL error at <location>: program instantiation inside interface '<string>' is not supported for synthesis
ID:21362 Verilog HDL error at <location>: parameters of dynamic types are not supported yet
ID:21363 Verilog HDL warning at <location>: invalid bind instance underneath the scope of another bind instance
ID:21364 Verilog HDL error at <location>: '<string>' is not a valid instance of '<string>' in bind directive
ID:21365 Verilog HDL error at <location>: no valid target '<string>' exist for this bind instance
ID:21366 Verilog HDL warning at <location>: immediate assertion expression evaluates to zero
ID:21367 Verilog HDL warning at <location>: concat or multiconcat actual not allowed for array formal port '<string>'
ID:21368 Verilog HDL warning at <location>: casting modport '<string>' to modport '<string>'
ID:21369 Verilog HDL warning at <location>: type parameter '<string>' cannot be overridden with a command line parameter override
ID:21370 Verilog HDL warning at <location>: invalid command line parameter override '<string>' in design element '<string>'
ID:21371 Verilog HDL error at <location>: checker parameter cannot be overridden using command line override
ID:21372 Verilog HDL warning at <location>: VHDL unit instantiation in Verilog should have an instance name
ID:21373 Verilog HDL warning at <location>: '<string>' is not declared under prefix '<string>', command line parameter override ignored
ID:21374 Verilog HDL error at <location>: incorrect value from command line for parameter '<string>'
ID:21375 Verilog HDL error at <location>: invalid black box instance path '<string>'
ID:21376 Verilog HDL warning at <location>: multiple instances of bind module, will be considered only once
ID:21377 Verilog HDL warning at <location>: invalid argument of type <string> in math function '<string>()', expected <string>
ID:21378 Verilog HDL error at <location>: operator <string> returns a <string>, it cannot be used where <string> is expected
ID:21379 Verilog HDL error at <location>: cannot create object of class process using new(), use process::self()
ID:21380 Verilog HDL error at <location>: invalid extends, class '<string>' cannot extend the built-in process class
ID:21381 Verilog HDL error at <location>: extern <string> '<string>' cannot have .* in its portlist
ID:21382 Verilog HDL warning at <location>: ignoring black box marking in interface '<string>'
ID:21383 Verilog HDL warning at <location>: unrecognized value for pragma '<string>'
ID:21384 Verilog HDL error at <location>: defparam '<string>' not applied
ID:21385 Verilog HDL error at <location>: invalid <string> type for value specification in bins
ID:21386 Verilog HDL warning at <location>: coverpoint expression shall be assignment compatible with the data type
ID:21387 Verilog HDL error at <location>: invalid argument of type <string> in string method <string>(), expected <string>
ID:21388 Verilog HDL error at <location>: covergroup instance variable is required to call non-static method <string>
ID:21389 Verilog HDL error at <location>: default or default sequence bin '<string>' cannot be explicitly ignored
ID:21390 Verilog HDL error at <location>: default sequence specification cannot be used for multiple transition bin '<string>'
ID:21391 Verilog HDL warning at <location>: braces without constraint expression violate IEEE 1800 syntax
ID:21392 Verilog HDL warning at <location>: generate block is allowed only inside loop and conditional generate in SystemVerilog mode
ID:21393 Verilog HDL error at <location>: mixed concurrent and procedural assignment on '<string>'
ID:21394 Verilog HDL error at <location>: '<string>' is not found for implicit <string> port connection
ID:21395 Verilog HDL info at <location>: incremental elaboration: restoring old netlist '<string>'
ID:21396 Verilog HDL error at <location>: declaration without an explicit type name violates IEEE 1800 syntax, assuming 'logic'
ID:21397 Verilog HDL info at <location>: hierarchy under '<string>' is unchanged, not elaborating further
ID:21398 Verilog HDL warning at <location>: delay control is not supported for synthesis
ID:21399 Verilog HDL error at <location>: cannot force RAM for identifier '<string>'
ID:21400 Verilog HDL warning at <location>: lifetime qualification static for interface class violates IEEE 1800 syntax
ID:21401 Verilog HDL warning at <location>: different enum types are used together with <string> operator
ID:21402 Verilog HDL error at <location>: actual <string> definition does not have parameter '<string>'
ID:21403 Verilog HDL warning at <location>: parameter '<string>' should exactly match its corresponding parameter in extern <string> '<string>'
ID:21404 Verilog HDL error at <location>: <string> bound of cycle delay range must be positive
ID:21405 Verilog HDL error at <location>: right bound of cycle delay range must be greater than or equal to the left bound
ID:21406 Verilog HDL error at <location>: cycle delay range must be positive
ID:21407 Verilog HDL error at <location>: <string> bound of range for SVA repetition expression must be positive
ID:21408 Verilog HDL error at <location>: right bound of SVA repetition range must be greater than or equal to the left bound
ID:21409 Verilog HDL error at <location>: SVA repetition expression must be positive
ID:21410 Verilog HDL error at <location>: event control statement inside subprogram is not supported for synthesis
ID:21411 Verilog HDL warning at <location>: use `" to terminate the macro text string, not "
ID:21412 Verilog HDL error at <location>: automatic variable '<string>' is not allowed in non-procedural context
ID:21413 Verilog HDL warning at <location>: cycle delay operator requires a default clocking to be specified
ID:21414 Verilog HDL error at <location>: cycle delay operator requires a default clocking to be specified
ID:21415 Verilog HDL warning at <location>: this design contains a SystemVerilog implicit generate region
ID:21416 Verilog HDL warning at <location>: synthesis of 'real' will round to nearest integer
ID:21417 Verilog HDL error at <location>: call to '<string>' on class object can only be used as task
ID:21418 Verilog HDL error at <location>: invalid expression as initializer for type parameter '<string>'
ID:21419 Verilog HDL warning at <location>: assignment to supply0/supply1 variable '<string>' is ignored
ID:21420 Verilog HDL error at <location>: array locator method '<string>' requires a 'with' clause
ID:21421 Verilog HDL warning at <location>: cannot omit 'with' clause for method '<string>', relational operators are not defined for element type of '<string>'
ID:21422 Verilog HDL error at <location>: <string> is unexpected here, violates IEEE 1800 syntax
ID:21423 Verilog HDL warning at <location>: '<string>' type net '<string>' is connected to 'inout' port; will treat as 'output'
ID:21424 Verilog HDL warning at <location>: self referencing of class '<string>' through '<string>', keeping original reference
ID:21425 Verilog HDL warning at <location>: ignoring <string> of command line macro '<string>'
ID:21426 Verilog HDL warning at <location>: '<string>' might have mixed concurrent and procedural assignment
ID:21427 Verilog HDL error at <location>: '<string>' is not a checker, cannot be instantiated in program '<string>'
ID:21428 Verilog HDL error at <location>: instantiation of checker '<string>' inside VHDL unit is not supported
ID:21429 Verilog HDL error at <location>: hier_tree already exists for <string> '<string>', cannot overwrite
ID:21430 Verilog HDL info at <location>: '<string>' is in instance '<string>' of '<string>'
ID:21431 Verilog HDL warning at <location>: interface cannot be used as top-level design unit, ignoring '<string>' from design statement
ID:21432 Verilog HDL error at <location>: embedded coverage group '<string>' cannot be instantiated outside the new method of encompassing class
ID:21433 Verilog HDL error at <location>: no actual value has been specified for formal argument '<string>' of covergroup '<string>'
ID:21434 Verilog HDL error at <location>: class '<string>' may not extend class '<string>' to avoid recursion
ID:21435 Verilog HDL warning at <location>: variable '<string>' requires <number> bits, truncating it to <number>
ID:21436 Verilog HDL error at <location>: the hierarchical name of the export task/function '<string>' should start with a interface port name
ID:21437 Verilog HDL error at <location>: net is invalidly connected to ref port '<string>' of covergroup
ID:21438 Verilog HDL info at <location>: hier_tree is deleted since parse tree is deleted
ID:21439 Verilog HDL error at <location>: invalid formal sample argument '<string>' in covergroup '<string>', output direction is not allowed
ID:21440 Verilog HDL warning at <location>: coverpoint or variable identifier '<string>' cannot appear more than once in cross coverage
ID:21441 Verilog HDL error at <location>: cross coverage should have at least two coverage points or variables
ID:21442 Verilog HDL warning at <location>: parameter '<string>' declared inside <string> '<string>' shall be treated as localparam
ID:21443 Verilog HDL warning at <location>: parameter declared as class-item becomes localparam in class '<string>'
ID:21444 Verilog HDL warning at <location>: event edge <string> has no meaning when used with a clocking block and will be ignored
ID:21445 Verilog HDL warning at <location>: module '<string>' is instantiated multiple times from VHDL or from both Verilog and VHDL, elaboration result may be incorrect
ID:21446 Verilog HDL info at <location>: set runtime flag 'veri_create_unique_hierarchy_for_module_instantiated_in_VHDL' to support such mixed language design
ID:21447 Verilog HDL error at <location>: <string> value is expected for coverage option '<string>'
ID:21448 Verilog HDL warning at <location>: creating cover cross from other cross '<string>' is not allowed
ID:21449 Verilog HDL error at <location>: invalid cross item, only coverpoint/variable identifier is allowed
ID:21450 Verilog HDL error at <location>: invalid set expression in bin, type of expression should be cross's CrossQueueType
ID:21451 Verilog HDL error at <location>: a fixed-size array transition bin '<string>' is not allowed in covergroup
ID:21452 Verilog HDL error at <location>: invalid set expression in coverpoint bin '<string>', type of expression should be unpacked array
ID:21453 Verilog HDL warning at <location>: expression of type string constant is used in coverpoint
ID:21454 Verilog HDL error at <location>: compilation unit '<string>' conflicts with package '<string>', ignoring <string>
ID:21455 Verilog HDL warning at <location>: <string> compilation unit name '<string>'
ID:21456 Verilog HDL error at <location>: go-to/non-consecutive repetition is not allowed in array transition bin '<string>'
ID:21457 Verilog HDL error at <location>: virtual interfaces are not allowed in unions
ID:21458 Verilog HDL error at <location>: default or default sequence bin '<string>' cannot be qualified with 'wildcard'
ID:21459 Verilog HDL warning at <location>: port '<string>' is not connected on this instance
ID:21460 Verilog HDL error at <location>: rand_mode in function form can only be called on singular type expression
ID:21461 Verilog HDL error at <location>: invalid duplicate member '<string>' appears in implicit structure type 'CrossValType'
ID:21462 Verilog HDL warning at <location>: invalid Verilog package parameter override from command line
ID:21463 Verilog HDL error at <location>: '<string>' is not present in the item list of enclosing cross
ID:21464 Verilog HDL error at <location>: invalid hierarchical name in binsof expression, suffix should be bin identifier
ID:21465 Verilog HDL error at <location>: invalid bin expression in binsof, should be coverage point or coverage point bin
ID:21466 Verilog HDL error at <location>: '<string>.<string>' can only be assigned from inside the covergroup declaration
ID:21467 Verilog HDL error at <location>: cross bin 'with' clauses cannot contain cross identifier '<string>'
ID:21468 Verilog HDL error at <location>: only label of enclosing cross '<string>' can be used as bin value
ID:21469 Verilog HDL error at <location>: '<string>' '<string>' is specified multiple times
ID:21470 Verilog HDL error at <location>: covergroup sample method argument '<string>' can only be used in coverpoint/cross/guard expressions
ID:21471 Verilog HDL error at <location>: transition bin specification of zero-length is not allowed
ID:21472 Verilog HDL error at <location>: function 'new' is allowed only in class context
ID:21473 Verilog HDL error at <location>: covergroup id '<string>' cannot be used as prefix for '<string>'
ID:21474 Verilog HDL error at <location>: hierarchical name cannot be used as type in this context
ID:21475 Verilog HDL error at <location>: invalid aggregate comparison as aggregates to be compared must be type equivalent
ID:21476 Verilog HDL warning at <location>: same compilation unit cannot be shared between AMS and SystemVerilog
ID:21477 Verilog HDL error at <location>: '<string>' was previously created with the run-time flag 'veri_speedup_save_restore' disabled, since currently the run-time flag 'veri_speedup_save_restore' is enabled, there is a high probability that a restore error will occur
ID:21478 Verilog HDL error at <location>: '<string>' was previously created using run-time flag 'veri_speedup_save_restore' , since currently the run-time flag 'veri_speedup_save_restore' is not enabled, there is a high probability that a restore error will occur
ID:21479 Verilog HDL error at <location>: parameter '<string>' cannot be used on the left hand side of assignment
ID:21480 Verilog HDL error at <location>: unexpected assignment pattern, parameter '<string>' does not have data type
ID:21481 Verilog HDL warning at <location>: assignment and/or driver for '<string>' inside static function '<string>' is not preserved
ID:21482 Verilog HDL error at <location>: invalid <string> expression for cross item
ID:21483 Verilog HDL warning at <location>: assignment to foreach-loop index variable '<string>' is not allowed
ID:21484 Verilog HDL error at <location>: methods triggered or matched cannot be applied to the instance of sequence '<string>' having input or inout local var formal '<string>'
ID:21485 Verilog HDL warning at <location>: system function call '<string>' is not IEEE standard
ID:21486 Verilog HDL error at <location>: invalid context for type operator
ID:21487 Verilog HDL warning at <location>: array element widths (<number>, <number>) don't match in assignment context
ID:21488 Verilog HDL error at <location>: non integral argument type is not legal for <string>
ID:21489 Verilog HDL warning at <location>: signed/unsigned conversion for real expression
ID:21490 Verilog HDL error at <location>: invalid aggregate comparison because the aggregates to be compared must be type equivalent
ID:21491 Verilog HDL error at <location>: $fatal : <string>
ID:21492 Verilog HDL warning at <location>: $error : <string>
ID:21493 Verilog HDL warning at <location>: $warning : <string>
ID:21494 Verilog HDL info at <location>: $info : <string>
ID:21495 Verilog HDL error at <location>: invalid inout port connection for '<string>', instance '<string>', requires net-lvalue
ID:21496 Verilog HDL error at <location>: invalid hierarchical name containing type name '<string>'
ID:21497 Verilog HDL error at <location>: 'void' cannot be used as argument of type operator
ID:21498 Verilog HDL warning at <location>: entry size <number> at <string>:<number> does not match memory width <number>
ID:21499 Verilog HDL warning at <location>: system function call '<string>' on interface port or instance is not supported for synthesis
ID:21500 Verilog HDL error at <location>: checker cannot be the target of bind, needs module or interface
ID:21501 Verilog HDL warning at <location>: unexpected parameter values in interface type variable/port declaration
ID:21502 Verilog HDL error at <location>: TBDM: '<string>' has no port connections
ID:21503 Verilog HDL error at <location>: TBDM: '<string>' has no port connect '<string>'
ID:21504 Verilog HDL error at <location>: TBDM: cannot find '<string>' in module '<string>'
ID:21507 Verilog HDL info at <location>: instance path : <string>
ID:21508 Verilog HDL warning at <location>: functions may not enable tasks
ID:21509 Verilog HDL info at <location>: the related preprocessor directive is used here
ID:21510 Verilog HDL error at <location>: type name '<string>' cannot be used as prefix in hierarchical name
ID:21511 Verilog HDL error at <location>: default field is not an assignment like context, cannot contain another assignment pattern
ID:21512 Verilog HDL warning at <location>: invalid leading underscore character in based number '<string>'
ID:21513 Verilog HDL warning at <location>: interface port '<string>' cannot be declared with a direction
ID:21514 Verilog HDL error at <location>: interface port '<string>' cannot be declared with a direction
ID:21515 Verilog HDL error at <location>: <string> '<string>' having uninitialized parameter '<string>' and cannot be elaborated by itself
ID:21516 Verilog HDL warning at <location>: overwriting compilation unit '<string>'
ID:21517 Verilog HDL error at <location>: invalid range [<string>] in array instance '<string>'
ID:21518 Verilog HDL warning at <location>: keyword '<string>' is used as identifier
ID:21519 Verilog HDL error at <location>: let construct '<string>' must be defined before used
ID:21520 Verilog HDL warning at <location>: invalid sequence operand for multiclock sequence
ID:21522 VHDL warning at <location>: expression has <number> elements ; expected <number>
ID:21523 VHDL warning at <location>: index <string> is out of array constraint <string> for target '<string>'
ID:21524 VHDL warning at <location>: index value <string> is out of range <string>
ID:21525 VHDL warning at <location>: index value <string> is always out of array index range <string>
ID:21526 VHDL warning at <location>: left bound of slice is outside its index type range
ID:21527 VHDL warning at <location>: right bound of slice is outside its index type range
ID:21528 VHDL warning at <location>: slice direction differs from its index subtype range
ID:21529 VHDL warning at <location>: slice direction differs from its index type range
ID:21530 VHDL warning at <location>: target slice is <number> elements ; value is <number> elements
ID:21531 VHDL warning at <location>: value <string> is out of target constraint range <string>
ID:21532 VHDL warning at <location>: non-static loop limit of <number> exceeded
ID:21533 VHDL error at <location>: partial association of component port '<string>' with formal '<string>' is not supported in static elaboration
ID:21534 VHDL error at <location>: design unit '<string>' contains unconstrained port(s)
ID:21535 VHDL warning at <location>: expression has incompatible type
ID:21536 VHDL error at <location>: direction/bounds for signal formal '<string>' must match with that of actual type for subprogram '<string>'
ID:21537 VHDL warning at <location>: no index value can belong to null index range
ID:21538 VHDL warning at <location>: expression has <number> elements ; formal '<string>' expects <number>
ID:21539 VHDL warning at <location>: top level unit is instantiated, use VHDL_COPY_TOP_BEFORE_STATIC_ELAB compile flag
ID:21540 VHDL error at <location>: library name '<string>' of instantiated unit conflicts with visible identifier
ID:21541 VHDL warning at <location>: type mismatch in <string>
ID:21542 VHDL warning at <location>: cannot be considered as top level, ignoring
ID:21543 VHDL warning at <location>: VHDL expression cannot be converted to Verilog expression
ID:21544 VHDL error at <location>: partial association of component generic '<string>' with formal '<string>' is not supported in static elaboration
ID:21545 VHDL error at <location>: external name is not resolved
ID:21546 VHDL error at <location>: unit '<string>' does not have a port named '<string>'
ID:21547 VHDL warning at <location>: no case item match case expression will not be elaborated
ID:21548 VHDL warning at <location>: only elaborated <string> can be referenced in external name
ID:21549 VHDL error at <location>: invalid element <string> in external name
ID:21550 VHDL error at <location>: no feasible entry for subprogram '<string>' found
ID:21551 VHDL info at <location>: incremental elaboration: restoring old netlist '<string>'
ID:21552 VHDL warning at <location>: delay ignored for synthesis
ID:21553 VHDL error at <location>: cannot force RAM for identifier '<string>'
ID:21554 VHDL info at <location>: executing '<string>'
ID:21555 VHDL error at <location>: size of value too large to convert to onehot
ID:21556 VHDL warning at <location>: <string> comparison of non constant with static metalogical value is always evaluated '<string>' ; may cause simulation-synthesis differences
ID:21557 VHDL error at <location>: hier_tree already exists for '<string>', cannot overwrite
ID:21558 VHDL warning at <location>: bind to black box entity '<string>' is ignored
ID:21559 VHDL info at <location>: hier_tree is deleted since parse tree is deleted
ID:21560 VHDL error at <location>: elaboration aborted for variable slice
ID:21561 VHDL error at <location>: '<string>' may be an internal object defined in Verilog module, only port/generic reference is supported
ID:21562 VHDL warning at <location>: design unit '<string>' implicitly depends on itself via '<string>'
ID:21563 VHDL error at <location>: TBDM: cannot insert '<string>', since design unit has an empty port list
ID:21564 VHDL warning at <location>: port '<string>' added as first port of design unit '<string>', existing instances may need to be updated
ID:21565 VHDL error at <location>: TBDM: cannot find '<string>' in architecture '<string>'
ID:21566 VHDL error at <location>: TBDM: '<string>' has no port connections
ID:21567 VHDL error at <location>: TBDM: '<string>' has no port connect '<string>'
ID:21568 VHDL error at <location>: '<string>' is not an instance of '<string>'
ID:21569 VHDL warning at <location>: function '<string>' may not always return a value
ID:21570 VHDL warning at <location>: using initial value for '<string>' since it is never assigned
ID:21571 VHDL warning at <location>: design unit '<string>' contains unconstrained port '<string>'
ID:21572 VHDL error at <location>: port '<string>' cannot be connected, subtype indication may contain generic having no actual
ID:21573 VHDL error at <location>: name of unit '<string>' matches with the entity defined in the global entity list
ID:21574 VHDL info at <location>: VHDL primary unit '<string>' is now considered a black-box
ID:21575 Too many file arguments specified.
ID:21577 The instance "<instance_name>" is periphery logic and cannot be included in a VQM file.
ID:21578 Target device <device> at index <index> does not support <name> Physical Unclonable Function.
ID:21580 Instances of periphery have been detected in the partition exported as a VQM. VQM export does not support periphery.
ID:21581 Missing HPS handoff file setting.
ID:21582 Missing HPS options file setting.
ID:21583 Illegal type specified for Physical Unclonable Function. Refer to --help=puf_type for legal Physical Unclonable Function type value.
ID:21584 Spine <layer>: <reason>
ID:21585 To properly enable the cascade feature, port CASCADE_WEIGHT_OUT for DSP block WYSIWYG primitive "<atom name>" must be connected to the CASCASDE_WEIGHT_IN port of the next DSP block.
ID:21586 To properly enable the cascade feature, port CASCADE_DATA_OUT for DSP block WYSIWYG primitive "<atom name>" must be connected to the CASCASDE_DATA_IN port of the next DSP block.
ID:21587 To properly enable the cascade feature, port CASCADE_WEIGHT_IN for DSP block WYSIWYG primitive "<atom name>" must be connected from the CASCASDE_WEIGHT_OUT port of the previous DSP block.
ID:21588 To properly enable the cascade feature, port CASCADE_DATA_IN for DSP block WYSIWYG primitive "<atom name>" must be connected from the CASCASDE_DATA_OUT port of the previous DSP block.
ID:21589 Cannot retrieve encryption key from <path>. Make sure the encryption key file (*.qek) is valid and you enter the correct passphrase.
ID:21590 Missing initialization vector value or the specified value is illegal.
ID:21591 Missing key storage type or the specified type is illegal.
ID:21592 Missing key wrapping type or the specified type is illegal.
ID:21593 PUF reliability diagnostic score is <number>
ID:21594 When parameter <parameter name> is set to "<value>" the port(s) <port name> for DSP block WYSIWYG primitive "<atom name>" should be connected. Make sure the parameter is set correctly or disconnect the violating port.
ID:21595 Illegal type specified for device status. Refer to --help=status_type for legal device status type value.
ID:21596 Target device at device index <number> does not support <type> status report.
ID:21597 <status>
ID:21599 Invalid compact certificate type \'<value>\'.
ID:21600 Invalid RMA counter value \'<value>\'
ID:21601 File <name> does not exist.
ID:21602 Invalid RMA counter value \'<value>\'
ID:21603 Invalid initialization vector value \'<value>\'.
ID:21604 In WYSIWYG primitive "<name>", parameter <name> can only be set to <name> when parameter <name> is set to <name>
ID:21605 Clock was constrained to route on spine <layer>.
ID:21607 Parallel synthesis process failed due to database issue. Run synthesis again. If the problem persists contact Intel.
ID:21608 This design uses IOs on the 3V I/O bank. Ensure the VCCR_GXB and VCCT_GXB rails on the corresponding tile are powered up to avoid any configuration issues.
ID:21609 Input port <name> on atom <name> is not connected to a valid source. Port <name> can only be driven by <name>.
ID:21610 Output port "<name>" in <name> entity "<name>" does not have a driver. Connecting to the default value "<value>".
ID:21611 Output port "<name>" in <name> entity "<name>" does not have a driver. Connecting to the default value "<value>".
ID:21615 Running Design Assistant Rules for snapshot '<snapshot name>'
ID:21618 Design Assistant Results: <number of violated fatal rules> of <number of total fatal rules> <serverity level> severity rules issued violations in snapshot '<snapshot name>'<additional info if applicable>
ID:21619 Design Assistant Results: <number of violated fatal rules> of <number of total fatal rules> <serverity level> severity rules issued violations in snapshot '<snapshot name>'<additional info if applicable>
ID:21620 Design Assistant Results: <number of violated high rules> of <number of total high rules> <serverity level> severity rules issued violations in snapshot '<snapshot name>'<additional info if applicable>
ID:21621 Design Assistant Results: <number of violated mediuem rules> of <number of total medium rules> <serverity level> severity rules issued violations in snapshot '<snapshot name>'<additional info if applicable>
ID:21622 Design Assistant Results: <number of violated low rules> of <number of total low rules> <serverity level> severity rules issued violations in snapshot '<snapshot name>'<additional info if applicable>
ID:21623 Encountered clock network congestion. Fitter is attempting to adjust clock regions to resolve congestion.
ID:21624 Not running Design Assistant in <stage name> stage because there is no enabled rule to check
ID:21625 When you convert the AES .qek file to .jam or .jbc format, the .jam or .jbc file contains the AES key in plaintext but obfuscated form. Consequently, you must protect the .jam or .jbc file when storing the AES key. You can do this by provisioning the AES key in a secure environment.
ID:21627 The root partition cannot be a Partial Reconfiguration or Reserved Core partition.
ID:21629 The Fitter cannot place module instance "<Node>", which is a <Node Wysiwyg Type> primitive, with requirement <Requirement> of value <Requirement Value>.
ID:21630 Attempted placing at location <Location>
ID:21631 Due to PAD <Pad> being placed or constrained to location <Location>
ID:21633 Module instances with conflicting requirement of <Requirement>:
ID:21634 <Conflicting PAD> of value <Requirement Value> <Has Constraint> <Location>
ID:21635 The SEU FIT report was not generated because it is not currently available for this device.
ID:21636 <text>
ID:21637 The Remote Update application combined bitstream does not support start address. Please remove start_address option from command line.
ID:21638 The following nodes are in a Partial Reconfiguration or Reserved Core partition but have location constraints outside the partition.
ID:21639 <atom>
ID:21640 IP instance <instance_name> uses invalid tile type <tile_type>. If you are using a Production F-tile device, regenerate your IP.
ID:21641 Valid tile type: <tile_type>
ID:21642 The file <file> does not exist.
ID:21645 Fast Preservation was not enabled. Fast preservation can only be enabled in Partial Reconfiguration and Reserved Core flows, and only when the top-level partition is preserved.
ID:21646 Fast Preservation cannot be enabled if all partitions are preserved.
ID:21648 Please refer to Package Outline Drawing (POD) for any mechanical enablement at https://www.intel.com/content/www/us/en/programmable/support/literature/lit-index/lit-pkg.html.
ID:21650 <text>
ID:21651 Imported partition "<parent_partition_name>" on the instance name ("<parent_instance_name>") has child partition with instnace name ("<child_instance_name>") with the same name.
ID:21654 Cannot enable frequency tamper detection if OSC_CLK_1 is used as the configuration CPU clock source.
ID:21655 The analysis type is disabled for current set of operating conditions.
ID:21656 PUF enrollment succeeded at device index <number>. Power-cycle the device for subsequent configuration.
ID:21659 Design Assistant Results: <number of violated fatal rules> of <number of total fatal rules> <serverity level> severity rules issued violations in snapshot '<snapshot name>'<additional info if applicable>
ID:21660 Design Assistant Results: <number of violated fatal rules> of <number of total fatal rules> <serverity level> severity rules issued violations in snapshot '<snapshot name>'<additional info if applicable>
ID:21661 Design Assistant Results: <number of violated high rules> of <number of total high rules> <serverity level> severity rules issued violations in snapshot '<snapshot name>'<additional info if applicable>
ID:21669 Defaulting to skew computation with high-accuracy CCPP as there may be <Number of exclusive clocks> clocks in all sets of exclusive clock groups, which exceeds the internal limit of <Number of exclusive clocks limit>.
ID:21672 Failed to write Early Power Estimation file "<file>"
ID:21673 Can't open file "<file>" for writing
ID:21674 Created Power and Thermal Calculator export file "<file>"
ID:21675 Failed to write Power and Thermal Calculator export file "<file>"
ID:21676 Database file contains invalid signature. Expected: <expected> Actual: <actual>
ID:21677 No power estimate was produced. Power Analyzer has no power model for target device family. Use the Power and Thermal Calcuator instead.
ID:21678 Power Analyzer (quartus_pow) cannot write a Power and Thermal Calculator import file. Target family <name> is not supported.
ID:21679 No signal activity data is required. Signal Activity File and Value Change Dump file settings are ignored.
ID:21680 Power analysis is not supported for the selected device <name> in the Intel Quartus Prime software Power Analyzer.
ID:21681 The selected device has an HPS. HPS power is not modeled in Power Analyzer for the selected device family. Use the Power and Thermal Calculator (PTC) to model HPS power for the selected device family.
ID:21682 Can't generate Power and Thermal Calculator import file. The target device does not support export to the Power and Thermal Calculator.
ID:21691 Verilog HDL error at <location>: '<string>' must have at least <number> arguments
ID:21692 Verilog HDL error at <location>: super class constructor has non-default arguments, super.new should be called
ID:21693 Verilog HDL warning at <location>: illegal reference to '<string>' in path description, expected port
ID:21694 Verilog HDL warning at <location>: target design for this bind instance is not instantiated
ID:21695 Verilog HDL warning at <location>: illegal interface port connection '<string>' through a generate or array instance
ID:21696 Verilog HDL error at <location>: could not find field/method name '<string>' in '<string>'
ID:21697 Verilog HDL error at <location>: parameter expression '<string>' cannnot be resolved, may refer object declared within generate
ID:21698 Verilog HDL warning at <location>: it is illegal to initialize non singular port '<string>'
ID:21699 Verilog HDL warning at <location>: instance '<string>' does not have a parameter named '<string>' to override
ID:21700 Verilog HDL warning at <location>: '<string>' statement ignored for synthesis
ID:21701 Verilog HDL warning at <location>: instance '<string>' of analog module '<string>' is ignored for elaboration
ID:21702 Verilog HDL warning at <location>: '<string>' is ignored for synthesis
ID:21703 Verilog HDL warning at <location>: ams net '<string>' is ignored for synthesis
ID:21704 Verilog HDL error at <location>: the formal '<string>' can only be used as event expression as it has $inferred_clock as default value
ID:21705 Verilog HDL warning at <location>: <string> system task '<string>' ignored for synthesis
ID:21706 Cannot place sector clock gate <name> as it has an unsupported region or location constraint.
ID:21707 Database file contains invalid class signature. Expected: <expected> Actual: <actual>
ID:21709 The top-level entity name "<entity>" does not match the QSF assignment "<assignment>".
ID:21713 Missing instance name argument in the bRAM option <option>.
ID:21715 File "<name>" is not a valid Signal Tap File.
ID:21716 Directory "<name>" does not exist.
ID:21717 Signal Tap File "<name>" is currently opened. Close the file before overwriting.
ID:21718 Entity "<NAME>" instantiates undefined entity "<NAME>". This may cause the generated IP info to be incomplete.
ID:21720 <Message String>
ID:21723 Signal Tap File "<name>" already exists. Do you want to overwrite the existing file?
ID:21724 Failed to read DDR handoff: <reason>.
ID:21725 Module instance "<Atom>", which is a <Atom Wysiwyg Type> primitive, has missing connections on port <Atom Port Name>.
ID:21726 Time Limited Core Name: <text>
ID:21727 This design uses a device that is restricted to a maximum of <maximum_ios> user-IOs. Currently <used_ios> are being used!
ID:21728 Deterministic overuse of <type> resources in region <region>
ID:21729 Interface Planner Plugin initializing. Interface Planner Plugin initializing. Interface Planner Plugin initializing. Interface Planner Plugin initializing. Interface Planner Plugin initializing. Interface Planner Plugin initializing. Interface Planner Plugin initializing.
ID:21736 Location assignment on block <locked_blk> gets applied to block <member_blk>, causing it to violate Logic Lock region constraint <region>.
ID:21737 Temperature upper bound value <upper> must not be lower than lower bound value <lower>.
ID:21739 Size of device data exceeds the memory capacity of <name>, and <name> does not support cascaded device chain.
ID:21740 Do you want to start the process? It will overwrite the results.
ID:21746 No available location can be found for node <node>. Location assignment on this node <locked_location> conflicts with Logic Lock region <region_name> <region_coordinates>.
ID:21747 Region <region_name> is a reserved region. It prevents the Fitter from placing non-member logic inside the region.
ID:21749 No available location can be found for node <node>. This node was locked to <locked_location> by previous compiles, which conflicts with Logic Lock region <region_name> <region_coordinates>.
ID:21750 Region <region_name> is a reserved region. It prevents the Fitter from placing non-member logic inside the region.
ID:21751 VHDL warning at <location>: synthesis directive "<string>" is not supported
ID:21752 Signal <Name of signal> will not be considered for automatic promotion to the global clock network because it is placed at a non-dedicated clock pin location.
ID:21753 Verilog HDL warning at <location>: synthesis directive "<string>" is not supported
ID:21755 Unable to create Logic Lock region. Compile your design and try again.
ID:21756 Illegal argument type for setup guardband or hold guardband. The Fitter is using the default value for setup guardband (<default_setup_guard>) and hold guardband (<default_hold_guard>).
ID:21757 Clock region <region> cannot be applied to <node>.
ID:21758 Device <name> is not supported for engineering certificate generation.
ID:21759 Too many global data input signals for node <string>. Only <number> global data input signals are allowed per LAB.
ID:21760 Node <string> has <number> global input signals.
ID:21761 Input signal <string> is global.
ID:21762 ECO: ECO-modified nodes must be placed before committing the design. See error messages below for a list of unplaced ECO-modified nodes.
ID:21763 Detected unconnected ECO-modified node: <name>.
ID:21765 ECO: Detected unplaced ECO-modified node: <name>.
ID:21766 The design uses <number> block(s) of type <block_type>, but only <number> block(s) exist in tile <tile_name> of type <tile_type>
ID:21767 Verilog HDL error at <location>: illegal reference to dynamic SystemVerilog type <string> '<string>' in sequence/property expression
ID:21768 Verilog HDL error at <location>: illegal multiple default disable iff in same scope
ID:21769 Verilog HDL warning at <location>: TBDM: header parenthesis was not specified for module '<string>', need to be added manually
ID:21770 Verilog HDL warning at <location>: illegal line number <string>; should be a positive integer
ID:21771 Verilog HDL warning at <location>: an integer level should be specified
ID:21772 Verilog HDL warning at <location>: illegal level value <string>; can be 0, 1 or 2
ID:21773 Verilog HDL warning at <location>: illegal character '<character>' after `line compiler directive
ID:21774 Verilog HDL warning at <location>: non-net output port '<string>' cannot be initialized at declaration in SystemVerilog mode
ID:21775 Verilog HDL error at <location>: extra comma in port association list is not allowed
ID:21776 Verilog HDL error at <location>: default value for port '<string>' must be a constant expression
ID:21777 Verilog HDL warning at <location>: illegal target expression
ID:21778 Verilog HDL error at <location>: previous syntax error is within expansion of macro '<string>' defined here
ID:21780 VHDL error at <location>: value of '<string>' depends on itself, value ignored
ID:21781 VHDL warning at <location>: file read / write outside initial region is ignored for synthesis
ID:21782 VHDL error at <location>: multiple 'force' assignment on '<string>'
ID:21783 VHDL error at <location>: use of 'force' in this context is not supported for synthesis
ID:21784 VHDL error at <location>: 'force' without preserving user nets is not supported for synthesis
ID:21785 VHDL error at <location>: elaboration of variable slice is not supported in this scope
ID:21787 FF atom "<name>" has aclr source and bypass flag to true.
ID:21788 This is a test info message
ID:21790 Detected global signal with Clock Region constraints on some but not all destinations: <name>.
ID:21791 Detected multiple overlapping clock regions for the following global signal: <name>.
ID:21792 Device index <value> is invalid. The device index must start with 1.
ID:21793 Quartus Prime <name> was successful. <number> error<name>, <number> warning<name>
ID:21794 Quartus Prime <name> was unsuccessful. <number> error<name>, <number> warning<name>
ID:21795 Smart recompilation skipped module <name> because it is not required
ID:21796 Flow or module <name> does not exist
ID:21797 Current module <name> terminated because of lack of memory. Verify that you have sufficient memory available to compile your design. You can view disk space and physical RAM requirements on the System and Software Requirements page of the Intel FPGA website (https://fpgasoftware.intel.com/requirements/).
ID:21798 Current module <name> terminated with unexpected exit code <exit_code>. This may be because some system resource has been exhausted. You can view system resource requirements on the System and Software Requirements page of the Intel FPGA website (https://fpgasoftware.intel.com/requirements/).
ID:21799 Current module <name> was unexpectedly terminated by signal <signal_number>. This may be because some system resource has been exhausted, or <name> performed an illegal operation. You can view system resource requirements on the System and Software Requirements page of the Intel FPGA website (https://fpgasoftware.intel.com/requirements/).
ID:21800 Post-flow processing script assignment value <name> is illegal
ID:21801 Pre-flow processing script assignment value <name> is illegal
ID:21802 Post-module processing script assignment value <name> is illegal
ID:21803 Error(s) found while running <module>
ID:21804 Skipped module <name> due to the assignment <name>
ID:21805 Current flow <name> ended unexpectedly
ID:21806 Can't perform <name> because you are currently running <name>. To perform <name>, stop the current flow or wait for the current flow to finish.
ID:21807 Some modules have been skipped due to smart recompilation. You can turn off smart recompilation under Compilation Process Settings in the Settings dialog to fully recompile your design
ID:21808 '<name>' is not supported in the Quartus Prime Pro edition software.
ID:21809 '<name>' is not supported in the Quartus Prime Pro edition software.
ID:21810 Quartus Prime <name> was stopped. <number> error<name>, <number> warning<name>
ID:21811 Quartus Prime <name> was stopped. <number> error<name>, <number> warning<name>
ID:21812 Failed to save design database: <exception>
ID:21813 Failed to initialize flow repository
ID:21814 Failed to open design database: <exception>
ID:21815 <Message String>
ID:21816 Part <text> cannot allow design reconfiguration.
ID:21817 Failed to create design database: <exception>
ID:21819 Found outdated setting on the node "<name>". If you are using Partial Reconfiguration, Intel recommends recompiling the static region.
ID:21820 Routing Constraint File is not a supported feature of the target device
ID:21821 The block <instance_name> has a silicon_rev parameter value of <value> which does not match the block <instance_name> silicon_rev parameter value of <value>
ID:21822 GPIO atom <name> has specified bitpos <number>. Legal range is from 0 to <number>.
ID:21824 Some LSM legal locations <text>.
ID:21825 The design uses <number> block(s) of type <block_type>, but only <number> block(s) exist in tile(s) of type <tile_type>
ID:21829 The host CPU is not supported in this version of the Intel Quartus Prime software. Intel requires that you upgrade to a more recent processor that supports SSE 4.2 and the POPCNT instruction.
ID:21831 <output>
ID:21833 < <text> > signal is being used as nPERST pin for PCIE HIP and must not be used as general-purpose I/O (GPIO). The logic in the core must be driven by another signal.
ID:21835 Incorrect "<NAME>" argument applied to the QDB_FILE_PARTITION assignment in "<LINE_IN_FILE>".
ID:21836 PAGE command payload value <number> is out of range 0 - 255.
ID:21837 File <name> is corrupted.
ID:21838 Failed to find a physically unclonable function (PUF) data partition from flash. Ensure the flash device is formatted with a PUF partition.
ID:21839 Failed to initialize flow definition repository
ID:21841 Project "<project path>" is already open. Do you want to close and reopen the project?
ID:21842 Support logic cannot be generated because IP components used in the design have conflicting settings<string>
ID:21843 <string>
ID:21844 Failed to read options: <reason>.
ID:21845 Primitive name "<NAME>" used for Verilog module name.
ID:21846 <Message String>
ID:21850 Specify qky_file and pem_file options to generate a signed certificate.
ID:21851 The selected device does not support retiming.
ID:21852 This command only supports planned, placed, routed, retimed, and final snapshots.
ID:21853 Defaulting to low-accuracy skew computation algorithm for the following assignments because they cover a large number of skew paths:
ID:21854 These max skew assignments cover a large number of exclusive clock groups, which may increase the skew computation runtime.
ID:21855 Waiver file name cannot be empty. Specify a valid waiver file name before saving the waiver.
ID:21856 Waiver file "<filename>" is read-only.
ID:21857 There are "<number of PR partitions>" Partial Reconfiguration partitions in total. Bitstream verification does not support more than "<maximum supported number of PR partitions>" Partial Reconfiguration partitions in a design.
ID:21858 Programming failed on device index <number>. To avoid this failure, you can retry with QSPI fast programming option turned off.
ID:21862 ENABLE_PR_POF_ID is not being turned on.
ID:21863 This is a test info message
ID:21864 SDM_IO <number> has conflicting assignments of <name> and <name>
ID:21865 This design is signed, and the HPS Debug Access Port (DAP) has been enabled. No integrity claim could be made with HPS DAP enabled. After usage, this generated bitstream should be properly disposed and preferably, its signing key should be cancelled to guarantee no open access for the silicon. The options to enable HPS DAP will have different behavior in future releases.
ID:21866 Cannot enable frequency tamper detection if OSC_CLK_1 is used as the configuration CPU clock source.
ID:21867 The specified file "<name>" for programming bitstream authentication cannot be located.
ID:21868 The bitstream encryption is not supported on current device
ID:21869 This design has enabled programming bitstream encryption. You must also enable authentication by specifying a valid QKY file
ID:21870 To force an SDM clock to the Internal Oscillator, you must specify the Internal Oscillator as configuration clock source
ID:21871 To disable HPS debug, you must disable the HPS debug access port (DAP).
ID:21872 When you disable eFuses for encryption storage, you must specify Battery Backup RAM or PUF option for the Encryption Key Select.
ID:21873 When you disable Battery Backup RAM for encryption key storage, you must specify the eFuses or PUF option for the Encryption Key Select.
ID:21874 When you disable PUF wrapped encryption key, you must specify the Battery Backup RAM or eFuses option for the Encryption Key Select.
ID:21875 When you force encryption key update, you must specify the Encryption Update Ratio.
ID:21876 An illegal value <number> is specified for <name> tamper detection.
ID:21877 Temperature upper bound value <upper> must not be lower than lower bound value <lower>.
ID:21878 ECO: Cannot remove node <node> since it is neither a LUT nor LAB FF.
ID:21879 ECO: Cannot remove placed node <node>.
ID:21880 Can't find file "<path_checked>" required by the WYSIWYG "<wysiwyg_instance_name>" with the parameter "<parameter_value>" set to "<parameter_name>".
ID:21881 WYSIWYG "<wysiwyg_instance_name>" parameter "<parameter_name>" is empty, which is invalid.
ID:21882 Verilog HDL error at <location>: access function '<string>' not supported for synthesis
ID:21883 Verilog HDL error at <location>: invalid value range specifier, first expression shall be numerically smaller than the second expression
ID:21884 Verilog HDL error at <location>: value '<string>' for parameter '<string>' is not in permissible range of values
ID:21885 Verilog HDL warning at <location>: closing label :<string> is only allowed in SystemVerilog mode
ID:21886 Verilog HDL error at <location>: class parameter cannot be overridden using defparam
ID:21887 Verilog HDL error at <location>: too deep class instantiation
ID:21888 Verilog HDL error at <location>: non-ansi port expression '<string>' is not valid here
ID:21889 Verilog HDL error at <location>: Registering Dependencies Error: The library '<string>' is not defined
ID:21890 Verilog HDL error at <location>: Registering Dependencies Error: Type of design unit '<string>.<string>' is unknown
ID:21891 Verilog HDL info at <location>: macro '<string>' is defined here
ID:21892 Verilog HDL warning at <location>: instance '<string>' in use-clause target not found
ID:21893 Verilog HDL warning at <location>: cannot find object '<string>' in current package '<string>', assumed forward reference
ID:21894 Verilog HDL warning at <location>: illegal operator '<string>' for real expression
ID:21895 Verilog HDL error at <location>: illegal operator '<string>' for real expression
ID:21896 VHDL warning at <location>: comparison between unequal length arrays always returns <string>, left argument length <number> is different from right argument length <number> for '<string>' array
ID:21897 VHDL info at <location>: comparing arrays of unequal length in operator '<string>', left argument length <number> and right argument length <number>
ID:21898 VHDL error at <location>: cannot index/slice '<string>' in external name, must be referenced as a whole object
ID:21899 Verilog HDL error at <location>: $error : <string>
ID:21900 File "<filename>" is not a valid Design Assistant waiver file (.dawf).
ID:21901 Starting a flow requires closing the Snapshot Viewer. Do you want to close the Snapshot Viewer and proceed?
ID:21902 Rule <name of rule to be deprecated> at stage <stage name> has been marked for deprecation in a future release.
ID:21903 Rule <name of deprecated rule> at stage <stage name> has been deprecated.
ID:21904 Rule <name of rule to be replaced> at stage <stage name> will be re-indexed to <name of new rule>.
ID:21905 Rule <name of replaced rule> at stage <stage name> has been re-indexed to <name of new rule>.
ID:21906 <string> has already run successfully. Do you want to run the task again?
ID:21908 ECO: Node <node> is not placed.
ID:21909 The following LUTRAM and register nodes are locked to the same x,y location. The Intel Quartus Prime software does not support this.
ID:21910 Node "<atom>" at (<x>, <y>)
ID:21911 Fast Preservation will not be enabled while performing a Fast Forward compile.
ID:21912 <Message String>
ID:21913 ECO: Cannot remove node <node> since it is connected to IO.
ID:21914 Target device at device index <number> does not support service root key provisioning.
ID:21915 Writing to files in the entity mode is enabled with qhd_tcl_vfs_enable_transient_files INI. However, the writes are not committed to the internal databases.
ID:21916 Waived violation(s) of <Mandatory rule or FATAL serviery> rule '<rule id>' for stage '<stage name>'
ID:21918 The DA settings file is read-only and will not be updated with any changes made
ID:21920 Generating service root key on device index <number>.
ID:21921 Service root key generation succeeded on device index <number>.
ID:21922 Invalid entropy value \'<value>\'.<reason>
ID:21923 Adjusted regions for <num_clocks> clock<plural> to resolve congestion.
ID:21924 <clk_name> (<fanout> fanout) drives <new_region> instead of <old_region>
ID:21926 PAGE command payload value is out of range 0x00 - 0xFF.
ID:21927 Device <number> contains JTAG Sub ID code 0x<number>
ID:21928 Expected JTAG Sub ID code 0x<number> for device <number>, but found JTAG Sub ID code 0x<number>.
ID:21931 Fitter is having difficulty packing for clock region sector (<number>,<number>) due to high LAB utilization in that region. <number> LABs are required but only <number> LABs are available exclusively for that region.
ID:21932 <number> additional device is needed to ensure all multipliers are hardened.
ID:21933 Current resource multiplier: <number>. DSP converted to soft logic: <number>. DSP available per device: <number>.
ID:21934 ECO: Failed to find a valid location for node <name> <loc_or_reg>.
ID:21935 <percentage>% of the locations failed due to <reason>.
ID:21936 Invalid explicit key cancellation value \'<value>\'. Specify a valid value between 0 and 31.
ID:21937 Invalid fuse counter value \'<value>\'.<text>
ID:21941 Invalid QKY input file \'<name>\'.<reason>
ID:21943 Failed to place node <name> due to <reason>.
ID:21946 The current device <text>'s data-rate cannot exceed 499Gbps. The design's TX data-rate is <number>, and RX data-rate is <number>.
ID:21948 ECO: Unable to disconnect clock port on node <name>. Use make_connection instead to make a new connection to the clock port.
ID:21949 Target device at device index <number> supports programming only a maximum of <number> root key file(s) (.qky)<text>.
ID:21950 Found duplicate root key from <name> and <name>.
ID:21951 Fitter is having difficulty packing from clock region sectors (<number>,<number>) to (<number>,<number>) due to high LAB utilization. <number> LABs are required but only <number> LABs are available exclusively for that region.
ID:21952 The region "<region>" contains more than <num_points> locations. Searching the region may take longer than desired. Either modify the region or append "-patient" to the command to override the region size restriction.
ID:21953 This command only supports routed, retimed, and final snapshots.
ID:21954 Imported or previously compiled 'finalized' database exists but is not the suitable database to load for this operation!
ID:21955 Intel Stratix 10 devices use the OSC_CLK_1 pin to provide the transceiver calibration clock source. You must provide a 25, 100, or 125 MHz free running and stable clock to OSC_CLK_1. The FPGA's Internal Oscillator cannot be used for transceiver calibration.
ID:21956 A '<snapshot>' database is required and it can only be generated by running 'Fitter' again with ENABLE_INTERMEDIATE_SNAPSHOTS QSF assignment enabled.
ID:21957 A '<snapshot>' database is required and it can only be generated by running 'Analysis & Synthesis' again.
ID:21958 Initialized Quartus Message Database
ID:21959 <percentage>% of the clock legality failures are due to <reason>.
ID:21961 Input port <name> of a "<name>" I/O output buffer "<name>" is not supported.
ID:21962 The cumulative data-rate on the current device <text> cannot exceed 499 Gbps. If the use of dynamic reconfiguration exceeds this data-rate, you will see unexpected/incorrect behavior on hardware because timing closure cannot be guaranteed under those circumstances
ID:21963 Rule <name of deprecated rule> at stage <stage name> has been deprecated.
ID:21964 Rule <name of replaced rule> at stage <stage name> has been re-indexed to <name of new rule>.
ID:21965 ECO: Unable to <op> flip-flop <name> without CLK port. Use make_connection to connect to the CLK port and try again.
ID:21966 HSSI refclk pin < <text> > cannot has fanout to PLD.
ID:21968 Failed to create waiver for rule <rule_id> for stage <stage_name>.
ID:21969 All shift registers are inferred to RAM. This can lead to formal verification failure.
ID:21972 ECO: Cannot find WYSIWYG port <port name> on the placed node <node name>. To introduce a new signal to a FF or a LUT, unplace it with unplace_node first, make the connections, then place it with place_node.
ID:21973 This command only supports routed, retimed, and final snapshots.
ID:21974 Missing instance name argument in the XCVR option <option>.
ID:21975 Missing data file argument in the XCVR option <option>.
ID:21976 Incorrect number of arguments in the XCVR option <option>.
ID:21978 The <port> port on clock divide <node> is connected to a constant. It must be driven by a real signal.
ID:21980 Owner field cannot be empty. Specify a valid owner before saving the waiver.
ID:21981 Description field cannot be empty. Specify a valid description before saving the waiver.
ID:21982 Specify at least one violation field value to create a waiver.
ID:21983 OTN channels represented by FPLL < <name> > have been placed in the same Tile along with bonded channel(more than 4 channels) with rate switch represented by < <name> > which will cause high jitter rate. Place these channels in a Tile with no PCIE.
ID:21984 OTN channels represented by FPLL < <name> > have been placed in the same BANK along with bonded channel with rate switch represented by < <name> > which will cause high jitter rate. Place these channels in a Tile with no PCIE.
ID:21985 ENABLE_PR_POF_ID is set to 'OFF'. Bitstream verification will be disabled.
ID:21986 Verilog HDL error at <location>: conflicting FSM state value <number> for '<string>'<string>
ID:21987 Successfully placed node <name> at <loc>
ID:21992 The top-level entity name "<entity>" does not match the QSF assignment "<assignment>".
ID:21993 Constraint on fitter-created node <name> is not supported.
ID:21996 ECO: Command report_connections received redundant arguments.
ID:21997 ECO: Could not find input port <port name> on node <node name>.
ID:21998 ECO: Could not find output port <port name> on node <node name>.
ID:21999 <reason>
ID:22000 Can't find file <name>
ID:22001 The project setting files are read-only and will not be updated with any changes made.
ID:22002 Can't open editor -- can't load library "<name>". <text>
ID:22003 Cannot create window <name>.
ID:22004 A process is currently running and must be stopped before closing the Quartus Prime software.
ID:22005 '<file name>' has been modified. Do you want to save your changes?
ID:22006 Cannot open project because a process is currently running.
ID:22007 Cannot close project because a process is currently running.
ID:22008 Cannot start a process because a process is currently running.
ID:22009 Flow <user flow name> <file name> was <successful, NOT successful, stopped, or canceled due to an error> (<error count> <error/errors string>, <warning count> <warning/warnings string>)
ID:22010 Flow <user flow name> <file name> was <successful, NOT successful, stopped, or canceled due to an error> (<error or warning count> <error/errors or warning/warnings string>)
ID:22011 Flow <user flow name> <file name> was <successful, NOT successful, stopped, or canceled due to an error>
ID:22012 <user flow name> was <successful, NOT successful, stopped, or canceled due to an error>
ID:22013 EDA physical synthesis completed successfully. Compilation results located in directory "<project directory>resynthesis/adt". To view compilation results, close the current project and open the project in directory "<project directory>resynthesis/adt/<project name>"
ID:22014 <user flow name> was <successful, NOT successful, stopped, or canceled due to an error> (<number> <error/errors string>, <number> <warning/warnings string>)
ID:22015 <user flow name> was <successful, NOT successful, stopped, or canceled due to an error> (<number> <error/errors or warning/warnings string>)
ID:22016 Do you want to overwrite the database for revision "<name>" created by <number>?
ID:22017 Can't open project -- you do not have permission to write to all the files or create new files in the project's database directory
ID:22018 Cannot create a database directory for the project in the project directory "<name>"
ID:22019 Cannot remove incompatible database files from project
ID:22020 Access is denied for file "<file name>"
ID:22021 Project "<file name>" is already open in another instance of the Intel Quartus Prime software. Opening more than one instance of a project can cause design conflicts. Do you still want to open the project (in non-monitoring mode)?
ID:22022 Do you want to close current project "<name>"?
ID:22023 Error processing command line Tcl script. Error message was "<Tcl error message>"
ID:22024 File "<name>" already exists. Do you want to overwrite it?
ID:22025 Starting EDA physical synthesis will overwrite the results of the last compilation -- do you want to continue?
ID:22026 Close the Quartus Prime software and open the project in the Design Space Explorer II?
ID:22027 Close Quartus Prime software and open Design Space Explorer?
ID:22028 Can't launch Design Space Explorer
ID:22029 Do you want to stop the current process?
ID:22030 Do you want to create a new project with this file?
ID:22031 Can't locate the destination tool because a process is currently running
ID:22032 Error occurred while updating the companion revision assignments for both the current revision and the current companion revision
ID:22033 Cannot open file "<name>"
ID:22034 Closing the main software window causes all open windows to close. Do you want to exit the software and close all open windows?
ID:22035 <text>
ID:22036 <text>
ID:22037 Can't find file <name>. Run the EDA Netlist Writer.
ID:22038 Rerun the EDA Netlist Writer
ID:22039 Cannot start EDA timing analysis -- no EDA timing analysis tool specified
ID:22040 Can't start external text editor. Do you want to use the Quartus Prime Text Editor?
ID:22041 Can't locate top-level file in hierarchy
ID:22042 Can't view encrypted file "<name>"
ID:22043 Cannot start the VQM Writer because VQM netlist generation is not supported for the specified device family
ID:22044 Cannot find the Nios II Software Build Tools for Eclipse
ID:22045 Cannot launch the <name> software because you did not specify the path to the executables of the <name> software.
ID:22046 You did not specify an EDA simulation tool.
ID:22048 Design contains periphery IP logic at "<bad_hpath>". The resynthesis of this IP logic is not supported.
ID:22050 Operation failed on device <number>. If JTAG secure mode is enabled, retry with JTAG secure mode disabled.
ID:22053 Node "<name>" is at the edge of the route region. Modifying the route region may allow this signal to route.
ID:22054 The <name> file does not exist.
ID:22055 <name> is an incorrect firmware file.
ID:22058 This command can run only after a design is loaded. Load the design with eco_load_design.
ID:22059 Random power-up flipping for partition <name> is run with probability <text> and seed <number>
ID:22060 <text>
ID:22062 Device <name> is not supported for fabric tap enable certificate generation.
ID:22063 ECO: Invalid checkpoint "<cid>".
ID:22065 Can't display node -- node is encrypted. Displaying non-encrypted portions of schematic.
ID:22066 Can't display node -- node cannot be found in schematic.
ID:22069 A cascading IOPLL was placed between IOPLLs of a different cascade pair. It is not possible for cascading IOPLL pairs to be interleaved. Constrain IOPLL locations so that each cascading IOPLL pair does not share I/O banks with other cascading IOPLL pairs.
ID:22073 Multiple .pfg input files are not supported.
ID:22074 Verilog HDL error at <location>: attribute '<string>' is already specified, previous one will be overwritten
ID:22075 Verilog HDL warning at <location>: <string> directive should be specified outside of a design unit
ID:22077 VHDL error at <location>: path token '@' should be specified before logical library name '<string>'
ID:22078 <Message String>
ID:22079 Total numbers of public root key file (.qky) specified exceed the maximum of <max_number> allowed.
ID:22081 CVP is enabled on tile <text> which is placed on a slot not CVP capable.
ID:22083 Skipped partial reconfiguration raw binary file (.rbf) generation due to Quartus key file is specified.
ID:22085 Skipped partial reconfiguration raw binary file (.rbf) generation due to partial reconfiguration bitstream encryption is enabled.
ID:22086 More than one tile is CVP enabled!
ID:22088 The specified block <block_name> cannot be placed at the location <location> as the location does not allow using a MAC.
ID:22089 The current deivce < <text> > is a sata limited deivce. TE_TEST_ATOM can not be used.
ID:22090 Port(s) <port name> for DSP block WYSIWYG primitive "<atom name>" should not be connected to constant value 2'b11 when parameter <parameter name> is set to "<value>". Make sure the parameter is set correctly or disconnect the violating port.
ID:22091 Failed to load the database model due to incompatible version. Database model was compiled in <db_version> and Quartus version is <quartus_version>.
ID:22092 The Early Power Estimation file name is missing.
ID:22093 The Power and Thermal Calculator file name is missing.
ID:22095 Found duplicate <type> file, <name> and <name>.
ID:22096 The specified block <block_name> cannot be placed at the location <location> as the block requires stream <integer> in an Ethernet <integer>g block but the location only supports stream(s) <id_set>.
ID:22097 Please restart the Intel Quartus Prime software for the applied font changes to take effect everywhere.
ID:22098 The bonded Ethernet blocks starting from <block_name> has a total size of <size> that is not in the set <size_set>.
ID:22099 Cannot use the RTL_PARAMETER assignment "<VALUE>" with partition "<NAME>". This assignment can be used only on RTL modules that are instantiated from a precompiled partition. "<LINE_IN_FILE>".
ID:22100 Invalid <type> input file \'<name>\'. <reason>
ID:22101 Ignore FUSE compact certificate file \'<name>\'. A FUSE compact certificate file subtype <subtype> with the same counter value already exists.
ID:22107 The bonded transceiver blocks starting from <block_name> has a total size of <size> that is not in the set <size_set>.
ID:22109 The bonded transceiver block <block_name> has an id of <id> in a group of bonded transceiver blocks but the location <location> only supports id(s) in <channel_set>.
ID:22110 The '<operation>' operation failed. Cannot find the '<property>' property in the '<database>' database.
ID:22111 Cannot place the block <block_name> at location <location> because there is no topology setting for the tile that allows the placement.
ID:22112 The 'set property' operation failed in the '<database>' database. The '<property>' property cannot be set.
ID:22114 The 'add property' operation failed in the '<database>' database. The '<name>' property already exists in the database.
ID:22115 The 'set property' operation failed in the '<database>' database. The existing type of '<name>' property does not match the type of the new value.
ID:22117 Verilog HDL error at <location>: class '<string>'('<string>') extends a non-class type
ID:22118 Verilog HDL warning at <location>: root module name '<string>' already used as a design name
ID:22119 Verilog HDL info at <location>: macro '<string>' was defined here but has either been undefined or the compilation unit has been closed
ID:22120 Verilog HDL warning at <location>: invert of if-condition matches sensitivity list edge, this is unconventional
ID:22121 VHDL info at <location>: identifier '<string>' (<string>) declared here
ID:22122 VHDL error at <location>: subprogram '<string>' is not visible to use as default for interface subprogram '<string>'
ID:22123 Netlist error at <location>: ram '<string>' with size larger than 2**<number> bits is not supported for blasting
ID:22124 CVP must not be enabled on a non CVP supported tile slot.
ID:22125 Failed to read memory override files: <reason>.
ID:22127 RTL_PARAMETER assignment with an invalid argument. "<LINE_IN_FILE>".
ID:22128 <text>
ID:22129 The component '<component_name>' contains invalid characters. '<extra_info>'
ID:22133 The project "<project name>" is already compiling. Opening this project in a mode other than monitoring mode can cause design conflicts. Do you want to open the project in monitoring mode?
ID:22134 Cannot generate a non-JTAG provisioning bitstream. <reason>
ID:22135 The option file specified must be a .qsf file.
ID:22136 Cannot place the block <block_name> at location <location> using streams [<min>, <max>] because it crosses the block <block_name> at location <location> using streams [<min>, <max>].
ID:22137 Partition "<name>" cannot be marked both as Reserved Core and Partial Reconfiguration type.
ID:22138 The component '<component_name>' was not found. '<extra_info>'
ID:22139 The '<database>' database cannot be loaded. The database's internal consistency checks failed.
ID:22140 Invalid CVP Error: <text>
ID:22141 LSM atom <text> has no location assignment. To be placed at correct LSM section you need add location assignment in Quartus Assignment Editor.
ID:22142 The '<database>' database cannot be accessed. The database has not been opened.
ID:22143 The '<database>' database cannot be written to. The database has not been opened for writing.
ID:22144 Cannot place the block <block_name> at location <location> because the connected cell <block_name> can only be placed in location(s) <location>.
ID:22145 VHDL info at <location>: Note: <string>
ID:22146 VHDL warning at <location>: Warning: <string>
ID:22147 VHDL warning at <location>: Error: <string>
ID:22148 VHDL error at <location>: Failure: <string>: <string>
ID:22149 VHDL error at <location>: prefix of attribute '<string>' should be an object of access or file type
ID:22150 VHDL error at <location>: subtype indication of mode view '<string>' shall denote an unresolved record type or subtype
ID:22151 VHDL error at <location>: mode for record element '<string>' of record type '<string>' is not specified in mode view '<string>'
ID:22152 VHDL error at <location>: '<string>' is not a mode view
ID:22153 VHDL error at <location>: mode of an element mode indication cannot be linkage in mode view '<string>'
ID:22154 VHDL error at <location>: type or subtype of record element '<string>' is not compatible with the type or subtype of mode view '<string>'
ID:22155 VHDL error at <location>: array mode view is specified for a non-array record element '<string>'
ID:22156 VHDL error at <location>: element type or subtype of record element '<string>' is not compatible with the type or subtype of mode view '<string>'
ID:22157 VHDL error at <location>: subtype '<string>' is not compatible with the type or subtype of mode view '<string>'
ID:22158 VHDL error at <location>: element type of '<string>' is not compatible with the type or subtype of mode view '<string>'
ID:22159 VHDL error at <location>: mode-view element '<string>' is not an element of record type '<string>'
ID:22160 VHDL error at <location>: prefix of attribute '<string>' should be a mode view
ID:22164 <text>
ID:22165 ECO: Incremental timing updates and timing-driven ECO options are disabled following an I/O parameter change. A full timing update will be performed when ECO changes are committed (during eco_commit_design).
ID:22166 Are you sure you want to delete the waiver?
ID:22170 Cannot connect "<name>" port and "<name>" port at the same time in altera_syncram IP.
ID:22175 file: "<file_name>"
ID:22176 Not in a legalized state
ID:22177 The '<database>' database cannot be accessed.
ID:22178 User specified unused bank voltage <unused_bank_vccio> is not legal. <legal_bank_vccio> are the legal unused bank voltages for the selected device family.
ID:22179 Family <name> is not supported by the compiler.
ID:22180 Programming of a non-JTAG provisioning bitstream file <name> is not allowed.
ID:22181 Cannot add non-JTAG provisioning bitstream file.
ID:22183 Error: Failed to open file <text>
ID:22185 The assignment <text> should not be modified. Remove the assignment from the QSF file.
ID:22187 Synthesis found <number> latches with readback/writeback requests and added <number> capture flipflops.
ID:22189 Unsupported value for <text>.
ID:22191 Fitter requires <number> LABs to implement the design, but the device contains only <number> LABs. Fitting has terminated due to high LAB utilization.
ID:22192 Verilog HDL warning at <location>: direction for signal '<string>' in modport changed to <string> because it was specified as input
ID:22193 Verilog HDL warning at <location>: <string> is deprecated in IEEE Std 1800-2017
ID:22194 VHDL warning at <location>: multiplication operation has overflowed
ID:22195 Failed to add requested writeback functionality to latch "<latch_name>" because "<failure_reason>".
ID:22196 Cannot write to file <name>. Please check whether the file or folder is writtable.
ID:22198 This design contains constraints that reference clocks before they are created. Run the Design Assistant for more details.
ID:22200 The '<database>' database cannot be loaded. The database was not saved properly the last time it was accessed.
ID:22205 ECO: The specified node <node> is not supported for LUT Equation computation. LUT equations aren't supported for arithmetic LUTs, logic modules or LUTs with more than 6 inputs, hence the lutmask will be returned instead.
ID:22207 The configuration pin assignment <name> has invalid value <number>.
ID:22208 The configuration pin assignment <name> has invalid value <number>.
ID:22209 Encryption key storage location is not consistent across all revisions.
ID:22210 A database file, '<filename>', was not found on disk.
ID:22211 The '<database>' database is being accessed by another Intel Quartus Prime component.
ID:22212 The '<database>' database could not be removed.
ID:22213 A database directory, '<dirname>', was not found on disk.
ID:22214 The '<database>' database could not be copied.
ID:22215 <Message String>
ID:22218 The directory contains the files '<filename>'.
ID:22222 The component '<component_name>' was not found.
ID:22223 The component '<component_name>' contains invalid characters.
ID:22224 The '<path description>' database could not be found.
ID:22225 The path to HPS handoff, HPS options and DDR handoff files must be specified altogether.
ID:22227 The '<database>' sandbox path is invalid.
ID:22228 <Message String>
ID:22229 The Intel Quartus Prime reporting database could not be accessed.
ID:22230 No project is currently open.
ID:22232 The top-level entity assignment must be set in the main QSF and not in a sourced file.
ID:22233 Verilog HDL error at <location>: time unit 'step' should appear as '1step'
ID:22234 Verilog HDL warning at <location>: '{}' may only be used with a queue
ID:22235 VHDL error at <location>: illegal subprogram name
ID:22236 Module name "<name>" contains invalid characters.
ID:22241 Cannot place the block <block_name> at location <location> because it uses port <port_name> that is not present at this location.
ID:22243 Cannot place the block <block_name> at location <location> because port <port_name> connects to block <block_name> and port <port_name> but the port at this location cannot connect to such a port.
ID:22244 Verilog HDL error at <location>: non-array or non-structure context is not legal for assignment-pattern
ID:22247 Clock tree synthesis failed.
ID:22249 Tile-specific unused channel preservation has been enabled
ID:22250 All unused channels of empty '<Indicates the Tile-type to be preserved>' indicated by pin location '<Pin name referring to the unused transceiver tile>' will be preserved
ID:22251 Empty '<Indicates the Tile-type to be preserved>' indicated by pin '<Pin name referring to the unused transceiver tile>' has been preserved due to PRESERVE_UNUSED_XCVR_CHANNEL instance assignment
ID:22252 Empty '<Indicates the Tile-type to be preserved>' has been preserved due to PRESERVE_UNUSED_XCVR_CHANNEL global_assignment
ID:22253 Target device <device> at device index <number> does not support device infomation examination.
ID:22255 The design contains route region(s) that split DSP columns. The following route region(s) are in violation:
ID:22256 <msg>
ID:22258 The configuration scheme <text> is not supported for this device <text>.
ID:22259 The boundary port '<boundary_port_name>' located at (<port_x_location>, <port_y_location>) of the parent Partial Reconfiguration (PR) region '<pr_parent_region_name>' is incorrectly placed inside the child Partial Reconfiguration (PR) region '<pr_child_region_name>'.
ID:22260 A new floorplan should be designed in the partial reconfiguration base compile to place the boundary port(s) outside all child partial reconfiguration regions in all implementations.
ID:22261 An LVDS IP reference clock fed by a cascaded PLL. Connect the LVDS IP core reference clock to an input buffer.
ID:22262 Upstream PLL: <PLL name>
ID:22263 Downstream PLL: <PLL name>
ID:22264 Device <name> does not support the selected mode (<mode>).
ID:22266 Core clock network driver <name> is constrained to region (<xmin>, <ymin>) to (<xmax>, <ymax>). This may result in a longer insertion path and increase Fitter runtime.
ID:22268 Configuration via Protocol (CvP) will not be enabled due to incorrect CvP-related QSF settings.
ID:22270 Cannot locate file <filename>.
ID:22286 Unable to create database '<database>' in folder '<folder>'.
ID:22287 Intel Quartus Prime was not able to initialize project databases.
ID:22288 The clock source <text> is not supported for this device <text>.
ID:22289 Invalid bitstream.
ID:22290 Corrupted SOF information.
ID:22291 Cannot use file <name> because it contains an unsupported file extension. The expected file extension is <name>.
ID:22293 Global signals <clock1>, constrained to the region <region1>, and <clock2>, constrained to the region <region2>, do not intersect but they drive the same <num_nodes_and_comment>
ID:22294 <atom_name>
ID:22295 The detected design changes are too large or affect unsupported nodes.
ID:22296 Unsupported change detected: <description>
ID:22297 Only SignalTap pre-allocated post-fit tap target changes are supported.
ID:22299 The power calculated in the constant junction temperature mode is not representative of actual power during use. It is unlikely that all components of the die are at uniform temperature during normal operation. For more representative power, use the other calculation modes that utilize the thermal calculator.
ID:22300 Design uses Placement Effort Multiplier = <multiplier>.
ID:22301 ECO: Unable to remove a connection with an I/O that results in having a disconnected port.
ID:22302 The configuration scheme is not set, it will be set to <text> for this device.
ID:22303 Parameter value is an <name> type but parameter "<name>" from entity "<name>" is not an <name>
ID:22304 SDC_ENTITY_FILE '<SDC File name>' was not applied. No matching entity: '<Entity>' in library: '<Library>'.
ID:22305 The address set for <text> slave device <text> is invalid. The address set should be 00.
ID:22307 Placed <integer> blocks out of <integer> blocks, The placer last tried to place block <block_name>.
ID:22308 Device <name> does not support Reference Integrity Manifest (.rim) file generation.
ID:22309 Partition assignment <partition_name> cannot be applied to a megafunction.
ID:22312 Unable to reroute a connection while fixing a hold violation. Restoring the Retimed snapshot.
ID:22313 Logic module atom "<name>" in position "<number>" of the propagate carry chain has an invalid propagate invert property.
ID:22316 A license for the Intrinsic ID PUF feature was not detected. Support for this feature is not enabled. Contact Intrinsic ID for an appropriate license.
ID:22318 Intrinsic ID PUF support is enabled for Intel FPGA devices.
ID:22319 The width of the port "<name>" in "<name>" does not match the width in parent entity "<name>". The width is <number> in parent entity, but the current width is <number>.
ID:22321 Detected change to SignalTap sample depth - current design has <current depth> bytes, previous compile had <previous depth> bytes
ID:22322 Detected change to SignalTap <type of port> ports - current design has <current number of ports> ports, previous compile had <previous number of ports> ports
ID:22323 Block <block_name> placed at location <location> cannot be paired with block <block_name> because their types are different
ID:22324 Blocks <block_name> and <block_name> are placed at paired locations <location> and <location> but their connected blocks <block_name> and <block_name> are placed at locations <location> and <location> that are not paired
ID:22325 Cannot place block <block_name> with system PLL <block_name> at location <location> because there is already another system PLL <block_name> used by the paired Ethernet/UX RX/TX
ID:22326 Cannot display state or state machine. State or State machine cannot be found in schematic.
ID:22327 The LUT <node_name> is from an encrypted source file. LUT-mask will not be reported.
ID:22328 <Message String>
ID:22329 The following filter matches with Quartus-created nodes that may change during the compilation flow: <SDC Filter>
ID:22330 The following filter at <SDC File Name>(<SDC Line Number>) matches with Quartus-created nodes that may change during the compilation flow: <SDC Filter>
ID:22331 OCT RZQIN cannot be a virtual pin.
ID:22333 IOs from two EMIF/PHYLite systems have been constrained to share a sub-bank in IOBANK_<name>.
ID:22334 The design already exists at '<path>'.
ID:22335 The checkpoint already exists at '<path>'.
ID:22338 A database operation was performed using an invalid database handle.
ID:22339 An attempt was made to convert a '<Database Type>' database handle to a '<Database Type>' database handle, but the databases are not compatible.
ID:22342 Verilog HDL warning at <location>: missing scope operator in command line parameter override using '<string>' for package '<string>'
ID:22343 Verilog HDL error at <location>: branch or node type argument is expected in access function '<string>'
ID:22344 Verilog HDL warning at <location>: type '<string>' is not visible from the scope containing the bind statement
ID:22345 Verilog HDL warning at <location>: user-defined type '<string>' must match the type in the target scope '<string>'
ID:22346 Verilog HDL error at <location>: unpacked array widths (<number> versus <number>) do not match
ID:22347 Verilog HDL error at <location>: operator '<string>' on genvar '<string>' is not allowed in a genvar/constant expression
ID:22348 VHDL error at <location>: illegal value '<string>' for generic '<string>'
ID:22349 VHDL error at <location>: type error near '<string>' ; expected type of VHDL port does not match its Verilog connection
ID:22350 VHDL error at <location>: type error near '<string>' ; expected type of VHDL generic does not match its Verilog connection
ID:22351 Verilog HDL error at <location>: '<string>' expects <number> arguments
ID:22354 Failed to save reporting database '<file_name>'.
ID:22355 Intel Quartus Prime software failed to save name database '<filename>'.
ID:22356 IP instances <instance_name> and <instance_name> must be placed in the same tile, but are placed at tiles <tile_name> and <tile_name>
ID:22358 This command can run only when no design is loaded. Unload the design with eco_unload_design.
ID:22359 '<text>' is an invalid trait name. Define the trait names with the syntax 'category:group:name'. Valid categories are '<text>'.
ID:22360 Design Assistant Results: <number of passed rules> of <number of total enabled rules> enabled rules passed, and <number of disabled rules> rules was disabled, in snapshot '<snapshot name>'<additional info if applicable>
ID:22361 The CVP mode in the Device and Pin Options dialog box was enabled using the INI variable enable_design_cvp.
ID:22363 <Message String>
ID:22367 Cannot place block <block_name> at location <location> in tile <tile_id> as it is disabled (e.g. associated pad may not be bonded)
ID:22368 An attempt was made to get the root database folder's parent folder. The root database folder has no parent.
ID:22369 The CVP mode in Device and Pins Options dialog box was enabled using qsf assignment, but the AVST X8 configuration scheme is unsupported.
ID:22371 The CVP mode in Device and Pins Options dialog box has been enabled using ini variable enable_design_cvp, but the configuration scheme used is unsupported.
ID:22376 Inout port "<name>" of a true differential output buffer "<name>" is not supported.
ID:22378 test message.
ID:22379 Export failed. Can't export PDF file <file_name>: <error_message>. Verify that the file is closed and that you can write to the specified file and location.
ID:22381 Multi authority must not be enabled with Partial Reconfiguration encryption enabled.
ID:22382 Invalid identifier value \'<name>\'.<text>
ID:22383 Unable to unarchive '<Archive Path>'.
ID:22384 Disk operation '<Disk Operation>' failed on '<File Path>'. The following error was reported by the operating system: '<Operating System Error Message>'.
ID:22388 Ignored invalid location <location> to block <block_name>
ID:22390 Part <name> is not supported by synthesis.
ID:22396 Signal Tap Logic Analyzer data acquisition is in progress. Do you want to stop data acquisition, discard changes, and close Signal Tap Logic Analyzer?
ID:22399 The acquisition clock for the current instance has been updated to "<name>". If there are multiple clocks selected, new instances have been created for the clocks.
ID:22400 Cannot perform action -- Signal Tap Logic Analyzer data acquisition is in progress
ID:22401 Intel Quartus Prime software failed to load name database '<filename>'.
ID:22408 Atom '<name>' (atom id: <id>): is part of a carry chain and has an invert on the carry in, this is an invalid connection
ID:22409 User specified invalid assignment <pin_name> in bank <bank_name> with pin index[<invalid_pin_indexes>], which is not allowed for the AVST x16 or the AVST x32 configuration schemes for the Intel Agilex device family.
ID:22411 <not_shown_count> others not shown. Set DRC_DETAIL_MESSAGE_LIMIT to change the number of nodes shown here.
ID:22412 The design requires at least <design_required> elements of type <type> but the device has only <device_available>.
ID:22413 IP <ip_name> requires elements of this type.
ID:22414 Node: <cell_name>.
ID:22415 <cell_type> node(s) not associated with an IP require elements of this type:
ID:22416 Verilog HDL error at <location>: use of automatic variable '<string>' in sampled value function is illegal
ID:22417 Verilog HDL info at <location>: undeclared symbol '<string>', assumed default net type '<string>'
ID:22418 Verilog HDL error at <location>: illegal actual value '<string>' for ref formal '<string>', value must be assignable
ID:22419 VHDL warning at <location>: `warning : <string>
ID:22420 VHDL error at <location>: `error : <string>
ID:22421 VHDL error at <location>: <string> without `if
ID:22422 VHDL error at <location>: unexpected EOF : missing `end
ID:22423 VHDL warning at <location>: use of undefined conditional analysis identifier '<string>'
ID:22424 VHDL info at <location>: the related conditional analysis directive is used here
ID:22425 VHDL warning at <location>: ignoring re-definition of predefined conditional analysis id '<string>'
ID:22426 Only PCIe X16 can be used when CVP is enabled in P-Tile Avalon Streaming Intel FPGA IP for PCI Express.
ID:22427 The active serial clock is not supported in device initialization clock <device clock>.
ID:22428 Check timing found deprecated check: <Deprecated check> that has been replaced by check: <Replacement check>. Performing the replacement check.
ID:22432 Cannot enable anti tamper detection if clock source OSC_CLK_1 is used and run configuration from internal oscillator is not enabled.
ID:22433 To use anti-tamper device self-kill for <Tamper type>, anti-tamper IP must be present in the design.
ID:22434 Cannot enable anti tamper detection if clock source OSC_CLK_1 is used and run configuration from internal oscillator is not enabled.
ID:22435 To use anti-tamper device self-kill for <Tamper type>, anti-tamper IP must be present in the design.
ID:22436 Recompile has detected unsupported changes.
ID:22437 Detected change: <CHANGE_DESCRIPTION>
ID:22438 In WYSIWYG primitive "<atom_name>", when parameter <parameter_name> is set to <value>, port <port_name> must be connected.
ID:22439 In RAM Primitive "<atom_name>", when parameter <parameter_name> is set to <value>, parameter <parameter_name> must be set to <value>.
ID:22441 User specified I/O standard assignment is not legal for the complementary pin '<name>'.
ID:22442 Can't read from an Atom Netlist File <name>
ID:22443 <Message String>
ID:22444 One or more blocks are missing configuration settings and might not function correctly.
ID:22445 Block "<name>"
ID:22446 Invalid value for pr_slot command option. The value must be either 2 or 4.
ID:22447 You must not enable the checkbox for Enable multi-authority and Enable partial reconfiguration bitstream encryption at the same time.
ID:22452 Target device at device index <number> does not support eFuse cache reloading.
ID:22459 Can't display node -- node cannot be found in schematic.
ID:22460 Non-JTAG provisioning does not support encryption key file (.qek) programming. You can use a compact certificate (.ccert) to program the encryption key.
ID:22461 Detected that more than one system PLL output of system clock IP '<SysClkName>' drives IPs with PTP. <Details>
ID:22462 System clock input of IP '<IPName>' is not driven by System Clock IP as required, but rather is driven by <DrvName>.
ID:22463 System clock frequency of IP port '<IPName>' (<IPclkFreq>) does not match the system clock frequency of system clock IP port '<SysClkName>' (<SysClkFreq>).
ID:22464 Reference clock input of IP '<IPName>' is not driven by system clock IP as required, but rather is driven by <DrvName>.
ID:22465 Reference clock frequency of IP port '<IPName>' (<IPclkFreq>) does not match the reference clock frequency of system clock IP port '<RefClkName>' (<RefClkFreq>).
ID:22466 Multiple IPs {<IPNames>} with FEC are using different system clocks {<ClkNames>} and cannot be placed in the same FEC quad '<QuadName>'. Clean up following location constraints directing their placement in same FEC quad:
ID:22467 Multiple IPs with FEC that are driven by different system clock outputs are assigned to the same tile. Do not place in the same FEC quad, IPs listed in different collections below:
ID:22468 Detected <sysClkNum> system clock instances {<ClkInstNames>}. The maximum number of system clock instances for this device is <maxAllowedClks>, because the <devFamily> F-tile architecture supports only one system clock IP instance per tile.
ID:22469 Can't display node -- node is encrypted. Displaying non-encrypted portions of schematic.
ID:22471 Ignored Maximum Fan-Out logic option for node "<name>" because <reason>
ID:22472 The global signal <clock> is constrained to the region <region> due to <preserv_or_clock_region> but the region does not cover the destination(s) below:
ID:22473 Destination node is placed at (<xcoord>, <ycoord>): <atom_name>
ID:22474 The global signal <clock> is constrained to the region <region> due to <preserv_or_clock_region> but the region does not overlap with the Partial Reconfiguration region for the partition(s) below:
ID:22475 <partition_name>
ID:22476 Intel Quartus Prime software failed to create name database.
ID:22478 Expecting atom ports to be connected to a common atom:
ID:22479 <region_type> <region_name>: <region>
ID:22480 The region requires <demand> <resource_type> resources but there are only <supply> <resource_type> resources available
ID:22481 <not_shown_count> instance(s) not shown. Set DRC_DETAIL_MESSAGE_LIMIT to change the number of instances shown here.
ID:22482 BPPS feature (Based on the Fitter license) is not available with your current license, or the license does not exist.
ID:22483 The QSF <QSF option> is not supported and should be removed.
ID:22484 '<text>' option is for internal developer only and developer license is not found.
ID:22487 UNOC_VIRTUAL_CLOCK port of Initiator "<name>" must be disconnected since its uNoC mode is disabled
ID:22488 Failed to reroute node <node_name> port <port_name> with targeted setup slack <setup> ns and hold slack <hold> ns in <attempts> attempts. The closest rerouted result is a setup slack of <best setup> ns and a hold slack of <best hold> ns.
ID:22489 Ignoring line for bad VHDL conditional analysis variable definition (<line>)
ID:22490 Using VHDL conditional analysis variable definitions file: <path>
ID:22491 Failed to open VHDL conditional analysis variable definitions file: <path>
ID:22492 Overwriting VHDL conditional analysis variable definition for <id> (old=<old_value>, new=<new_value>)
ID:22493 Verilog HDL warning at <location>: wildcard in directory name '<string>' is not supported
ID:22494 Verilog HDL warning at <location>: no matching file found for wildcard pattern '<string>'
ID:22495 Verilog HDL warning at <location>: elaboration created identifier '<string>' is used before its declaration; pretty-printed output may be illegal
ID:22496 Verilog HDL warning at <location>: disconnecting input port '<string>' from '<string>'
ID:22497 VHDL error at <location>: character '<character>' in file '<string>' is not in the element return type '<string>' of this 'readline()' call
ID:22498 The '<database>' database could not be renamed to '<new name>'.
ID:22501 The '<database>' database could not be copied to '<new name>.
ID:22502 Invalid <type> input file \'<name>\'. <reason>
ID:22504 Instance name exceeds the maximum length of <max_length>: "<name>".
ID:22505 Cannot place block <block_name> at location <location_name> because it must use system PLL location <location_name>
ID:22506 Cannot import a design compiled with device "<import revision device>". Only Programmer is supported with this device type.
ID:22507 The active serial clock <active serial clock> is not supported in device initialization clock <device clock>.
ID:22508 Blocks <block_name> and <block_name> are placed at paired locations <location> and <location> but do not have matching parameter settings
ID:22509 Anti-tamper response is disabled. QSF settings related to anti-tamper will be disabled in the SOF.
ID:22510 This design has enabled anti-tamper. You must also enable authentication by specifying a valid QKY file.
ID:22511 This design has enabled attestation commands. You must also enable authentication by specifying a valid QKY file.
ID:22513 To use anti-tamper device self-kill for <Self kill type>, <Tamper type> tamper detection must be enabled.
ID:22515 The net <net_name> is assigned to more than one building block location
ID:22516 Block <block_name>
ID:22517 Location <location_name>
ID:22518 IPs targeted for same tile require <uxDemand> FGT channels (>16).
ID:22519 IPs targeted for same tile require <uxDemand> FHT channels (>4).
ID:22520 IPs targeting the same tile use FHT channels and require <uxDemand> FGT channels (>8).
ID:22521 Reference clock input of IP '<IPName>' is not driven by system clock IP as required, but rather is driven by <DrvName>.
ID:22522 Reference clock frequency of IP port '<IPName>' (<IPclkFreq>) does not match the reference clock frequency of system clock IP port '<RefClkName>' (<RefClkFreq>).
ID:22523 System clock frequency of IP port '<IPName>' (<IPclkFreq>) does not match the system clock frequency of system clock IP port '<SysClkName>' (<SysClkFreq>).
ID:22524 System clock input of IP '<IPName>' is not driven by System Clock IP as required, but rather is driven by <DrvName>.
ID:22527 Programming files generation using command <command line> was successful. Check pfg.log for more info.
ID:22528 Programming files generation using command <command line> was unsuccessful. Check pfg.log for more info.
ID:22533 No piping to other process, this line "<line>" will be replaced by "<line to be replaced>" instead.
ID:22534 Make sure to start every command argument line with "-c" or "--convert".
ID:22535 Make sure to have at least two argument tokens in the command argument line for programmer subsystem call for programming files conversion.
ID:22536 The device selected is not checked for configuration setting correctness and might not function correctly.
ID:22537 Current strength assignments are intended for only output or bidirectional nodes
ID:22539 Voltage tamper detection trigger is outside of the required 15% -100% range.
ID:22541 Command argument <command line> must at least contain two argument tokens.
ID:22543 This feature does not support piping to other subprocesses. Only <command line> will be called.
ID:22544 Command argument <command line> does not start with -c or --convert.
ID:22545 Command argument <command line> must at least contain two argument tokens.
ID:22546 This feature does not support piping to other subprocesses. Only <command line> will be called.
ID:22550 RAM packing optimized away register(s) with SDC constraints targeting input data ports.
ID:22551 RAM packing optimized away constrained register: "<hpath>"
ID:22553 Target collection contains only one item: <Single Target>
ID:22554 Found unexpected block connectivity due to possible circular dedicated chain connection.
ID:22555 Block <block_name> is not part of a macro but <connection> using a dedicated chain connection.
ID:22556 Cannot synthesize dual-clock dual-port RAM logic "<name>". This RAM logic configuration is not supported by the selected device family, but you may configure RAM: 2-PORT Intel FPGA IP to emulate TDP dual clock mode through Platform Designer.
ID:22557 Implemented a large decoder <name> with input width <in_width> and output width <out_width> as logic, at least <num_fo_checked> of the outputs have true fanout.
ID:22558 Intel Quartus Prime detected <Detected> I/O banks with DDR4 interfaces clocked at 1333 MHz for package 1760, 2397B and 2912E. This exceeds the maximum number allowed of <Maximum>.
ID:22560 Target pin is not a clock pin: <Pin Found>
ID:22561 "<Skew>" is not a valid skew value.
ID:22562 Verilog HDL warning at <location>: reference of automatic function '<string>' is not allowed in <string>
ID:22563 Verilog HDL info at <location>: loop count exceeds <number>, while no loop limit is set
ID:22564 Verilog HDL error at <location>: non-constant loop count limit <number> exceeded
ID:22565 Verilog HDL warning at <location>: constant '<string>' cannot be initialized more than once in constructor
ID:22566 Verilog HDL warning at <location>: pg pin '<string>' is not connected on this instance
ID:22567 Verilog HDL info at <location>: extracting RAM for identifier '<string>'
ID:22568 Verilog HDL warning at <location>: cannot index into scalar type parameter/localparam '<string>'
ID:22569 Verilog HDL error at <location>: illegal argument in copy constructor for class '<string>'
ID:22570 VHDL warning at <location>: <string> operation has overflowed
ID:22571 Netlist warning at <location>: pg pin '<string>' is not connected on this instance
ID:22572 Netlist info at <location>: register on net '<string>' is optimized away because of <string>
ID:22573 Netlist warning at <location>: port '<string>' is already connected to net '<string>'
ID:22574 Hierarchies were optimized away during sweep. For details, refer to " Hierarchies Optimized Away During Sweep " report.
ID:22575 NoC group "<name>" must contain all required NoC atoms
ID:22577 NoC atom "<name>" must be part of a NoC group
ID:22578 Pin <pin_name> is reserved for the Intel Agilex device family according to the Intel Agilex Configuration User Guide.
ID:22579 Intel Quartus Prime detected <Maximum> I/O banks with DDR4 interfaces clocked at 1333 MHz. This is the maximum allow for package 1760, 2397B and 2912E and remaining I/O banks do not support other EMIF or GPIO usage. However, Intel Quartus Prime detected <gpio_bank> I/O banks with other EMIF or GPIO usage.
ID:22580 Direct format coefficient m must be a non-zero value when voltage output format of PMBUS device is Direct format.
ID:22581 Cannot write to file <name>. Please check whether the file or folder is writtable.
ID:22582 Invalid cable name. The cable name cannot be empty.
ID:22583 Device index <value> is invalid. The device index must start with 1.
ID:22584 Requested operation is not supported for the target device at device index <number>.
ID:22585 Device index <name> must be less than device index of physical JTAG chain. Check board or choose legal device index.
ID:22586 Programming hardware cable not detected
ID:22587 More than one programming cable found in available hardware list but correct programming cable is not specified
ID:22588 Hardware frequency is auto-adjusted to <frequency>
ID:22589 Fail to scan JTAG chain. Error code <name>.
ID:22590 Query denied because the '<text>' object referenced is invalid.
ID:22591 Query denied because the module object referenced is encrypted.
ID:22592 The specified typical device power characteristics are not valid for the given part.
ID:22593 The specified typical device power characteristics are not valid when the thermal solver is enabled.
ID:22594 Writing to file (<name>) failed during restore. Please check the disk usage or failure
ID:22595 Intel Quartus Prime software does not support entity "<NAME>" of type "<NAME>". Convert <NAME> files to Verilog or VHDL for continued support.
ID:22596 The specified typical device power characteristics should not be used for regulator sizing.
ID:22597 Your system uses a regional numeric format that is incompatible with Quartus
ID:22598 DSP packing optimized away register(s) with SDC constraints.
ID:22599 DSP packing optimized away constrained register: "<hpath>"
ID:22600 Cannot save or open file <name>
ID:22605 Device <name> does not support ECC injection.
ID:22606 Invalid ECC type input at device <name>. Retry with 1 = single-bit error and 2 = double-bit error.
ID:22607 The object (<name>) is not found.
ID:22608 <coefficient of vout format> value is out of range. Valid value range should be within <range>.
ID:22609 <coefficient of vout format> value should have nonzero value. Valid value is <range>.
ID:22613 Failed to find the Remote System Update (RSU) sub-partition table (SPT) from flash. Ensure the flash device is formatted with the RSU layout.
ID:22614 Failed to find the Remote System Update (RSU) configuration pointer block (CPB) from flash. Ensure the flash device is formatted with the RSU layout.
ID:22615 DSP block WYSIWYG primitive "<atom_name>" When port <parameter_name> is used, do not use port <parameter_name>.
ID:22616 Verilog HDL warning at <location>: ignoring the contents of protected block
ID:22617 Verilog HDL warning at <location>: module refers to objects outside modport '<string>' via port '<string>'; using full interface
ID:22618 Verilog HDL error at <location>: asynchronous case condition is not supported for synthesis
ID:22619 Verilog HDL warning at <location>: concatenation '<string>' cannot be used within unpacked array concatenation for unpacked type target
ID:22620 Verilog HDL info at <location>: <string> cannot have named port; ignoring port expression
ID:22621 Verilog HDL error at <location>: modport named port '<string>' is to be declared with a direction
ID:22623 Target collection includes register with multiple clock pins: <Multi-clock register>
ID:22626 The design has <number> reconfiguration controllers in the tile <tile_name> when there should be only 1.
ID:22627 Cannot find PTP adapter for the block <block_name>.
ID:22629 The database file "<filename>" cannot be located.
ID:22630 Unable to read the database file "<filename>".
ID:22631 Database file "<filename>" is corrupted on line <line>.
ID:22632 The launch and latch times for the relationship between source clock: <Src Clock Name> and destination clock: <Dst Clock Name> are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
ID:22634 The database file "<filename>" cannot be located.
ID:22635 Unable to read the database file "<filename>".
ID:22636 Database file "<filename>" is corrupted on line <line>.
ID:22637 Cannot add the block/reconfiguration group <name> to reconfiguration group <name> as it is already a part of reconfiguration group <name>
ID:22641 Failed to copy <name> to <name>. Ensure that you have sufficient access to write files in target location
ID:22645 Cannot locate <name> <name>
ID:22646 Value <original default value> for QSF Assignment <assignment name> is not supported. Hence changing the value to <new default value>
ID:22647 Power management voltage output format <vout format> is not supported for the current device family.
ID:22648 SmartVID slave device type had been updated to Other as current selected slave device type is not supported by this device family.
ID:22649 Cannot place block <block_name> using system PLL <block_name> in location <location> because there are already other system PLL(s) in the same FEC quad
ID:22650 File <name> is <reason>. <details>.
ID:22651 Port <ConnectType>: tile IP instance: <IPName>, system clock port: <SysClkName>, is not connected to system clock IP
ID:22652 Multiple drivers: tile IP instance: <IPName>, system clock port: <SysClkName>, is connected to <NumDrivers> driving ports
ID:22653 Port <ConnectType>: tile IP instance: <IPName>, reference clock port: <RefClkName>, is not connected to system clock IP
ID:22654 Multiple-driver: tile IP instance: <IPName>, reference clock port: <RefClkName>, is connected to <NumDrivers> driving ports
ID:22657 Can't generate simulation output files. Update EDA Tool Settings to specify an EDA Simulation tool and output format. Alternatively, specify the settings with command-line options or Tcl script.
ID:22658 Cannot place block <block_name> in location <location> because it makes the block <block_name> unplaceable
ID:22660 The reconfiguration group <name> should only have 1 shared SIP IP instance, but found <number> IP instances.
ID:22661 IP instance <name>
ID:22662 The block <block_name> is part of a shared SIP group and must be assigned to a single location.
ID:22663 Clock source <ClkName> cannot drive the following <IPnum> IPs of mixed FHT and FGT types:
ID:22664 The current OPN does not support Inline Cryptographic Acceleration. Use a different OPN that supports Inline Cryptographic Acceleration. For more information contact Intel Premier Support and quote ID #14014651561.
ID:22666 ECO: <node name> is constrained to an invalid search region <region>.
ID:22667 String cannot be empty.
ID:22668 Character '<text>' in string '<text>' is not lowercase.
ID:22669 System clock ports '<BusName>' of tile IP '<TileName>' are not driven by the same clock:
ID:22670 Reference clock ports '<BusName>' of tile IP '<TileName>' are not driven by the same clock:
ID:22671 The instance assignment target (<assignment target>) uses deprecated "entity:inst" style. Instance paths should be specified using only instance names.
ID:22672 Quit monitoring mode before closing Intel Quartus Prime Software, To quit monitoring mode, select Processing > Quit Monitoring.
ID:22673 pfg_commands.txt is not found under <pfg commands txt filepath>, make sure that this is a valid project path or re-edit commands on "Programming files" under "Settings" dialogue to update the project path.
ID:22674 pfg_commands.txt is not found under <pfg commands txt filepath>, make sure that this is a valid project path or re-edit commands on "Programming files" under "Settings" dialogue to update the project path.
ID:22675 The argument (<constraint argument>) matches hierarchical instance '<constraint target>' which will be lost during flattening. In this release, this constraint target is ignored.
ID:22676 The argument (<constraint argument>) matches bidirectional hierarchical pin '<constraint target>' which will be lost during flattening. In this release, this constraint target is ignored.
ID:22677 The argument (<constraint argument>) matches net '<constraint target>' which will be lost during flattening. In this release, this constraint target is ignored.
ID:22678 An alias for the "<original_sim_tool>" simulation tool has been found. Updating the tool name to "<aliased_sim_tool>".
ID:22679 The SDC compression feature does not guarantee the order of the constraints.
ID:22681 USE CONF_DONE output pin must be assigned for AVST configuration scheme.
ID:22683 Error: Failed to open <text> <text> for <text>. Confirm that you have write permission for this file. Update the file permissions, if needed.
ID:22685 <type> "<hpath>" is connected to a virtual port on "<virtual_hpath>".
ID:22686 Verilog HDL warning at <location>: class '<string>' cannot have both arguments after 'extends' and use 'super.new()' in the constructor
ID:22687 Verilog HDL error at <location>: unexpected assignment pattern; parameter '<string>' does not have a resolve data type '<string>'
ID:22690 Parameter setting <parameter name>=<value> for rule <rule name> in da_drc.ini is not recognized. The parameter setting might be renamed or deprecated. Check the rule parameters and update your old settings from Quartus GUI menu Assignments>Settings>Design Assistant Rule Settings
ID:22691 Port connection by order is not allowed in Intel FPGA IP core instantiations: "<name>".
ID:22694 IP instance <instance_name> needs to be assigned to a tile through IP_TILE_ASSIGNMENT QSF setting or associated with another IP instance through a IP_COLOCATE QSF setting.
ID:22697 Assignment setting for <assignment name> (<assembler setting>) found in assembler does not match the setting found in fitter (<fitter setting>). Rerun fitter stage.
ID:22700 Number of targets in group "<name>" (<num_initiators>) exceeds the maximum capacity on the NoC device (<max_initiators> targets in the <name> largest NoC group.).
ID:22701 Number of initiators in group "<name>" (<num_initiators>) exceeds the maximum capacity on the NoC device (<max_initiators> initiators in the <name> largest NoC group.).
ID:22702 Number of NoC groups (<num_groups>) exceeds the maximum (<max_groups>).
ID:22703 Cannot place block <block_name> at location <location> as the block <block_name> with relative distance <distance> from this cell cannot be placed at location <location>
ID:22704 Cannot place block <block_name> at location <location> as it makes the block <block_name> at relative distance <distance> from this cell unplaceable
ID:22707 Failed to create helper process named <pipe name> with Error Code: <error code>.
ID:22708 Verilog HDL warning at <location>: unrecognized pragma '<string>'
ID:22709 Verilog HDL warning at <location>: incorrect use of pragma '<string>'
ID:22710 Verilog HDL warning at <location>: unrecognized pragma name '<string>' for '<string>'
ID:22711 Verilog HDL warning at <location>: invalid index value for writing operation on queue '<string>'
ID:22712 Verilog HDL error at <location>: library alias name '<string>' already exists as a logical library
ID:22713 VHDL error at <location>: parameter of predefined attribute '<string>' must be an expression
ID:22714 Netlist warning at <location>: RAM '<string>' is driven from mixed clocked regions; not supported for blasting
ID:22716 Failed to enable \'<name>\'.<reason>
ID:22717 Security feature <security feature> is not supported on VID device. Choose a non-VID device that supports the feature or disable it.
ID:22718 CRL distribution point in attestation must contain a valid HTTPS URL.
ID:22720 Parameter "<parameter_name>" has invalid value "<parameter_value>" on netlist "<netlist_name>".
ID:22721 CRL distribution point in attestation must contain a valid HTTPS URL.
ID:22724 QUICK_ELAB_TILE_IP_PROPERTY value "<NAME>" on entity "<NAME>" is invalid due to error: "<NAME>".
ID:22725 Intel Enpirion device will not be supported in a future release of the Intel Quartus Prime Software.
ID:22726 Detected Intel Enpirion slave device "<Intel Enpirion slave device>". Intel Enpirion device will not be supported in a future release of the Intel Quartus Prime Software.
ID:22727 Design uses Tile IP for instance "<name>" of entity "<name>" but the selected device "<name>" does not support it.
ID:22728 Synthesis is run on design with Tile IP for instance "<name>" of entity "<name>" but the support logic has not been generated.
ID:22729 Found different distances, <distance> and <distance>, between blocks <block_name> and <block_name>
ID:22730 RAM Primitive "<atom_name>" parameter <parameter_name> value <value> is no longer supported for the target device.
ID:22731 Target device <device> at device index <number> does not support attestation certificate generation.
ID:22732 Invalid certificate type \'<value>\'.
ID:22733 EMIF system <name> is not assigned to contiguous banks. Assign EMIF pins to contiguous banks in order to generate a valid EMIF system.
ID:22734 Transceiver speed <XcvrSpeed>GHz required for IP '<HPath>' using transceiver type '<XcvrType>' in modulation '<Modulation>' is higher than the maximum speed <AllowedSpeed>GHz at speed-grade <SpeedGrade> for chosen device '<OPN>'.
ID:22740 Failed to find migration part ID corresponding to part "<device name>" in DEVICE_MIGRATION_LIST assignment.
ID:22743 Cannot load Tile Assignment design file! Please run Design Analysis to generate the design file.
ID:22744 Your Tile Assignment Editor assignments have been saved.
ID:22745 <old_name> is deprecated. Use <new_name> to avoid the warning.
ID:22746 There should be one block for the master clock channel within the reconfiguration group <name>, but found <number> building blocks
ID:22747 Value <original default value> for QSF Assignment <assignment name> is not supported. Hence changing the value to <new default value>
ID:22749 Unable to determine preserved clock tree for signal <source>. To specify the intended clock region, a Clock Region assignment can be applied to the source in the original compile.
ID:22750 Clock routing from this source is also driving <destination>.
ID:22751 An HPS file is not provided but the configuration order is set as "HPS First"
ID:22752 Detected project compiling. Do you want to monitor the compilation?
ID:22753 Sending request to generate attestation certificate(s) on device index <number>.
ID:22754 Generating attestation certificate(s) on device index <number>.
ID:22755 The design uses <number> block(s) that uses the port <port_name>, but only <number> location(s) exist in tile <tile_name> of type <tile_type>
ID:22756 Verilog HDL warning at <location>: illegal index value for '<string>'
ID:22757 Verilog HDL error at <location>: attribute instance with system timing check violates Verilog syntax
ID:22758 Verilog HDL warning at <location>: illegal entry at <string>:<number> for index <number> in range [<number>:<number>]
ID:22759 Verilog HDL error at <location>: nested `include file depth limit <number> was exceeded
ID:22760 Verilog HDL warning at <location>: elements or members of dynamic variables not declared in checker will not be referenced in checker
ID:22761 Verilog HDL error at <location>: cannot compare type 'chandle' to type '<string>'
ID:22762 Verilog HDL error at <location>: complex non-ANSI port '<string>' cannot be referred by name
ID:22763 Verilog HDL error at <location>: static qualifier for constraint block '<string>' does not match pure constraint
ID:22764 Verilog HDL warning at <location>: external constraint block cannot be defined for pure constraint '<string>'
ID:22765 VHDL error at <location>: this construct is only supported in VHDL 1076-2019
ID:22766 VHDL error at <location>: '<string>' is not an uninstantiated protected type id
ID:22767 System PLL output '<PLLPortName>' of system clock IP '<ClkIPName>' does not drive the system clock of any F-tile IP. Regenerate this system clock IP after disabling the System PLL that will not drive the system clock port of any IP.
ID:22768 Cannot synthesize true dual-port RAM logic "<name>". This RAM is set to read-during-write mixed-port mode with the old-data parameter enabled, which is not supported by the selected device family.
ID:22769 Design uses Tile IP for instance "<name>" of entity "<name>" but the selected device "<name>" does not support it.
ID:22770 Dropping constraint on port "<port>" of instance "<hpath>"
ID:22771 In the altera_syncram Intel FPGA IP core, port <name> cannot be connected when parameter <name> is set to <name> for the target device family <name>
ID:22772 In the altsyncram Intel FPGA IP core, port <name> cannot be connected when parameter <name> is set to <name> for the target device family <name>
ID:22773 In the altdpram Intel FPGA IP core, port <name> cannot be connected when parameter <name> is set to <name> for the target device family <name>
ID:22776 Do you want to save changes to the assignments?
ID:22777 Unable to inject faults because no license for Fault Injection Intel FPGA IP Core (6AF7_D028) was found.
ID:22779 The instance assignment "target <assignment target>" uses deprecated "entity:inst" style and has been changed into "<assignment target>".
ID:22780 Verilog HDL error at <location>: '<string>' is already declared in the bind target scope of '<string>'
ID:22781 Verilog HDL warning at <location>: default qualifier is missing for unnamed clocking block
ID:22782 Verilog HDL error at <location>: expression of '<string>' type is not allowed in concatenation
ID:22783 Verilog HDL warning at <location>: a constructor shall not be declared as a static method
ID:22784 Verilog HDL warning at <location>: hierarchical references in type operator is an extension of the LRM
ID:22785 Verilog HDL warning at <location>: always_ff block does not infer flop
ID:22786 Verilog HDL warning at <location>: function '<string>', with side effects cannot be called from constraint
ID:22787 Verilog HDL error at <location>: use of 'force' in this context is not supported for synthesis
ID:22788 Verilog HDL error at <location>: multiple 'force' assignments on '<string>'
ID:22789 VHDL warning at <location>: ignoring the contents of protected block
ID:22791 RTL SDCs were detected, but failed to load.
ID:22792 Intel Quartus Prime detected External Memory Interface <EMIF System Name> has Address/Command sub-bank placed not in the center sub-bank. It spans sub-bank <Left-most sub-bank> to <Right-most sub-bank> but the Address/Command sub-bank is placed in <AC sub-bank>. Refer to External Memory Interface Intel Agilex FPGA IP User Guide for details on sub-bank ordering.
ID:22793 The Timing Analyzer is analyzing <number of latches> combinational loops as latches. To see the list of latches that were not entered as explicit comb loops in design files, view the "User-Specified and Inferred Latches" table in the Synthesis report.
ID:22794 Invalid Beta counter value \'<value>\'
ID:22795 Device <name> is not supported for beta certificate generation.
ID:22796 Quit monitoring the process. Does not stop the process
ID:22799 Anti-tamper response is disabled. QSF settings related to anti-tamper will be disabled in the SOF.
ID:22800 <filename> not found. Specify an existing beta certificate file to append the device ID into it.
ID:22801 The assignment (<variable type> : <variable value>) is not supported by the specified Agilex device.
ID:22802 RAM Primitive "<atom_name>" parameter <parameter_name> can be set only to value <value> for the target device.
ID:22804 Ignoring noprune assignment on target "<target>" because it is a RAM. Try also using (*no_ram*) if you want a collection of registers with the noprune assignment.
ID:22805 The period, rise edge, or fall edge of clock: <Clock Name> was found to be outside of the range of supported time values. The minimum supported time value is <Minimum Illegal Delay> and the maximum supported time value is <Maximum Illegal Delay>. This clock will be ignored.
ID:22807 The the relationship between source clock: <Src Clock Name> and destination clock: <Dst Clock Name> is outside of the legal time range due to large clock period or large multicycle. The <Multicycle Type> multicycle on <Src Clock Name> is <Multicycle Start value>, on <Dst Clock Name> is <Multicycle End value>. The maximal limit of clock relationship is <Maximum Delay>.
ID:22808 Invalid chip select value \'<number>\'.
ID:22811 The specified block <block_name> cannot be placed at the location <location> as the block requires stream(s) <id_set> in an Ethernet <integer>g block but the location only supports stream(s) <id_set>.
ID:22812 The specified block <block_name> cannot be placed at the location <location_name> because it uses a <integer>g transceiver that the location does not support
ID:22816 A license for the Intrinsic ID PUF feature was not detected. Support for this feature is not enabled. Contact Intrinsic ID for an appropriate license.
ID:22819 The option assigned for assignment (<variable type> : <variable value>) is not supported.
ID:22820 Verilog HDL error at <location>: cannot omit 'with' clause for method '<string>'; corresponding arithmetic or boolean reduction operation is not defined for element type of '<string>'
ID:22821 Verilog HDL error at <location>: virtual interface variable '<string>' cannot be used outside procedural blocks
ID:22824 Critical Warning message
ID:22826 Target device at device index <number> does not support the compact certificate file (.ccert) with pr_slot value of <number>. The value must be <number>.
ID:22827 Maximum numbers of device IDs reached. Total number of <max_number> is allowed.
ID:22828 EMIF system <EMIF name> has <Number of lanes current> gap lanes. EMIF systems with constrained pin assignments can have up to <Number of lanes allowed> gap lanes. Modify EMIF pin assignments to move EMIF lanes closer together to generate a valid EMIF system.
ID:22829 Port "<name>" does not exist in macrofunction "<name>".
ID:22830 Port "<name>" does not exist in macrofunction "<name>".
ID:22831 Port at position <number> does not exist in macrofunction "<name>"
ID:22832 Port at position <number> does not exist in macrofunction "<name>"
ID:22833 Cannot display block. The located block is not a block diagram.
ID:22834 Verilog HDL warning at <location>: illegal comparison operation on packed type and string
ID:22837 Cannot open Tile Assignment Editor! Manually configuring a multi-rate IP instance in a reconfiguration group is currently not supported by Tile Assignment Editor. Please edit your assignments in the Assignment Editor or in your preferred text editor.
ID:22839 Failed to <value>
ID:22847 The MBR partition (type 0xA2) for configuration data storage does not exist. The generated programming file will not support ASx4 configuration.
ID:22848 Illegal value "<name>" set for parameter "<name>" on ATOM "<name>". The valid value for this parameter is "<name>" /ECUT_LEGALITY_RULE_CUT_ATOM_ENUM_DATA_PARAM_RULE_E
ID:22849 Intel FPGA IP instantiated in the design requires the DEVICE_INITIALIZATION_CLOCK option to be set to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ or OSC_CLK_1_125MHZ. This assignment is missing in the QSF file.
ID:22850 Generating attestation IPCS URLs on device index <number>.
ID:22851 IOPLL "<Upstream IOPLL atom name>" drives another IOPLL but it's not configured as a upstream IOPLL.
ID:22852 Verilog HDL error at <location>: unexpected non-printable character with the hex value '0x<number>'
ID:22862 During reporting, the detailed clock path to node <Node> for clock <Clock> was not found. The slacks reported are accurate but the detailed clock path cannot be reported.
ID:22863 Found an IOPLL cascade chain of two or more fabric IOPLLs. Fabric IOPLLs cannot be cascaded together.
ID:22864 Cannot locate MIF File: "<name>".
ID:22867 System clock inputs of all IPs in the Dynamic Reconfiguration group must be driven by the same system PLL output. IPs in the Reconfiguration group hierarchy '<DrGroup>' are driven by different system PLL outputs:
ID:22868 Reference clock inputs of all IPs in the Dynamic Reconfiguration group must be driven by the same system clock IP. IPs in the Reconfiguration group hierarchy '<DrGroup>' are driven by different system clock IP:
ID:22870 All Reconfigurable IPs driven by one system clock IP must be controlled by a single Dynamic Reconfiguration controller IP. Reconfigurable IPs driven by system clock IP '<SysClkIp>' are controlled by multiple controller IPs:
ID:22871 All Reconfigurable IPs controlled by one Dynamic Reconfiguration controller IP must be driven by a single system clock IP. Reconfigurable IPs controlled by controller IP '<DrController>' are driven by multiple system clock IPs:
ID:22872 The extswitch input port of IOPLL "<IOPLL atom name>" is not connected in switchover manual mode.
ID:22873 The refclk1 input port of IOPLL "<IOPLL atom name>" is not connected in switchover mode.
ID:22879 The location <location> in tile <tile> has multiple nets assigned
ID:22880 Net <name>
ID:22881 RAM logic "<name>" is uninferred because the RAM dataout registers are powered up to high
ID:22882 Can't display clock network diagram -- no data available
ID:22883 The cascade_out port of IOPLL "<IOPLL atom name>" is connected to multiple downstream IOPLLs.
ID:22884 The current device does not support the ACR_CONFIGURATION_FILE assignment
ID:22885 The XML file "<filename>" from the ACR_CONFIGURATION_FILE assignment cannot be located.
ID:22886 Fanout connections between atoms "<atom1>" and "<atom2>" can be added only in the same netlist.
ID:22887 All initiators connected to the target (<name>) do not use the same base addresses.
ID:22888 Initiator (<name>) connected to the target (<name>) uses base address of (<initiator_base_address>), does not match initiator (<name>) with base address of (<initiator_base_address>).
ID:22889 This design was generated using the DNI flow.
ID:22890 This information is available only for generated clocks. (located at <SDC Location>)
ID:22891 Monitoring mode ended.
ID:22892 The signal carried by "<IOPLL port name>" port of IOPLL "<IOPLL atom name>" must remain in the FPGA.
ID:22893 Invalid I/O standards are used with LVDS SERDES IP instance <name>.
ID:22895 Multiple reference clock input ports {<InRefClkPorts>} of system clock IP are driven by the same clock source '<ClkSrcName>'. Ensure that one clock source drives a single reference clock input port of a system clock IP.
ID:22897 No printer detected.
ID:22898 Ignoring PLACEMENT_EFFORT_MULTIPLIER because it is set to a value greater than 1.0, which is not supported.
ID:22899 Synthesis dropped constraints during Technology Mapping
ID:22900 Dropped <port_type_name> pin constraints from node "<node_name>" for constraint <constraint_info>
ID:22901 Cannot open a new project for revision '<Revision>'. An existing project is already open.
ID:22903 A database with the name '<component_name>' already exists in the folder.
ID:22904 The option assigned for assignment (<variable type>) is not supported. Follow 7-bit PMBus target device addressing and should be up to 2 digits hexadecimal only.
ID:22905 Unable to load the reporting database '<report_name>'. The report database files are missing at '<file_path>'.
ID:22906 Unable to load the reporting database '<report_name>'.
ID:22907 Critical Assertion warning: <text>
ID:22908 The ECC setting of (<initiator_ecc_value>) for the initiator "<name>" does not match the ECC setting of (<target_ecc_value>) for the target "<name>".
ID:22909 The Intel Quartus Prime assembler does not accept designs that are compiled for RTL analysis. Disable RTL analysis and recompile the design before running the assembler.
ID:22910 There is no sweep hint available because nothing is swept away or the design has been swept already.
ID:22912 Unhandled exception: <msg>
ID:22913 The Intel Quartus Prime software encountered an unhandled exception, but it could not report the issue.
ID:22915 Verilog HDL error at <location>: vector is larger than 2**<number> bits
ID:22916 Verilog HDL info at <location>: <string> <string> translate off state
ID:22917 Verilog HDL error at <location>: local variable '<string>' is referenced without assigning a value
ID:22918 Verilog HDL error at <location>: dynamic range is not allowed in packed dimension
ID:22919 Verilog HDL error at <location>: no file name provided for restore
ID:22920 Verilog HDL error at <location>: Verilog library not found in file '<string>'
ID:22921 Verilog HDL error at <location>: hierarchy depth of <number> was exceeded; value of runtime-flag 'veri_max_hierarchy_depth_in_static_elab' may be increased if desired
ID:22923 Invalid input provided. <error_message>.
ID:22924 Input buffer can drive only ESRAM PLL.
ID:22927 Switching to and from RTL Analysis Flow requires cleaning the project. Do you want to continue?
ID:22928 All multirate IPs or IPs of the Dynamic Reconfiguration group must be DR eligible. The following IPs are not DR eligible:
ID:22930 The output voltage computed is out of range. The output voltage should be within 0 and 0xFFFF. Adjust the power management coefficients values that correspond to the selected voltage output format.
ID:22931 Node "<name>" is assigned to empty location or region. Such assignments are ignored.
ID:22932 Node "<name>" is assigned to an empty location or region. Such assignments are ignored.
ID:22933 The address ranges set for targets connected to the initiator "<name>" overlap with each other.
ID:22934 The base address 0x<target_base_address> set to the target "<name>" overlaps with the maximum address range of 0x<target_max_address> set by target "<name>".
ID:22935 Disconnect NoC atoms that are no longer in the same group. View the message in the System tab of the Messages window for details.
ID:22937 Disconnect "<name>" and "<name>" as there are no longer in the same group.
ID:22940 Failed to set hardware frequency to <frequency>Hz. No hardware is connected.
ID:22942 Failed to <value>
ID:22943 Verilog HDL error at <location>: config cell '<string>' is recursively used
ID:22944 The '<database>' database cannot be exclusively locked.
ID:22945 Detected current project revision compiling in the command-line. Starting a flow can cause both to fail. Do you want to continue?
ID:22950 The number of General Purpose Outputs (GPOs) used by the Readback Writeback IP and the auto-instantiated Intel Configuration Reset Release for Debug IP/user-instantiated Intel Reset Release IP exceed the device capacity. To fix the error do one of the following: Remove the Intel Reset Release IP from the design, or ground the Intel Configuration Reset Release for Debug IP that gets added from the debug flow, or fix the the Readback Writeback IP to use at most 19 General Purpose Outputs (GPOs).
ID:22951 File directory "<name>" does not exist.
ID:22952 Hardware frequency is set to <frequency>Hz.
ID:22953 The base address 0x<base_address> set to the target "<name>" is not aligned to blocks of 0x<block_size> (<size_bits> bits).
ID:22958 The following signals are in a related group that is partially constrained. Signals in the group cannot be optimized for clock domain crossings. This might detrimentally affect timing closure. Signals within a related group should ideally fanout to the same region
ID:22960 The following signals are in a related group that is fully constrained. Signals in the group cannot be optimized for clock domain crossings. This might detrimentally affect timing closure. Signals within a related group should ideally fanout to the same region
ID:22961 Signal <Signal Name> is constrained to <extent>
ID:22963 Open Intel Quartus Prime projects only from trusted sources. Do you want to continue?
ID:22964 Entity "<name>" cannot be elaborated because entity names with escaped identifiers are not supported.
ID:22965 Skipping "<name>" atom "<name>" used for QSF instance assignment 'NOC_CONNECTION'. It does not represent an atom in the design.
ID:22966 Restore Intel Quartus Prime project archives only from trusted sources. Do you want to continue?
ID:22967 OLD_DATA (Read First) is not supported for single port RAM instance "<instance>".
ID:22968 NEW_DATA_WITH_NBE_READ is not supported for single port RAM instance "<instance>".
ID:22969 QUAD port on RAM instance "<instance>" can only be implemented as logic.
ID:22970 The asynchronous address clear on RAM instance "<instance>" is not supported.
ID:22971 Input Output clock mode of RAM instance "<instance>" is not supported.
ID:22972 Unsupported ramstyle for RAM instance "<instance>".
ID:22973 Number of AXI Lite initiators (<num_initiators>) exceeds the maximum capacity on the NoC device (<max_initiators>).
ID:22976 Dynamic Reconfiguration controller IP specification is missing for IP or IPs {<IpNames>}. Use IP_COLOCATE assignment to specify a Dynamic Reconfiguration controller IP.
ID:22977 The base address value set for the target "<name>" overlaps with the target "<name>".
ID:22978 Routing has encountered congestion with the following signal(s)
ID:22979 Failed to generate file system partition.
ID:22980 IP instance <instance_name> using building block location <location> and IP instance <instance_name> using building block location <location> have conflicting settings for building block attribute <name> (<setting> != <setting>)
ID:22981 IP instance <instance_name> using building block location <location> and IP instance <instance_name> using building block location <location> are both exclusive from IP instance <instance_name> using building block location <location> and IP instance <instance_name> using building block location <location>, but they have conflicting settings for building block attribute <name> (<setting> != <setting>)
ID:22984 Invalid value for measurement_idx command option. The value must be 16-31.
ID:22985 Invalid value for auth_obj command option. The value must be either the path to the object file (.bin) or the SHA384 hash value of the object file for authentication. If SHA384 hash value is specified,the value must be a 48-byte HEX string.
ID:22986 Signal <Signal Name> is <extent>
ID:22987 When "<parameter_name>" for DSP block WYSIWYG primitive "<atom_name>" is selected, all the DSP block registers must be enabled.
ID:22988 Maximum precision of decimal places for <Name> is <Number>
ID:22990 During <optimization name> for node <root node name> synthesis ignored constraints on registers because precedence was given to optimizations.
ID:22991 Ignored <constraint> on <constrained node> during optimizations.
ID:22992 During <optimization name> for node <root node name> synthesis skipped optimization due to constraints.
ID:22993 <constraint> on <constrained node> prevented optimization.
ID:22997 Failed to find "<entity_name>" that has a PRE_COMPILED_MODULE assignment.
ID:22999 Please run Analysis and Elaboration successfully before using this editor.
ID:23002 Running <name> <name>
ID:23003 <number>
ID:23004 Processing started: <number>
ID:23005 Command: <name>
ID:23006 Quartus(args): <name>
ID:23007 <name>
ID:23008 <name> <name> was successful. <number> error<name>, <number> warning<name>
ID:23009 <name> <name> was unsuccessful. <number> error<name>, <number> warning<name>
ID:23010 Peak virtual memory: <number> megabytes
ID:23011 Peak virtual memory: <number> megabytes
ID:23012 Processing ended: <number>
ID:23013 Processing ended: <number>
ID:23014 Elapsed time: <number>
ID:23015 Elapsed time: <number>
ID:23016 Total CPU time (on all processors): <number>
ID:23017 Total CPU time (on all processors): <number>
ID:23018 Tcl Script File <name> not found
ID:23019 Additional arguments found in Tcl shell mode: <name>. -s | -shell option does not require additional arguments.
ID:23020 Additional arguments found before a Tcl mode argument
ID:23021 Long option --<name> does not take an argument
ID:23022 Value for long option --<name> must be "on" or "off" with default set to "on"
ID:23023 Long option --<name> requires an argument. Refer to --help for legal arguments
ID:23024 Unknown long option --<name>. Refer to --help for legal options
ID:23025 Short option -<name> takes an argument. Refer to --help for legal arguments.
ID:23026 Argument file <name> not found
ID:23027 Unknown short option -<name>. Refer to --help for legal options.
ID:23028 Unknown argument "<name>". Refer to --help for legal arguments.
ID:23030 Evaluation of Tcl script <name> was successful
ID:23031 Evaluation of Tcl script <name> unsuccessful
ID:23032 Parsing of argument file <name> failed at line <number>, near <text>
ID:23033 The --<name> option must be specified when using the --<name> option
ID:23034 At least one of the --<name> options must be specified when using the --<name> option
ID:23035 Tcl error: <name>
ID:23036 Cannot read file <name> -- make sure you have permission to read the file
ID:23037 The --64bit option is no longer supported. Install the 64-bit version of the Quartus Prime software for 64-bit support
ID:23038 Using INI file <name>
ID:23040 <message> by device <name>.
ID:23043 Base address of block "<name>" is not unique, overlaps with base address of "<name>" at address "<address>".
ID:23044 CRL distribution point in attestation must contain a valid HTTPS URL.
ID:23045 Verilog HDL error at <location>: '<string>' is not a property of the calling object of class randomize call
ID:23047 Verilog HDL warning at <location>: illegal type parameter expression with hierarchical name containing type name '<string>'
ID:23048 One or more partitions (<partition_name>) use "auto" or "start" addressing modes. Use the "block" addressing mode, so that the partition or partitions can fit a larger image that might be deployed in the future.
ID:23049 Parameters used for IP "<ip_name>" instance "<inst_name>":
ID:23050 Parameter "<param_name>" value "<param_value>" type "<param_type>"
ID:23051 NIOS data memory size <mif_size>KBytes of Dynamic Reconfiguration Controller IP <instance_name> is smaller than required MIF Size of <mif_size>Bytes to store the data in NIOS Memory
ID:23053 Missing <missing_assignment> assignment from <initiator_type> atom "<initiator_name>" to <target_type> atom "<target_name>" but found <found_assignment> assignment of this pair.
ID:23054 No NOC_CONNECTION or NOC_TARGET_BASE_ADDRESS QSF assignments found for <atom_type> atom "<name>".
ID:23055 <rden> port is connected in altera_syncram megafunction. <ram_block_type> block can now be driven by rden signal
ID:23059 <rden> port is connected in altsyncram megafunction. <ram_block_type> block can now be driven by rden signal
ID:23060 <rden> port is connected in altdpram megafunction. <ram_block_type> block can now be driven by rden signal
ID:23061 Import entity "<entity_name>" in library "<library_name>" from precompiled component database "<qdb_path>".
ID:23063 Option <name>="<value>" will be dropped.
ID:23064 <type> pin "<name>" of module instance "<name>" is not connected. Its options will not be propagated.
ID:23065 Remote update mode must have a factory configuration page (Page 0) and the page address must start at 0x20.
ID:23066 <Signal Name> cannot be placed within row clock region <extent> because the region is fully occupied. Capacity is <row clock capcity> signals.
ID:23069 Do you want to save the changes to the NoC assignments?
ID:23070 An IO error occurred while copying init file from "<NAME>" to "<NAME>". The error reported: "<NAME>"
ID:23071 An IO error occurred while trying to create directory "<NAME>". The error reported: "<NAME>"
ID:23072 There is a problem with initialization file "<NAME>" on component "<NAME>". The warning reported: "<NAME>"
ID:23073 Could not find initialization file "<NAME>" on component "<NAME>".
ID:23074 Unable to load online design examples. Please check the internet connectivity configuration by clicking the "More settings" button.
ID:23075 Could not find initialization file "<NAME>" on component "<NAME>".
ID:23076 The design was compiled by using the DNI flow that is not supported for version-compatible export yet.
ID:23078 When the parameter "<parameter>" is enabled for RAM Primitive "<atom_name>", the "<atom_name>" atom and "<atom_name>" atom must be connected.
ID:23079 Action data '<name>' is invalid. It either contains special characters or has data length more than <len> bytes.
ID:23080 Incomplete bitstream is used in the programming file generation. As a result, the generated programming file may not configure correctly on the device.
ID:23081 Design example download directory is invalid or unwritable. Check the download directory by clicking "More settings".
ID:23082 PCIe IP port '<pcie_ip_port_hpath>' at '<pcie_sys_freq>' in the half-clock adapter mode requires system clock frequency of '<2x_pcie_sys_freq>'. System clock frequency of '<sysclk_sys_freq>' for IP port '<sysclock_ip_port_hpath>', driving the system clock port of PCIe IP, does not meet this requirement.
ID:23083 UPLL2H_HBMC_CLK port of HBMC "<name>" must be driven by PLL clock
ID:23084 PLL atom "<name>" is being configured as UIB PLL, and thus does not support user reset
ID:23085 <error message>
ID:23087 <warning message>
ID:23088 <message>
ID:23089 NIOS data memory size <mif_size>Bytes is needed to store the data for Dynamic Reconfiguration Controller IP <instance_name>
ID:23092 <Signal Name> is routed to this row clock region
ID:23093 Secure Partial Reconfiguration Mask will not be generated because the targeted device family does not support this feature.
ID:23095 Weak pull-down option is set to 'ON' for pin <name>, but setting is not supported by I/O standard <name>.
ID:23096 Schmitt trigger option is set to 'ON' for pin <name>, but setting is not supported by I/O standard <name>.
ID:23098 One or more blocks are configured incorrectly and will not have the desired functionality. <Full error message from ini>
ID:23100 A calibrated termination logic option is set to <name> for <name> pin <name>, but setting is not supported by GPIO pins
ID:23101 Port "<name>" does not exist in the current RTL design or the stub file but exists in the snapshot from the provided Partition Database File (.qdb).
ID:23102 Port "<name>" exists in the current RTL design or the stub file but does not exist in the snapshot from the provided Partition Database File (.qdb).
ID:23103 FHT reference clock input port '<IPPortName>' of IP '<IPName>' is driven by '<DrvName>' instead of the FHT reference clock output of system clock IP. The valid FHT reference clock ports of system clock IP are {<ValidDrvPortNames>}.
ID:23106 Number of NoC groups (<num_groups>) exceeds the maximum (<max_groups>).
ID:23107 Number of NoC groups (<num_groups>) exceeds the maximum (<max_groups>).
ID:23109 The Quartus Database File "<archive>" contains a full design and cannot be imported with the import_block command, or as a QDB File Partition assignment.
ID:23110 The command (<constraint command>) contains an invalid delay time value '<constraint time value>'.
ID:23111 NoC target "<target>" is from group "<target_group>" but is connected to initiator "<initiator>" from group "<initiator_group>".
ID:23113 Failed to add requested readback functionality to latch "<latch_name>" because "<failure_reason>".
ID:23115 Instance "<instance_name>" instantiates an entity "<entity_name>" that is not supported in an SASIC flow.
ID:23117 Clocks automatically promoted to use the global network have contributed to clock routing congestion. Automatic global promotion can be disabled in the design and/or promotion of these signals can be manually controlled with the Global Signal assignment to try and resolve congestion.
ID:23118 The device family from the input file (<name>) is not supported for the "-i" or "--info" option. Ensure that the device family for the input file is supported.
ID:23119 Missing <missing_assignment> assignment from <initiator_type> atom "<initiator_name>" to <target_type> atom "<target_name>" but found <found_assignment> assignment of this pair.
ID:23120 No NOC_CONNECTION or NOC_TARGET_BASE_ADDRESS QSF assignments found for <atom_type> atom "<name>".
ID:23121 uNOC atom <string> has no legal placement. The atom is constrained outside its NOC initiator (<string>) column <number>.
ID:23122 The reference clock input port of NoC Clock Control IP "<name>" must be driven exclusively from the top-level with no other fan-outs. The current driver "<name>" fans out to more than one destination.
ID:23123 uNOC group ID <number>, subgroup ID <number>, beats <number> in NOC initiator <string> has no legal placement due to conflicting constraints.
ID:23124 uNOC group ID <number> in NOC initiator <string> has no legal placement due to conflicting constraints.
ID:23125 <name>. View the message in the System tab of the Messages window for details.
ID:23126 Base address "<base_address>" of "<ipath name>", "<tpath name>" connection is overlapped with base address of "<overlapped_paths>" connection.
ID:23136 Current RTL design or the stub file use entity "<stub_entity>" which does not match with the entity "<import_entity>" import from the Partition Database File (.qdb).
ID:23137 Entity <Entity Name> is attributed to <Source Files> source files.
ID:23138 <Message String>
ID:23139 "<ipath name>", "<tpath name>" connection has no base address.
ID:23141 The constraint target '<Target input string>' does not specify a type and will be inferred. This may result in unexpected behaviour. Consider using a '[dni::get_<type> ...]' command instead. File: <Location>
ID:23142 RTL SDCs were detected, but failed to load.
ID:23143 <Message String> File: <Location>
ID:23144 <Signal Name>
ID:23145 Top design <text> '<text>' set with value '<text>' from user settings
ID:23146 The design places <number> block(s) that use CVP in tile <tile_name>, but only <number> block(s) exist in the tile
ID:23147 <Message String> File: <Location>
ID:23148 Port <name> of multiplexer <name> id <number> has conflicting net names <name> and <name>
ID:23149 Port <name> of multiplexer <name> has conflicting net names <name> and <name>
ID:23151 Failed to execute command: <command_name>
ID:23153 An inverted clock pin of flip flop (<name>) with register packing is not allowed.
ID:23155 The database was generated with a different database engine. Do you want to overwrite the database for revision "<name>" created by <number>?
ID:23156 RX equalization is set to <name> for pin <name>, but setting is not supported by I/O standard <name>.
ID:23158 Cannot create a dynamic reconfiguration group with an empty name.
ID:23159 Cannot create a dynamic reconfiguration group named <group_name> as it already exists.
ID:23160 The IO Standard setting for "<Instance name>" must be set to a True Differential IO Standard. Reference clocks and external clock outputs support only True Differential IO Standards
ID:23161 No <Name> objects matched <Name>
ID:23162 Filtering across ten or more logic levels increases processing time. Do you want to continue?
ID:23165 The refclk pin "<name>" is not in the same IO bank as the design
ID:23166 During hold fix-up, <num_non_routable_failing_arcs> non-routable connections are found and ignored.
ID:23167 During hold fix-up, <num_large_failing_arcs> connections with hold failures larger than <max_hold_failure> ps are found and ignored.
ID:23170 Verilog HDL error at <location>: illegal use of assignment pattern outside of an assignment-like context
ID:23171 Verilog HDL warning at <location>: illegal call of array ordering method '<string>' on associative array
ID:23172 Verilog HDL error at <location>: built-in method 'match' violates IEEE 1800 syntax
ID:23173 Verilog HDL error at <location>: evaluation of built-in method 'match' is not supported
ID:23174 Verilog HDL error at <location>: strength can be specified only for assignments to nets
ID:23175 Verilog HDL warning at <location>: not-net '<string>' cannot be connected to the output of gates with driving strength
ID:23176 Verilog HDL error at <location>: built-in method 'prematch' violates IEEE 1800 syntax
ID:23177 Verilog HDL error at <location>: evaluation of built-in method 'prematch' is not supported
ID:23178 Verilog HDL error at <location>: built-in method 'postmatch' violates IEEE 1800 syntax
ID:23179 Verilog HDL error at <location>: evaluation of built-in method 'postmatch' is not supported
ID:23180 Verilog HDL error at <location>: illegal virtual interface operand for operator '<string>'
ID:23181 Verilog HDL error at <location>: illegal argument in string comparison; expected string or string literal
ID:23182 Verilog HDL warning at <location>: writing to the same variable '<string>' multiple times may be dependent on evaluation order
ID:23183 Verilog HDL error at <location>: first argument of '$<string>' must be a file name
ID:23184 Verilog HDL error at <location>: first argument of '$<string>' must be a memory or integral variable
ID:23185 Verilog HDL error at <location>: cannot mix packed and unpacked type for operator '<string>'
ID:23186 Verilog HDL error at <location>: illegal casting type; dimension is not allowed with reference of type '<string>'
ID:23189 File I/O error has occurred. Unable to write to file "<stp_filename>".
ID:23190 Design Assistant Results: All <number of disabled rules> rules disabled in snapshot '<snapshot name>'
ID:23191 Cannot place OE Delay Chain because output buffer '<name>' does not have OE connection.
ID:23192 Cannot find the port "<port>" in the Intel FPGA IP Evaluation Mode entity "<entity>". Intel FPGA IP Evaluation Mode specification file is invalid.
ID:23193 The top-level entity cannot be an Intel FPGA IP Evaluation Mode entity.
ID:23194 Cannot read the Intel FPGA IP Evaluation Mode specification file -- "<reason>"
ID:23195 Intel FPGA IP Evaluation Mode feature is turned on for the following cores:
ID:23196 "<name>" will use the Intel FPGA IP Evaluation Mode feature.
ID:23197 Intel FPGA IP Evaluation Mode (Simulation-Only) feature is turned on for all cores in the design.
ID:23198 Some cores in this design do not support the Intel FPGA IP Evaluation Mode feature.
ID:23199 "<name>" does not support the Intel FPGA IP Evaluation Mode feature.
ID:23200 EDA simulation disabled for this design.
ID:23201 "<name>" cannot be simulated with Intel FPGA IP Evaluation Mode (Simulation-Only).
ID:23205 The current OPN <text> does not support the SM4 encryption method for the Inline Cryptographic Acceleration. Use a different OPN that supports the SM4 encryption method.
ID:23207 OCP endpoint .vhd file or one of its dependencies is missing or corrupted.
ID:23209 Design contains configuration via protocol (CvP) capable IP. However. it is not enabled. Enable the CvP Settings section of the Device and Pin Options dialog box.
ID:23210 ECO: Node cannot be found in the netlist.
ID:23213 Inverted clock "<clock_port>" found on instance "<ram>" .
ID:23217 Detected that recovered clock output '<outCdrClkPort>' of system clock IP '<ClkIPName>' is driving loads other than top level output port. It is driving the following loads:
ID:23218 Cannot overwrite the database for revision "<name>" created by <number>. The database is being used by another process, is read-only, or both.
ID:23220 Detected that recovered clock output '<outCdrClkPort>' of protocol IP '<IPName>' is driving loads other than FGT CDR clock input of System Clock IP. It is driving the following loads:
ID:23221 <Number of signals> signal<Plural> not promoted to use global clock network
ID:23222 <Signal Name> (<Number of fanouts> fanout)
ID:23223 Detected that recovered clock output of protocol IP '<IPName>' is driving the following <ExtraMsg>
ID:23224 The recovered clock output port '<outCdrClkPort>' of system clock IP '<ClkIPName>' is used but its corresponding input port '<inCdrClkPort>' is not connected to a valid source.
ID:23226 The selected flash loader and input file device family (<device_family>) do not match.
ID:23227 The IOPLL "<IOPLL name>" is used for either dedicated path for PLL cascading or for EMIF. Cannot connect the refclk to non-PLLs.
ID:23234 Instance "<NAME>" bound to "<NAME>" is not supported.
ID:23236 Cannot access list of signals from Questa simulator.
ID:23237 Verilog HDL error at <location>: 'local::' may only be used within an inline constraint block
ID:23238 Verilog HDL error at <location>: illegal class casting from incompatible type
ID:23239 Verilog HDL error at <location>: illegal cast operation; target class is not in the inheritance tree
ID:23240 Verilog HDL error at <location>: string type index to wildcard associative array is not allowed
ID:23241 Verilog HDL error at <location>: genvar declarations are not allowed in package or compilation unit
ID:23242 Verilog HDL warning at <location>: constant epression is not allowed in unique constraint
ID:23243 Verilog HDL warning at <location>: implicit net assignments are not allowed in package
ID:23244 Directory "<name>" does not exist.
ID:23245 Global AVMM IP '<GAVMMName>' is not associated with any F-tile protocol IP. Associate right set of protocol IPs with GAVMM IP via IP_COLOCATE QSF assignment.
ID:23246 Global AVMM IP '<GAVMMName>' is not associated with any F-tile protocol IP. Associate right set of protocol IPs with GAVMM IP via IP_COLOCATE QSF assignment.
ID:23247 No board selected. Select a board.
ID:23250 Command-line option --estimate_power=off is ignored when the --output_epe or --output_ptc option is used.
ID:23251 No error or warning found.
ID:23252 PCIE Topology <Topology Type> cannot be used when CVP is enabled in <Tile type> Avalon Streaming Intel FPGA IP for PCI Express.
ID:23259 RZQ_GROUP is not defined for the pad "<name>".
ID:23260 The RZQ group "<name>" in the QSF assignment does not match with the existing RZQ group in the project.
ID:23262 Cannot route signal "<signal_name>" to node "<atom>". The Fitter exited early during the routing of a HiPI.
ID:23264 More than two sets of I/O configurations are assigned to the same RZQ Group.
ID:23265 Failed to route connection<reason>
ID:23266 From <signal> (<fanout> fanout)
ID:23267 From <signal> (<fanout> fanout) via <clock_tree_status> clock tree routed to <region>
ID:23268 To <dst>
ID:23269 To <clock_tree_status> clock tree routed to <region>
ID:23270 The following <count> signal(s) conflicted
ID:23271 <signal> (<fanout> fanout)
ID:23272 <signal> (<fanout> fanout) via <clock_tree_status> clock tree routed to <region>
ID:23273 destination is driven from sector <sector>
ID:23274 RZQ_PIN_GROUP_NAME is not defined for the pad "<name>".
ID:23275 RZQ_PIN_GROUP_NAME "<name>" for the pad "<name>" has been assigned to a different RZQ pin.
ID:23276 Could not find usable path between <name>: <port name> and <name>: <port name>
ID:23277 Illegal assignment found between <atom_type> at "<atom_name>" and <atom_type> at "<atom_name>".
ID:23279 Hierarchical PR designs do not support PR bitstream security verification.
ID:23280 Illegal value <text> for <name> parameter in WYSIWYG primitive "<name>" -- value must be <text>
ID:23281 WYSIWYG primitive "<name>" is missing value for <name> parameter. Legal values for <name> parameter are <values>.
ID:23282 When in its current operating mode, WYSIWYG RAM primitive "<name>" cannot have <name> parameter
ID:23283 Can't recognize value for <name> parameter for WYSIWYG RAM primitive "<name>"
ID:23284 WYSIWYG RAM primitive "<name>" must have <name> parameter
ID:23285 WYSIWYG RAM primitive "<name>" uses <name> port, which is inconsistent with <name> parameter value
ID:23286 Correcting WYSIWYG RAM primitive "<name>" <name> parameter value to 1 since using <name> port
ID:23288 WYSIWYG primitive "<name>" has inconsistent parameter values <name> and <name>
ID:23289 WYSIWYG RAM primitive "<name>" has too many bits
ID:23290 WYSIWYG RAM primitive "<name>" has the use of <name> port declared, but the port is unconnected
ID:23291 Block type <name> for WYSIWYG RAM primitive "<name>" is not supported in target device family
ID:23292 WYSIWYG RAM primitive "<name>" you have specified an illegal operation mode
ID:23293 When in its current operating mode, WYSIWYG RAM primitive "<name>" "<name>" is out of range
ID:23294 WYSIWYG RAM primitive "<name>" has inconsistent values for <name>, <name>, <name>, and <name> parameters
ID:23295 WYSIWYG RAM primitive "<name>" in operation mode "<name>" uses an unsupported value for parameter "<name>"
ID:23296 In current operating mode, WYSIWYG RAM primitive "<name>" cannot have <name> port or parameter connected
ID:23297 WYSIWYG RAM primitive "<name>" in operation mode "<name>" uses an unsupported value for parameter "<name>"
ID:23298 WYSIWYG primitive "<name>" must use clk0 port.
ID:23299 WYSIWYG RAM primitive "<name>" port "<name>" and "<name>" cannot connect at the same time
ID:23300 WYSIWYG RAM primitive "<name>" must have the "<name>" port connected when "<name>" port is connected
ID:23301 WYSIWYG RAM primitive "<name>" must have "<name>" or "<name>" parameter
ID:23302 WYSIWYG RAM primitive "<name>" "<name>" and "<name>" must set to ena0 when clock enable 0 is used
ID:23303 WYSIWYG primitive "<name>" must use clk1 port if ena1 port is used
ID:23304 WYSIWYG RAM primitive "<name>" must have the <name> port connected
ID:23305 WYSIWYG RAM Primitive "<name>" mixed port read during write cannot set "<name>" in this operation mode.
ID:23306 WYSIWYG RAM primitive "<name>" maximum width ratio for Port A data width A and Port B data width is 4!
ID:23307 WYSIWYG RAM primitive "<name>" port "<name>" in "<name>" is not allowed to be connected!
ID:23308 WYSIWYG RAM primitive "<name>" "<name>" Mix Port Width with "<name>" in "<name>" is not allowed
ID:23309 WYSIWYG RAM Primitive "<name>" the mixed-port read-during-write must use don't care when operation mode is set to "<name>" .
ID:23310 WYSIWYG RAM primitive "<name>" cannot use "<name>" in true dual port.
ID:23311 WYSIWYG RAM Primitive "<name>" maximum for "<name>" in "<name>" is 2!
ID:23312 WYSIWYG RAM Primitive "<name>" the mixed-port read-during-write must use don't care or new_a_old_b when operation mode is set to "<name>" .
ID:23313 WYSIWYG RAM Primitive "<name>" cannot use "<name>" in simple quad port port.
ID:23314 WYSIWYG RAM Primitive "<name>" enables the ECC feature, which only can be implemented in 512 (depth) by 32 (width) in simple dual-port mode.
ID:23315 WYSIWYG RAM Primitive "<name>" cannot use ECC and byte-mask features at the same time.
ID:23316 WYSIWYG RAM Primitive "<name>" has set the parameter ECC_PIPELINE_STAGE_ENABLED to TRUE, but does not use the output registers of the RAM primitive.
ID:23317 WYSIWYG RAM primitive "<name>" cannot have "<name>" port connected because parameter "<name>" is not set.
ID:23318 WYSIWYG primitive "<name>" cannot have value for <name> parameter unless <name> parameter is set to <text> value
ID:23319 WYSIWYG RAM primitive "<name>". Only the "<name>" operating mode is allowed. Ensure that port A and port B data widths are the same when using coherent read mode.
ID:23320 WYSIWYG primitive "<name>" parameter "<name>" cannot be set to true when using coherent read mode.
ID:23321 WYSIWYG RAM Primitive "<name>" mixed port read during write cannot set "<name>" when enable_coherent_read is true.
ID:23322 WYSIWYG RAM primitive "<name>" cannot use coherent read and byte-enable mask features at the same time.
ID:23323 When in its current operating mode, WYSIWYG RAM primitive "<name>" "<name>" is out of range
ID:23324 WYSIWYG RAM primitive "<name>" must have the "<name>" port and "<name>" port connected to the identical clock source with identical clock unateness.
ID:23325 WYSIWYG RAM primitive "<name>" cannot have parameter "<name>" set to "<name>" when using coherent read mode.
ID:23326 When in its current operating mode, WYSIWYG RAM primitive "<name>" port "<name>" and "<name>" need to be connected
ID:23327 WYSIWYG RAM primitive "<name>" must have width of "<name>" port set to 8.
ID:23328 WYSIWYG RAM primitive "<name>" must have "<name>" parameter and set to true when enable_ecc_encoder_bypass is set
ID:23329 WYSIWYG primitive "<name>" parameter "<name>" cannot set to false when port "<name>" is connected.
ID:23330 WYSIWYG RAM primitive "<name>" cannot have "<name>" port and "<name>" connected because parameter "<name>" is not set.
ID:23332 WYSIWYG ALM640 primitive "<name>" has too many address lines on <name> port
ID:23334 In WYSIWYG primitive "<name>", parameter <name> can only be set to <name> when parameter <name> is set to <name>
ID:23335 WYSIWYG RAM primitive "<name>" when using "<name>", "<name>" need to be used
ID:23336 WYSIWYG RAM primitive "<name>" has different clock signals feeding bits of <name> input bus port
ID:23337 WYSIWYG RAM primitive "<name>" has mismatched <names> parameters for <name> port and <name> port
ID:23339 Cannot start "<name>" with argument: <arguments>.
ID:23340 Download path is empty. Specify a download path.
ID:23341 Encountered congestion <specifier> sector <sector>. Found <net_count> nets using nearby routing. (Device maximum is <device_max>)
ID:23344 WYSIWYG RAM primitive "<name>" ports "<name>" and "<name>" cannot be connected at the same time when using coherent read mode.
ID:23345 WYSIWYG RAM Primitive "<name>" uses ECC feature and the mixed-port read-during-write mode is set to old memory content. These two features cannot be used together.
ID:23346 WYSIWYG primitive "<name>" must use clk1 port if ena3 port is used
ID:23347 Can't find file "<path_checked>" required by the WYSIWYG "<wysiwyg_instance_name>" with the parameter "<parameter_value>" set to "<parameter_name>".
ID:23348 WYSIWYG "<wysiwyg_instance_name>" parameter "<parameter_name>" is empty, which is invalid.
ID:23349 The working directory is unwritable.
ID:23350 Duplicate group name entered.
ID:23351 Reading <SoR Constraints Count> SDC on RTL constraints.
ID:23353 No SDC file assignments detected, attempting to load a default SDC file: <Filename>.
ID:23354 By default, read_sdc on a synthesized snapshot loads only SDC-on-RTL constraints and SDC files with READ_DURING_POST_SYN_AND_POST_FIT_TIMING_ANALYSIS / READ_DURING_POST_SYN_AND_NOT_POST_FIT_TIMING_ANALYSIS assignments.
ID:23355 The Quartus assignment <assignment> tried to set a delay chain of <dly>ps to <target>, which is outside of the supported range (<start>ps - <end>ps).
ID:23356 Verilog HDL error at <location>: too few arguments to function/task call '<string>'
ID:23357 Verilog HDL warning at <location>: ref port '<string>' cannot be of net type
ID:23358 Verilog HDL warning at <location>: assignment pattern cannot be used in static casting
ID:23359 Verilog HDL warning at <location>: illegal use of assignment pattern as operand of equality operator
ID:23360 Verilog HDL warning at <location>: only simple identifiers of integral type are allowed as argument of <string> randomize call
ID:23361 Verilog HDL warning at <location>: no inferred clock found for this instance
ID:23362 Verilog HDL warning at <location>: illegal assignment to variable input port '<string>'
ID:23363 Verilog HDL warning at <location>: format specifier c cannot have unpacked argument (#<number>)
ID:23364 Verilog HDL error at <location>: undefined design '<string>' in VHDL bind instantiation
ID:23365 Verilog HDL error at <location>: illegal target for 'new' expression with size argument; expected dynamic array
ID:23366 Verilog HDL error at <location>: missing clocking block for default clocking indentifier '<string>'
ID:23367 Verilog HDL warning at <location>: 'const' cast is not allowed in constraint expression
ID:23368 Verilog HDL warning at <location>: streaming operators cannot be used in constraint expression
ID:23369 Verilog HDL warning at <location>: width (<number>) of randc variable '<string>' exceeds limit <number>
ID:23370 Verilog HDL warning at <location>: integral type index to associative array having string index type is not allowed
ID:23371 Parameter <name> is not supported for WYSIWYG primitive "<name>"
ID:23372 Duplicate node name entered.
ID:23373 Verilog HDL warning at <location>: packed array is not allowed as return type of DPI function
ID:23374 Verilog HDL error at <location>: task/function port '<string>' cannot be of net type
ID:23375 Verilog HDL warning at <location>: real type expressions are not allowed in a constraint declaration
ID:23376 Verilog HDL error at <location>: illegal assignment expression to '<string>' in match item list; requires local variables
ID:23377 Verilog HDL warning at <location>: <string> '<string>' was previously defined as <string>
ID:23378 Invalid value for entropy command option. The value must be a 32-byte hexadecimal number.
ID:23379 WYSIWYG LCELL COMB primitive "<name>" has illegal format for LUT_MASK parameter value -- value must be 16-digit hexadecimal number or 64-digit binary number format
ID:23380 WYSIWYG LCELL COMB primitive "<name>" must use LUT_MASK parameter
ID:23381 RAM name is "<name>"
ID:23382 Memory Initialization File or Hexadecimal (Intel-Format) File for RAM is not specified but MEM_INIT parameter exists -- setting initial value from the content of mem_init parameter
ID:23383 Memory size (<number>) in design file differs from memory size (<number>) in MEM_INIT parameter -- setting initial value for remaining addresses to 0
ID:23384 Memory size (<number>) in design file differs from memory size (<number>) in MEM_INIT parameter -- truncated remaining initial content value to fit RAM
ID:23385 ROM name is "<name>"
ID:23386 Memory Initialization File or Hexadecimal (Intel-Format) File for ROM is not specified
ID:23387 WYSIWYG primitive "<name>" has illegal value for <name> parameter
ID:23388 Too many debug fabrics required to instrument the design. Currently, only <max_fab> debug fabrics per design are supported.
ID:23390 You cannot tap nodes in different Partial Reconfiguration or Reserved Core regions with the same Signal Tap instance. Change your design so that, for each Signal Tap instance, all the taps are contained on one side of a Partial Reconfiguration or Reserved Core region boundary. The following nodes and their respective partitions were requested for Signal Tap instance <instance>: <node_spec>
ID:23391 The top-level I/O names: "altera_reserved_tck", "altera_reserved_tms", "altera_reserved_tdi", and "altera_reserved_tdo" are reserved. Change the names of the following I/Os to other names that are not reserved: <res_pin_spec>.
ID:23393 Cannot compile the design. Your project generates files with paths that exceed the maximum length allowed by the operating system. Move or rename the project directory to reduce the number of characters in the path. The following file paths exceed the operating system limits: <files_spec>
ID:23396 The Quartus Settings File (.qsf) contains a CREATE_PARTITION_BOUNDARY_PORTS assignment to node: "<target>" in an inappropriate hierarchy. No boundary port(s) will be created.
ID:23397 The Intel Quartus Prime software partially connected Signal Tap or other In-System debug instance "<name>" to <number> of the <number> requested data inputs, trigger inputs, acquisition clocks, and dynamic pins. Check the compilation report for more details.
ID:23398 Automatic debug logic insertion has failed.
ID:23399 The Intel Quartus Prime software is unable to infer placement of Signal Tap instance "<instance>". Signal Tap instance "<instance>" will be placed within partition "<partition>".
ID:23400 Design has partial reconfiguration partitions enabled and external scrubbing options is also enabled.
ID:23401 User design entity "<NAME>" defined in file "<NAME>" collides with megafunction name. Rename user entity.
ID:23402 <Message String> File: <Location>
ID:23403 <Message String> File: <Location>
ID:23405 The <name> device family is changing. If you do not change the device family name, the tool runs based on the Agilex 7 device family. Update the --family option with the new device family name.
ID:23408 Read temperature value is not supported. Do you want to update the temperature value to supported default value?
ID:23409 Threshold temperature value out of range.
ID:23410 The current OPN <text> does not contain any HPS CPU Core. Use a different OPN that has HPS CPU Core.
ID:23411 Can't read Memory Initialization File or Hexadecimal (Intel-Format) File <name> for ROM instance <name>. If the file exists, it is not in correct format.
ID:23412 Can't read Memory Initialization File or Hexadecimal (Intel-Format) File <name> -- setting all initial values to 0
ID:23413 Memory depth (<number>) in the design file differs from memory depth (<number>) in the Memory Initialization File "<name>" -- truncated remaining initial content value to fit RAM
ID:23414 Memory depth (<number>) in the design file differs from memory depth (<number>) in the Memory Initialization File "<name>" -- setting initial value for remaining addresses to 0
ID:23415 Can't find Memory Initialization File or Hexadecimal (Intel-Format) File <name> for ROM instance <name>
ID:23417 Memory Initialization File or Hexadecimal (Intel-Format) File "<name>" contains "don't care" values -- overwriting them with 0s
ID:23418 Can't find Memory Initialization File or Hexadecimal (Intel-Format) File <name> -- setting all initial values to 0
ID:23419 Missing instance name argument in the pcie option <option>.
ID:23420 Missing data file argument in the pcie option <option>.
ID:23421 Incorrect number of arguments in the pcie option <option>.
ID:23422 Missing instance name argument in the eth option <option>.
ID:23423 Missing data file argument in the eth option <option>.
ID:23424 Incorrect number of arguments in the eth option <option>.
ID:23425 The Quartus Prime Fitter cannot find routing connectivity from source <src_cell_name> on port <src_port_name> to destination <dst_cell_name> on port <dst_port_name> because the routing resource is used by:
ID:23426 Source <src_cell_name> on port <src_port_name> to destination <dst_cell_name> on port <dst_port_name>.
ID:23428 Error injected to LUTRAM bit, the injection to this LUTRAM bit will be discarded if the LUTRAM configured as a RAM.
ID:23430 Failed to read pcie override files: <reason>.
ID:23431 Failed to read ethernet override files: <reason>.
ID:23432 The file <file> does not exist.
ID:23433 Failed to read attribute "<attribute>" for entity "<entity_name>" with a PRE_COMPILED_MODULE assignment from the IP cache.
ID:23435 Hold fixing has been running for <run_time_string>. This usually happens when hold fixing requires multiple full-timing analyses.
ID:23436 I/O standard <name> on bidirectional pin <name> is not supported. The I/O standard is allowed only on unidirectional pins.
ID:23443 Verilog HDL warning at <location>: symbol '<string>' is not declared, assumed default net type '<string>'
ID:23444 Verilog HDL warning at <location>: local qualifier is used to access external object '<string>'
ID:23445 Verilog HDL info at <location>: mapped module '<string>' for '<string>' does not exist; creating it
ID:23446 Verilog HDL error at <location>: illegal select-expression; expected select-condition after '!'
ID:23447 Verilog HDL warning at <location>: use of string type in 'inside' constraint is an extension of LRM
ID:23448 Verilog HDL warning at <location>: property instances with disable iff cannot be used as operand of property expression
ID:23449 The WYSIWYG PSEUDO_DIFF_OUT primitive "<name>" does not support static OE value
ID:23450 WYSIWYG LCELL COMB primitive "<name>" must use sharein port when in shared arithmetic mode
ID:23451 WYSIWYG LCELL COMB primitive "<name>" must use all LUT input ports when in extended LUT mode
ID:23452 WYSIWYG LCELL COMB primitive "<name>" has LUT_MASK parameter that is dependent on one or more unconnected input ports
ID:23453 WYSIWYG LCELL flipflop primitive "<name>" must use <name> port if it uses <name> port
ID:23454 WYSIWYG LCELL flipflop primitive "<name>" must use <name> port if it uses <name> port
ID:23455 WYSIWYG LCELL flipflop primitive "<name>" must use <name> port or <name> port if <name> port is used
ID:23456 uNOC group ID <number>, subgroup ID <number>, beats <number> in NOC initiator <string> is illegal because it has <number> atoms. It must have 1, 2, 4, or 8 atoms.
ID:23457 uNOC group ID <number>, subgroup ID <number>, beats <number> in NOC initiator <string> is illegal because there is no atom at index <number>.
ID:23460 WYSIWYG "<name>" primitive has illegal value <text> for <name> parameter -- used default value of <number>
ID:23461 WYSIWYG "<name>" primitive has illegal value <text> for <name> parameter -- used value <number> and ignored other values
ID:23462 In this package, RNRC refclk2 pin for U20 is being shorted to U22 refclk2. To use the pin, make a short/common connection to U22 refclk2
ID:23463 In this package, RNRC U20's refclk2 pin is being shorted to U22's refclk2 pin. If you plan to use U20's refclk2 later, make a short/common connection to U22 refclk2
ID:23464 The selected design example uses a device family that is unsupported for the current Intel Quartus Prime version. Are you sure you want to continue?
ID:23466 Encountered congestion routing to the sector gate enable in sector <sector>. Found <net_count> clocks requiring sector gate enables in this sector. (Device maximum is <device_max>)
ID:23467 Encryption key storage location option <text> is not supported for this device.
ID:23469 The block <instance_name> did not set the following parameters
ID:23470 Parameter <name>
ID:23471 Download path "<name>" does not exist. Do you want to create it?
ID:23472 Cannot create download path "<name>"
ID:23475 Timing Analyzer is currently using the "<snapshot>" snapshot. Delays are estimates.
ID:23476 Failed to import user device part <device 1>. Same JTAG ID already exists on device part <device 2>.
ID:23478 Failed to update user device part <device 1> with JTAG ID <jtag idcode>. Same JTAG ID already exists on device part <device 2>.
ID:23482 Invalid temperature threshold. Enter a value between 95 and 120 inclusive
ID:23483 Output port <name> of I/O output buffer "<name>" has <name> fan-outs. The I/O output buffer is allowed to drive only one top-level pin.
ID:23484 Intel Quartus Prime support for BDF files ends soon. Convert BDF files to Verilog or VHDL for continued support. One instance of BDF files is <file path>.
ID:23485 DSP packing failed to respect the provided packing level assignment(s).
ID:23486 DSP packing failed to respect the packing level assignment set on DSP block: "<hpath>"
ID:23487 ML delay model is not available for this device family
ID:23489 Selected SMH contains an unassigned ASD region ID. For more information about assigning ASD region IDs, refer to the hierarchy tagging information in the SEU Mitigation User Guide for your device family
ID:23491 Failed final netlist checks.
ID:23492 The clock latency constraint was ignored. No valid clock targets found.
ID:23493 The collection of targets provided to the set_clock_latency command contains some non-clock targets.
ID:23494 The base address 0x<base_address> between initiator "<initiator>" and target "<target>" is not aligned to blocks of 0x<block_size> (<size_bits> bits).
ID:23495 NoC initiator "<initiator>" is from group "<initiator_group>" but is connected to target "<target>" from group "<target_group>".
ID:23496 For initiator "<initiator>", target "<target>" has an address range from 0x<base_address> to 0x<max_address> which overlaps with target "<target>" that is from 0x<base_address> to 0x<max_address>.
ID:23497 Base address "<base_address>" from initiator "<initiator>" to target "<target>" is invalid: "<msg>".
ID:23504 Found ASD region ID <number> in the design. Maximum supported ASD region ID for selected device is <number>. For more information about ASD region IDs, refer to the hierarchy tagging information in the SEU Mitigation User Guide for your device family
ID:23505 <Message String>
ID:23506 NoC atom "<name>" must be part of a NoC group(groups: "<groups>")
ID:23507 Number of NoC groups (<num_groups>) exceeds the maximum (<max_groups>)(groups: "<groups>")
ID:23508 NoC group "<name>" must contain at least one initiator, target, SSM and PLL.
ID:23509 There are two groups on the FPGA that allow <num_device_targets_0> and <num_device_targets_1> targets respectively. However, the current design does not fit because it needs <design_targets> targets in groups <design_targets_groups>.
ID:23510 There are two groups on the FPGA that allow <num_device_initiators_0> and <num_device_initiators_1> initators respectively. However, the current design does not fit because it requires <design_initiators> initiators in groups <design_initiators_group>.
ID:23511 Number of AXI Lite4 initiators (<num_initiators>) exceeds group capacity (<max_initiators>).
ID:23517 Missing "<bandwidth_type>" bandwidth from NoC connection from initiator "<initiator>" to target "<target>".
ID:23518 Missing <bandwidth_type> for NoC connection from initiator "<initiator>" to target "<target>".
ID:23519 <warning msg>
ID:23520 The changes to NoC assignments you are about to save have failed validation and the design will fail Synthesis as a result. Are you sure you want to save?
ID:23523 <Argument Name> collection with value <Collection Filter> must include input pins or output pins or nets
ID:23524 Invalid value. Do you want to change the value to the default value?
ID:23525 Target device supports a maximum of <number> firmware source files for programming.
ID:23527 No route for refclk connection from "<Refclk ibuf name>" to "<IOPLL name>". Promote refclk to a global clock or use a dedicated IOPLL refclk pin.
ID:23529 Invalid firmware source file <name>.
ID:23530 Missing <missing_assignment> assignment from <initiator_type> atom "<initiator_name>" to <target_type> atom "<target_name>" but found <found_assignment> assignment of this pair.
ID:23533 Verilog HDL warning at <location>: non-blocking assignment in final block is illegal
ID:23534 Verilog HDL warning at <location>: $bits system function cannot have an argument of Interface class type
ID:23535 Verilog HDL error at <location>: illegal index expression; expected integral type
ID:23536 Verilog HDL error at <location>: virtual interface type variable '<string>' is not allowed in continuous assignments
ID:23537 Verilog HDL warning at <location>: parameter '<string>' of bind instantiation '<string>' cannot be used in generate condition
ID:23538 Verilog HDL warning at <location>: querying system functions are only allowed on the first variable-size dimension
ID:23539 Verilog HDL warning at <location>: illegal zero or negative value for dimension in array querry function '<string>'
ID:23540 Verilog HDL warning at <location>: dimension value out of bounds in array querry function '<string>'
ID:23541 Verilog HDL warning at <location>: first argument of array querry function '<string>' is missing
ID:23542 Verilog HDL error at <location>: illegal size casting to zero or negative value for width
ID:23543 Verilog HDL error at <location>: illegal reference to clocking variable '<string>'
ID:23544 Verilog HDL error at <location>: reference to block/label id '<string>' is not valid in an expression
ID:23545 Verilog HDL error at <location>: continuous assignments to nettype nets can only have single value delays.
ID:23546 Verilog HDL error at <location>: continuous assignments to nettype net must be atomic
ID:23547 Verilog HDL error at <location>: illegal use of string literal as scope in assertion control task '<string>'
ID:23548 Verilog HDL error at <location>: controlled timing check needs an edge as its first argument
ID:23549 Verilog HDL error at <location>: timing check '$<string>' can only be used within specify blocks
ID:23550 Verilog HDL warning at <location>: '<string>' inside always_latch block does not represent latched logic
ID:23551 Initiator "<name>" has both its arvalid and awvalid ports disconnected. At least one must be connected.
ID:23553 The specified compact certificate type does not support the counter type <counter type>.
ID:23554 Compact certificate generated is non-cancellable.
ID:23558 The value "<value>" cannot be pasted to the column "<column name>" due to Invalid input value or format.
ID:23562 The top-level pin "<name>" is driving I/O input buffer "<name>" and other <number> fan-outs. The top-level pin is allowed to drive only one I/O input buffer.
ID:23565 A license for the Intrinsic ID PUF feature was not detected. Support for this feature is not enabled. Contact Intrinsic ID for an appropriate license.
ID:23566 The compact certificate file (.ccert) is corrupted or not supported for program operation on the target device at device index <device index>.
ID:23569 Support for programming the specified compact certificate is not enabled for the target device.
ID:23570 The start address of Page 0 must be greater than or equal to 0x20.
ID:23571 The TOP_LEVEL_ENTITY assignment in the current design does not match the base design (assignment in current design = "<current_design_assignment_status>", assignment in base design = "<base_design_assignment_status>").
ID:23573 Power analyzer will not report correct NoC power due to incomplete bandwidth assignments.
ID:23574 Wildcard pattern "<pattern>" for <atom_type> in <assignment_type> assignment does not match a valid atom hierarchy.
ID:23575 Failed to generate debug phase log definition map using the specified firmware header file <header filename>. The information in the header file is corrupted.
ID:23589 Using the get_clock_info command with the -nreg_pos or -nreg_neg options as an SDC command is subject to restrictions. If there are set_sense SDC commands that target the clock network of the requested clock, the -nreg_pos or -nreg_neg options are not supported in the get_clock_info SDC command.
ID:23591 Partition "<partition name>" requires more DSPs than are available <number of dsps still used>/<number of dsps available>, of which <number of user wys> are user WYSIWYG DSPs. Synthesis converted <number of soft wys coverted to logic> inferred DSPs to logic.
ID:23592 Logic lock region with ID "<logic lock region id>" requires more DSPs than are available <number of dsps still used>/<number of dsps available>.
ID:23598 Port <namename> is connected in the ALTDPRAM megafunction -- <name> block for device family <name> of the ALTDPRAM megafunction cannot use wraddrstall signal
ID:23599 Cannot implement altera_syncram megafunction because RAM size is too large to use with OPERATION_MODE parameter set to value <value>
ID:23600 Cannot use Memory Initialization File with M-RAM block in altera_syncram megafunction
ID:23601 Cannot use READ_DURING_WRITE_MODE_MIXED_PORTS parameter value set to OLD_DATA with M-RAM block in altera_syncram megafunction
ID:23602 Cannot use aclr input ports with M-RAM block in altera_syncram megafunction
ID:23603 Cannot use byte enable ports with M512 block in altera_syncram megafunction
ID:23604 <rden> port is connected in altera_syncram megafunction. <ram_block_type> block can now be driven by rden signal
ID:23605 In altera_syncram megafunction, clock0 port must always be connected
ID:23606 In altera_syncram megafunction, clocken1 port can only be used when clock1 port is used
ID:23607 In altera_syncram megafunction, clocken3 port can only be used when clock1 port is used
ID:23608 <par> parameter cannot be set to value <value> for <family> device family
ID:23609 Parameter error: parameter <name> of altera_syncram megafunction set to value <value> is illegal -- legal values for parameter <name> are <values>
ID:23610 Parameter error: parameter <name> of altera_syncram megafunction set to value <value> is illegal -- legal values for parameter <name> are <choices>
ID:23611 Parameter error: WIDTH_BYTEENA parameter of altera_syncram megafunction set to value <value> is illegal -- legal values for WIDTH_BYTEENA parameter must be <name>
ID:23612 Cannot use <name> port when parameter <name> is less than or equal to 1
ID:23613 Connected <name> port of the altera_syncram megafunction is unused with the current set of parameters
ID:23614 Must connect <name> port of altera_syncram megafunction when using current set of parameters
ID:23615 Cannot use OPERATION_MODE parameter value set to ROM with M-RAM block in altera_syncram megafunction
ID:23616 Cannot use different clear ports for <name> port and <name> port of altera_syncram megafunction when RAM is deeper than one RAM block
ID:23617 Cannot use different <clock or clear> ports for <name> port and <name> port in altera_syncram megafunction
ID:23618 Cannot use clear port with <name> port of altera_syncram megafunction and OPERATION_MODE parameter set to value <value>
ID:23619 Cannot use OPERATION_MODE set to value BIDIR_DUAL_PORT with <ram_block> block in altera_syncram megafunction
ID:23620 In altera_syncram megafunction, when OPERATION_MODE parameter is set to <value>, total number of bits (width x depth) between port A and port B must be the same
ID:23621 Cannot use rden_b port with M-RAM block in altera_syncram megafunction
ID:23622 Cannot use port A width with port B width in altera_syncram megafunction
ID:23623 Cannot use port A and port B width values with RAM_BLOCK_TYPE parameter value set to AUTO and current set of parameters in altera_syncram megafunction
ID:23624 Device family <name> does not have <name> blocks -- using available memory blocks
ID:23625 Cannot use <name> port with device family <name> in altera_syncram megafunction
ID:23626 Cannot use <name> port with RAM block type <name> in altera_syncram megafunction
ID:23627 Cannot use value <name> of parameter <name> with device family <name> in altera_syncram megafunction
ID:23628 Ignoring parameter <name> that uses input register with clear signal -- RAM block for device family <name> of altera_syncram megafunction cannot use input registers with clear signals
ID:23629 Cannot have disabled and enabled clock enables in <name> registers and on different sides of RAM block of altera_syncram megafunction -- if using the same clock, clock enables must be either disabled or enabled on both sides of RAM block
ID:23630 Cannot have different clock enable setting for Port A inputs, Port B inputs and Port B outputs, as they use the same clock
ID:23631 Not using extra address lines in altera_syncram megafunction design -- <number> memory words in side <name> specified but total number of address lines is <value>
ID:23632 Insufficient address lines in altera_syncram megafunction design -- <number> memory words in side <name> specified but total number of address lines is <value>
ID:23633 Logic cell implementation of Altsyncram megafunction is not supported for <mode> operation mode
ID:23634 Logic cell implementation of Altsyncram megafunction doesn't support initialization file
ID:23635 Device family <name> does not have <name> blocks
ID:23639 CYCLONEII_M4K_COMPATIBILITY variable is set to OFF, but CYCLONEII_SAFE_WRITE parameter is set to <cycii_safe_write>. The CYCLONEII_SAFE_WRITE parameter should be set to NO_CHANGE to be compatible with the CYCLONEII_M4K_COMPATIBILITY setting
ID:23640 In altera_syncram megafunction, ECC feature cannot be used for the specified combination of ports and parameters
ID:23641 In altera_syncram megafunction, the parameter <par> cannot be set to the value <name> for the RAM block <RAM_BLOCK>
ID:23642 In altera_syncram megafunction, output latch for port <port> cannot be asynchronously cleared for the specified device family <dev>, the clear will be ignored.
ID:23643 Ignoring <name> port -- <name> block for device family <name> of altera_syncram megafunction cannot use rden signal
ID:23644 In the altera_syncram Intel FPGA IP core, port <name> cannot be connected when parameter <name> is set to <name> for the target device family <name>
ID:23645 Cannot use READ_DURING_WRITE_MODE_PORT_A parameter value set to <name> for device family <family_name> in altera_syncram megafunction
ID:23646 <name> device family does not support the specified configuration. Altsyncram megafunction will support it by tying the byte-enable to the write enable of the relevant slices.
ID:23647 <parameter> parameter is not set, using the default value <parameter>. This value is not compatible when operation_mode is set to <parameter> for device family <device>
ID:23648 The ENABLE_RUNTIME_MOD LPM_HINT is no longer used to enable the In-System Memory Content Editor. Please refer to the RAM_1PORT and ROM_1PORT IPs to generate a memory suitable for use with ISMCE.
ID:23649 You have specified <odd_memory_word_size> odd size of memory words in Altera Syncram IP. Altera Syncram IP does not allow odd size memory words and auto corrected to <even_memory_word_size> memory words.
ID:23651 Timing Analyzer is running on the synthesized snapshot. By default, only clocks that are defined via SDC on RTL or Synthesis SDC files are available. For information about loading additional SDC files, review the documentation for read_sdc in the Scripting User Guide. Currently, IP support for Timing Analysis on the synthesized snapshot is limited, so IP generated clocks may not be present.
ID:23652 The specified firmware header file <name> is invalid or not exist.
ID:23655 There are <num_landmark_opt> M20K_CE_CONTROL_FOR_PR assignments on input ports of partition "<partition>".
ID:23656 To enable the level3 feature in FP16_SUMOF2MULT_ACC in the DSP block WYSIWYG primitive "<atom name>",disable the <register parameter name> register(s) and enable the <register parameter name>, <register parameter name>, <register parameter name> and <register parameter name> registers.
ID:23657 Anti-tamper feature and external voltage reference is enabled together.
ID:23660 Missing <bandwidth_type> for NoC connection from initiator "<initiator>" to target "<target>".
ID:23664 Successfully set the new setting <setting> to to <param> for node <node>.
ID:23665 Failed setting the value <setting> to <param> for node <node>.
ID:23666 Verilog HDL warning at <location>: Ignoring elaborated Verilog <string> '<string>.<string>' because it cannot be saved
ID:23667 Verilog HDL warning at <location>: Interface unit '<string>' cannot be elaborated by itself
ID:23668 Verilog HDL warning at <location>: automatic class object or member '<string>' cannot be written with non-blocking assignment
ID:23669 Verilog HDL warning at <location>: variable '<string>[<number>]' might have multiple concurrent drivers
ID:23670 Verilog HDL warning at <location>: found another <string> driver of '<string>[<number>]' here
ID:23671 Verilog HDL warning at <location>: variable '<string>[<number>]' is driven by invalid combination of procedural drivers
ID:23672 Verilog HDL warning at <location>: '<string>[<number>]' driven by this <string> block should not be driven by any other process
ID:23673 Verilog HDL info at <location>: Ignoring module '<string>'
ID:23674 Verilog HDL warning at <location>: a module/program/checker/interface cannot have more than one default clock
ID:23675 Verilog HDL error at <location>: illegal net type actual for formal '<string>' in '<string>' call
ID:23676 VHDL warning at <location>: Ignoring elaborated VHDL unit '<string>.<string>' because it cannot be saved'
ID:23677 Target device at device index <device index> does not support the specified compact certificate type for compact certificate file (.ccert) programming.
ID:23678 The output buffer '<name>' need to have same clock source for OE path and data path.
ID:23682 The following <type> IP instance(s) placed in tile <tile_name> do not use any hard IP or channel blocks
ID:23683 The following <type> IP instance(s) placed in tile <tile_name> has FGT reference clock(s) but no FGT channel(s)
ID:23684 The following <type> IP instance(s) placed in tile <tile_name> does not use the <ehip_type> block but another reconfiguration IP instances <name> use <feature> for the <ehip_type> block
ID:23685 The test mode option for the specified compact certificate type is not supported on the target device.
ID:23689 Assuming default frequencies of (INIU=<default_initiator_freq>MHz, TNIU=<default_target_freq>MHz). Performance may change in the final NOC performance report.
ID:23690 GDR REFCLK <text> has no path to fabric thus cannot be shared with core fabric logic <text>. To fix, remove REFCLK to fabric logic connection in the design.
ID:23691 Failed to expand command template for task: <task> assignment: <assignment>
ID:23692 In RAM Primitive "<hierarchy_path>", the source of <clock_port> is not clean. Use the PLL-generated clocks to ensure a clean and glitch-free clock source.
ID:23699 Incorrect HPS data or bootloader source provided. <source>.
ID:23700 <operation mode name> is not support <operation mode value> read-during-write for the LUTRAM block.
ID:23701 <operation mode name> is not support <operation mode value> read-during-write for the LUTRAM block.
ID:23702 The port "<bp_node>" on partition "<partition>" has the assignment M20K_CE_CONTROL_FOR_PR but has been promoted to a global signal.
ID:23704 <File Name> entity file is nested within another entity file. Recursive reading of SDC entity files is not supported.
ID:23706 Verilog HDL error at <location>: can't find port "<name>"
ID:23709 Verilog HDL error at <location>: cannot connect unsized constant <string> to a blackbox port
ID:23710 The target device does not support the specified compact certificate type. Use ccert_device option to specify the target device when generating the compact certificate file (.ccert).
ID:23711 Target device at device index <number> does not support secondary owner's public root key for partial reconfiguration and external authentication.
ID:23713 The design uses <num_in_design> <resource_type>(s) which exceeds the device capacity <device_capacity>.
ID:23714 Can not generate programming files for your current project because you do not have a valid license. Visit the Intel FPGA Self-Service Licensing Center at https://licensing.intel.com
ID:23715 Verilog HDL error at <location>: parameter <string> has no actual or default value
ID:23716 Verify voltage output format, direct format coefficient/linear format N and translated voltage value unit values are appropriate.
ID:23718 ECO: Cannot unplace node <node> since it is neither a LUT nor LAB FF.
ID:23719 Deleted original project file <name> and saved copy of original project file and settings files in backup directory "<name>"
ID:23721 Cannot place block <block_name> in location <location> because the location cannot drive to core fabric
ID:23722 The design uses <number> block(s) of type <block_type> that drives to core fabric, but only <number> block(s) exist in tile <tile_name> of type <tile_type> that may drive to core fabric
ID:23723 NoC atoms do not form connected groups which fit the NoC subsystems available on device.
ID:23724 <text>
ID:23725 Target device at device index <number> does not support wkey examine with the specified options. Uses --ccert option to specify a valid compact certificate to examine wkey.
ID:23728 Database format is incompatible with the current version of Intel Quartus Prime Software. Current version: '<current_version>' Disk version '<disk_version>'.
ID:23729 NoC group "<name>" must contain exactly 1 SSM and at most 1 PLL.
ID:23730 The following IP instances are placed in the same tile but are not part of the same placement profile
ID:23732 Failed to open input file "<filename>" for reading.
ID:23734 Failed to write in file "<filename>" check for required permissions and enough working space.
ID:23735 Invalid cancel ID value \'<value>\'.<text>
ID:23736 Use of PRESERVE assignment on instance "<hpath>" is ignored in DNI compilation mode.
ID:23737 Failed to open input file "<filename>" for reading.
ID:23738 Failed to write in file "<filename>" check for required permissions and enough working space.
ID:23739 The new setting <setting> to <param> for node <node> is successfuly set. However, check other generated critical warnings or errors.
ID:23740 The entered value <setting> for parameter <node> is not within the valid range.
ID:23741 The changes have failed validation and the design will fail Synthesis as a result. Do you want to save the changes?
ID:23742 <name>
ID:23743 BCM driver "<NAME>" from port mapping data conflicts with discovered BCM driver "<NAME>".
ID:23745 QDB database compiled in Intel Quartus Prime software version 23.2 or earlier cannot be used with Intel Quartus Prime software version 23.3 or later. Recompile your design in the latest version of the Intel Quartus Prime software.
ID:23748 Error is not injected at sector <name> : frame <name> at bit <name>- device busy.
ID:23750 <operation mode name> does not support <operation mode value> read-during-write for the LUTRAM block.
ID:23753 ECC encoder bypassing for RAM instance "<instance>" is not supported.
ID:23754 The read during write option "NEW_DATA_WITH_NBE_READ" set on port "<NAME>" of TDP RAM instance "<instance>" is not supported.
ID:23755 The ratio of the data widths on RAM instance "<instance>" is too high: "<NAME>". The maximum supported ratio is 16
ID:23756 The asynchronous output clear of port "<NAME>" on RAM instance "<instance>" requires an output register
ID:23757 The read during write option "NEW_DATA" of SDP RAM instance "<instance>" cannot be supported together with clock enable signals.
ID:23758 The NUM_PARALLEL_FLOW_WORKERS setting exceeded available CPUs. Adjusted value to: <available_cpus>
ID:23759 In RAM Primitive "<atom_name>", parameter <parameter_name> value <value> is no longer supported for the target device.
ID:23760 All IPs in an Exclusive Dynamic Reconfiguration group must be in the same PMA mode. Remove unsupported mode IPs from Dynamic Group to continue. IPs of different mode in Dynamic Reconfiguration group '<DrGroup>' are:
ID:23761 Driver "<NAME>" does not drive BCM input "<NAME>" according to the port mapping data.
ID:23762 Hierarchies were optimized away during sweep. For details, refer to " Hierarchies Optimized Away During Sweep " report.
ID:23764 RAM logic "<name>" is uninferred due to "logic" being set as ramstyle synthesis attribute
ID:23768 "<initiator>" must only remap predefined addresses <addresses>.
ID:23769 Can't create database directory for project in project directory "<name>"
ID:23771 Can't open project -- you do not have permission to write to all the files or create new files in the project's database directory
ID:23772 OK to convert the setting files for this revision to the new format? Converting the settings files does not affect the design files or other source files, and may take a few minutes depending on the number of assignments.
ID:23773 OK to overwrite the database created by <version number> and convert the setting files to the new format? The database format is incompatible with the current version of the Quartus Prime software. Converting the settings files may take a few minutes depending on the number of assignments. Overwriting the database does not affect the design files or other source files, but will remove all database files for the revision.
ID:23774 OK to overwrite the database created by <version number>? The database format is incompatible with the current version of the Quartus Prime software. Overwriting the database does not affect the design files or other source files, but will remove all database files for the revision.
ID:23775 OK to overwrite the database and convert the setting files to the new format? The database format is incompatible with the current version of the Quartus Prime software. Converting the settings files may take a few minutes depending on the number of assignments. Overwriting the database does not affect the design files or other source files, but will remove all database files for the revision.
ID:23776 OK to overwrite the database? The database format is incompatible with the current version of the Quartus Prime software. Overwriting the database does not affect the design files or other source files, but will remove all database files for the revision.
ID:23777 Can't remove incompatible database files from project
ID:23780 Detected same reference clock port '<REFClkName>' of System Clock IP '<ClkIPName>' driving reference clock of IPs '<PCIEIPName>' and '<NONPCIEIPName>' using PCIe and non-PCIe transceivers. Ensure separate reference clocks are driving reference clocks of PCIe and non-PCIe transceivers.
ID:23781 The application is running in '<mode>' mode.
ID:23782 Failed to find an expected report while writing reporting database.
ID:23783 Found SDC files for the synthesized snapshot.
ID:23784 Detected undriven port '<PLLPortName>' of system clock IP '<ClkIPName>'. Ensure that '<PortType>' port is driven by appropriate driver.
ID:23785 Failed to append device identity. Same device identity already exists in beta certificate <certificate name>.
ID:23786 The block <block_name> of type <block_type> uses parameter <parameter_name> that is not valid for tile type <tile_type>
ID:23789 Cannot delete file "<NAME>".
ID:23790 Discovered <NAME> WYSIWYG "<NAME>" of type "<NAME>".
ID:23791 "test_mode" option is valid only when "non_volatile" option is disabled.
ID:23793 Device type '<name>' is invalid.
ID:23794 Initiator "<initiator>" cannot be connected to target "<target>" because they are in separate internal groups. Their internal groups cannot be changed.
ID:23795 This message supports name based suppression
ID:23799 Intel Quartus Prime support for TDF files ends soon. Convert TDF files to Verilog or VHDL for continued support. One instance of TDF files is <file path>.
ID:23800 Derived clock name suffix defaults to '~derived'.
ID:23801 Can't open project "<name>" -- no Quartus Prime Settings Files exist for any revision listed in the Quartus Prime Project File
ID:23802 Project "<name>" does not exist
ID:23803 Can't close project while a process is in progress
ID:23804 NoC <assignment_type> assignment is created on the non-user <atom_type> node "<atom_hierarchy>".
ID:23808 The Quartus Prime Fitter expects up to 2 IOSSM with the same IO96B_ADJACENT_PAIR_ANCHOR but detected more than 2.
ID:23809 Problematic IO96B_ADJACENT_PAIR_ANCHOR: <ID>
ID:23810 Problematic IOSSM: <IOSSM>
ID:23813 <signal> drives periphery destinations on opposite sides of the device simultaneously. A skew balanced clock tree cannot be generated to align with opposing periphery interfaces that extend an odd number of sectors apart. Modify the design to use distinct clock trees to drive periphery destinations on opposite sides of the device
ID:23814 The specified puf type is not supported on the device.
ID:23815 Cannot view encrypted file "<name>"
ID:23816 Cannot open the parameter editor because a process is currently running.
ID:23817 Open the file from Files tab in the Project Navigator.
ID:23818 Cannot open file <name> -- file does not exist
ID:23819 Target slot id <number> is invalid. Choose a slot id between 0 and 7.
ID:23820 IP instance <instance_name> has an invalid Verilog hierarchical name, which may have been from an unnamed for generate block in module <module>.
ID:23821 IP file "<filename>" from Tcl file "<tcl_file>" was renamed to "<filename>" and will be added to Quartus settings file (.qsf)
ID:23827 Menu command for "<menu item name>" is not available
ID:23828 Menu command for "<menu item name>" is disabled
ID:23829 Initiator "<initiator>" and target "<target>" have overlapping security ranges: [0x<range1_start>, 0x<range1_end>] (size <range1_mask>) and [0x<range2_start>, 0x<range2_end>] (size <range2_mask>).
ID:23830 Initiator "<initiator>" and target "<target>" have at least one security range between them, but they are not connected.
ID:23832 Initiator "<initiator>" and target "<target>" have defined security range [0x<sec_range_end>, 0x<sec_range_start>] (size <mask>), and logical range [0x<logical_range_start>, 0x<logical_range_start>]. The security range is not fully contained within the logical address range.
ID:23834 Target "<target>" has <num_ranges> security ranges defined. The maximum number of ranges allowed per target is <ranges_max>.
ID:23836 Illegal value <text> for <name> parameter in WYSIWYG primitive "<name>" -- value must be <text>
ID:23837 WYSIWYG primitive "<name>" is missing value for <name> parameter. Legal values for <name> parameter are <values>.
ID:23838 When in its current operating mode, WYSIWYG RAM primitive "<name>" cannot have <name> parameter
ID:23839 Can't recognize value for <name> parameter for WYSIWYG RAM primitive "<name>"
ID:23840 WYSIWYG RAM primitive "<name>" must have <name> parameter
ID:23841 WYSIWYG RAM primitive "<name>" uses <name> port, which is inconsistent with <name> parameter value
ID:23842 Correcting WYSIWYG RAM primitive "<name>" <name> parameter value to 1 since using <name> port
ID:23844 WYSIWYG primitive "<name>" has inconsistent parameter values <name> and <name>
ID:23845 WYSIWYG RAM primitive "<name>" has too many bits
ID:23846 WYSIWYG RAM primitive "<name>" has the use of <name> port declared, but the port is unconnected
ID:23847 Block type <name> for WYSIWYG RAM primitive "<name>" is not supported in target device family
ID:23848 WYSIWYG RAM primitive "<name>" you have specified an illegal operation mode
ID:23849 When in its current operating mode, WYSIWYG RAM primitive "<name>" "<name>" is out of range
ID:23850 WYSIWYG RAM primitive "<name>" has inconsistent values for <name>, <name>, <name>, and <name> parameters
ID:23851 WYSIWYG RAM primitive "<name>" in operation mode "<name>" uses an unsupported value for parameter "<name>"
ID:23852 In current operating mode, WYSIWYG RAM primitive "<name>" cannot have <name> port or parameter connected
ID:23853 WYSIWYG RAM primitive "<name>" in operation mode "<name>" uses an unsupported value for parameter "<name>"
ID:23854 WYSIWYG primitive "<name>" must use clk0 port.
ID:23855 WYSIWYG RAM primitive "<name>" port "<name>" and "<name>" cannot connect at the same time
ID:23856 WYSIWYG RAM primitive "<name>" must have the "<name>" port connected when "<name>" port is connected
ID:23857 WYSIWYG RAM primitive "<name>" must have "<name>" or "<name>" parameter
ID:23858 WYSIWYG RAM primitive "<name>" "<name>" and "<name>" must set to ena0 when clock enable 0 is used
ID:23859 WYSIWYG primitive "<name>" must use clk1 port if ena1 port is used
ID:23860 WYSIWYG RAM primitive "<name>" must have the <name> port connected
ID:23861 WYSIWYG RAM Primitive "<name>" mixed port read during write cannot set "<name>" in this operation mode.
ID:23862 WYSIWYG RAM primitive "<name>" maximum width ratio for Port A data width A and Port B data width is 4!
ID:23863 WYSIWYG RAM primitive "<name>" port "<name>" in "<name>" is not allowed to be connected!
ID:23864 WYSIWYG RAM primitive "<name>" "<name>" Mix Port Width with "<name>" in "<name>" is not allowed
ID:23865 WYSIWYG RAM Primitive "<name>" the mixed-port read-during-write must use don't care when operation mode is set to "<name>" .
ID:23866 WYSIWYG RAM primitive "<name>" cannot use "<name>" in true dual port.
ID:23867 WYSIWYG RAM Primitive "<name>" maximum for "<name>" in "<name>" is 2!
ID:23868 WYSIWYG RAM Primitive "<name>" the mixed-port read-during-write must use don't care or new_a_old_b when operation mode is set to "<name>" .
ID:23869 WYSIWYG RAM Primitive "<name>" cannot use "<name>" in simple quad port port.
ID:23870 WYSIWYG RAM Primitive "<name>" enables the ECC feature, which only can be implemented in 512 (depth) by 32 (width) in simple dual-port mode.
ID:23871 WYSIWYG RAM Primitive "<name>" cannot use ECC and byte-mask features at the same time.
ID:23872 WYSIWYG RAM Primitive "<name>" has set the parameter ECC_PIPELINE_STAGE_ENABLED to TRUE, but does not use the output registers of the RAM primitive.
ID:23873 WYSIWYG RAM primitive "<name>" cannot have "<name>" port connected because parameter "<name>" is not set.
ID:23874 WYSIWYG primitive "<name>" cannot have value for <name> parameter unless <name> parameter is set to <text> value
ID:23875 WYSIWYG RAM primitive "<name>". Only the "<name>" operating mode is allowed. Ensure that port A and port B data widths are the same when using coherent read mode.
ID:23876 WYSIWYG primitive "<name>" parameter "<name>" cannot be set to true when using coherent read mode.
ID:23877 WYSIWYG RAM Primitive "<name>" mixed port read during write cannot set "<name>" when enable_coherent_read is true.
ID:23878 WYSIWYG RAM primitive "<name>" cannot use coherent read and byte-enable mask features at the same time.
ID:23879 When in its current operating mode, WYSIWYG RAM primitive "<name>" "<name>" is out of range
ID:23880 WYSIWYG RAM primitive "<name>" must have the "<name>" port and "<name>" port connected to the identical clock source with identical clock unateness.
ID:23881 WYSIWYG RAM primitive "<name>" cannot have parameter "<name>" set to "<name>" when using coherent read mode.
ID:23882 When in its current operating mode, WYSIWYG RAM primitive "<name>" port "<name>" and "<name>" need to be connected
ID:23883 WYSIWYG RAM primitive "<name>" must have width of "<name>" port set to 8.
ID:23884 WYSIWYG RAM primitive "<name>" must have "<name>" parameter and set to true when enable_ecc_encoder_bypass is set
ID:23885 WYSIWYG primitive "<name>" parameter "<name>" cannot set to false when port "<name>" is connected.
ID:23886 WYSIWYG RAM primitive "<name>" cannot have "<name>" port and "<name>" connected because parameter "<name>" is not set.
ID:23887 WYSIWYG ALM640 primitive "<name>" has too many address lines on <name> port
ID:23888 In WYSIWYG primitive "<name>", parameter <name> can only be set to <name> when parameter <name> is set to <name>
ID:23889 WYSIWYG RAM primitive "<name>" when using "<name>", "<name>" need to be used
ID:23890 WYSIWYG RAM primitive "<name>" has different clock signals feeding bits of <name> input bus port
ID:23891 WYSIWYG RAM primitive "<name>" has mismatched <names> parameters for <name> port and <name> port
ID:23892 WYSIWYG RAM primitive "<name>" ports "<name>" and "<name>" cannot be connected at the same time when using coherent read mode.
ID:23893 WYSIWYG RAM Primitive "<name>" uses ECC feature and the mixed-port read-during-write mode is set to old memory content. These two features cannot be used together.
ID:23894 WYSIWYG primitive "<name>" must use clk1 port if ena3 port is used
ID:23895 Can't find file "<path_checked>" required by the WYSIWYG "<wysiwyg_instance_name>" with the parameter "<parameter_value>" set to "<parameter_name>".
ID:23896 WYSIWYG "<wysiwyg_instance_name>" parameter "<parameter_name>" is empty, which is invalid.
ID:23897 Parameter <name> is not supported for WYSIWYG primitive "<name>"
ID:23898 WYSIWYG LCELL COMB primitive "<name>" has illegal format for LUT_MASK parameter value -- value must be 16-digit hexadecimal number or 64-digit binary number format
ID:23899 WYSIWYG LCELL COMB primitive "<name>" must use LUT_MASK parameter
ID:23900 RAM name is "<name>"
ID:23901 Memory Initialization File or Hexadecimal (Intel-Format) File for RAM is not specified but MEM_INIT parameter exists -- setting initial value from the content of mem_init parameter
ID:23902 Memory size (<number>) in design file differs from memory size (<number>) in MEM_INIT parameter -- setting initial value for remaining addresses to 0
ID:23903 Memory size (<number>) in design file differs from memory size (<number>) in MEM_INIT parameter -- truncated remaining initial content value to fit RAM
ID:23906 WYSIWYG primitive "<name>" has illegal value for <name> parameter
ID:23907 Can't read Memory Initialization File or Hexadecimal (Intel-Format) File <name> for ROM instance <name>. If the file exists, it is not in correct format.
ID:23908 Can't read Memory Initialization File or Hexadecimal (Intel-Format) File <name> -- setting all initial values to 0
ID:23909 Memory depth (<number>) in the design file differs from memory depth (<number>) in the Memory Initialization File "<name>" -- truncated remaining initial content value to fit RAM
ID:23910 Memory depth (<number>) in the design file differs from memory depth (<number>) in the Memory Initialization File "<name>" -- setting initial value for remaining addresses to 0
ID:23911 Can't find Memory Initialization File or Hexadecimal (Intel-Format) File <name> for ROM instance <name>
ID:23912 Can't find Memory Initialization File or Hexadecimal (Intel-Format) File <name> -- setting all initial values to 0
ID:23913 Memory Initialization File or Hexadecimal (Intel-Format) File "<name>" contains "don't care" values -- overwriting them with 0s
ID:23914 WYSIWYG LCELL COMB primitive "<name>" must use sharein port when in shared arithmetic mode
ID:23915 WYSIWYG LCELL COMB primitive "<name>" must use all LUT input ports when in extended LUT mode
ID:23916 WYSIWYG LCELL COMB primitive "<name>" has LUT_MASK parameter that is dependent on one or more unconnected input ports
ID:23917 WYSIWYG LCELL flipflop primitive "<name>" must use <name> port if it uses <name> port
ID:23918 WYSIWYG LCELL flipflop primitive "<name>" must use <name> port if it uses <name> port
ID:23919 WYSIWYG LCELL flipflop primitive "<name>" must use <name> port or <name> port if <name> port is used
ID:23920 WYSIWYG "<name>" primitive has illegal value <text> for <name> parameter -- used default value of <number>
ID:23921 WYSIWYG "<name>" primitive has illegal value <text> for <name> parameter -- used value <number> and ignored other values
ID:23923 Running register packing on synthesized netlist.
ID:23924 The read and write widths do not match. The width of "<width1>" has to match with "<width2>" for node "<name>".
ID:23925 Debug suggestion: <text>
ID:23926 Verilog HDL error at <location>: base class constructor specification is missing in derived class '<string>'
ID:23927 Verilog HDL error at <location>: base class '<string>' does not contain the matching constructor for the derived class '<string>'
ID:23928 Verilog HDL error at <location>: evaluation of built-in method 'search' is not supported
ID:23929 Verilog HDL warning at <location>: buit-in method 'search' violates IEEE 1800 syntax
ID:23930 Verilog HDL error at <location>: nettype '<string>' cannot be used in this context
ID:23931 Verilog HDL warning at <location>: illegal argument of type string in '<string>()', expected <string>
ID:23932 Verilog HDL warning at <location>: hierarchical reference is not allowed in net alias statement
ID:23933 Verilog HDL warning at <location>: default clock used outside its declaration scope
ID:23934 Verilog HDL error at <location>: illegal hierarchical reference to checker variable '<string>'
ID:23935 Verilog HDL error at <location>: unable to elaborate '<string>' on interface prefix '<string>'
ID:23936 Verilog HDL error at <location>: '<string>:value' assignment pattern is illegal for '<string>'
ID:23937 Verilog HDL error at <location>: assignment pattern for dynamic array or queue cannot be incomplete
ID:23938 Verilog HDL warning at <location>: assignment pattern cannot be incomplete for fixed sized array
ID:23939 Verilog HDL warning at <location>: non-static method '<string>' with static lifetime cannot be referenced using class scope resolution operator '::'
ID:23940 Verilog HDL error at <location>: argument '<number>' of '<string>' does not represent any scope or assertion
ID:23941 Verilog HDL error at <location>: illegal first argument '<string>' for '<string>'
ID:23942 Verilog HDL warning at <location>: first argument '<string>' to '<string>' expects an integral variable, an unpacked array of byte or string data types
ID:23943 Verilog HDL error at <location>: incorrect number of delays for continuous assignment
ID:23944 Verilog HDL warning at <location>: input port '<string>' cannot be initialized at declaration
ID:23945 Verilog HDL warning at <location>: range bound expression '<string>' overflows integer domain
ID:23946 Verilog HDL warning at <location>: real type expression in the with clause is not allowed for array reduction method '<string>'
ID:23947 Verilog HDL error at <location>: array reduction method '<string>' requires integral elements
ID:23948 Verilog HDL warning at <location>: production '<string>' expects a return statement with a proper value
ID:23949 Verilog HDL warning at <location>: illegal return statement for production '<string>'; expects no expression
ID:23950 Verilog HDL warning at <location>: return statement for production '<string>' expects a valid expression
ID:23951 Verilog HDL warning at <location>: invalid use of production '<string>'; not yet generated
ID:23952 Verilog HDL warning at <location>: production '<string>' is not allowed in code block of '<string>'
ID:23953 Verilog HDL warning at <location>: else block with null statement is not allowed in '<string>'
ID:23954 Verilog HDL warning at <location>: variable '<string>' being bit blasted has Ram init file as attribute. We may lose this initialization value
ID:23956 Examine operation is not supported for flash <name>. If multiple flashes are connected, only single flash can be examined at a time.
ID:23957 Invalid SEU error type injected at device <number>. Retry with 1 = single-bit error, 2 = double-bit error and 3 = uncorrectable error.
ID:23958 Error is not injected at sector <name> : CRAM SEL id <name> , CRAM SEL <name>- device busy.
ID:23961 Flash's size (<size> Mb) at chip select <flash> is mismatch with flash's size (<size> Mb) at chip select <flash>. For multiple flashes support, all the connected flashes must has same density.
ID:23962 Flash's device ID code (<id>) at chip select <flash> is mismatch with flash's device ID code (<id>) at chip select <flash>. For multiple flashes support, all the connected flashes must has same device ID code.
ID:23964 The entered <temperature type> temperature is not supported
ID:23966 Invalid Physical Unclonable Function type specified for the selected Black Key Provision operation.
ID:23967 Device <name> does not support for Safe SEU Injection.
ID:24006 The target device does not support the specified compact certificate type.
ID:24007 File <filename> could not be read
ID:24008 The selected partition size <partition_size> cannot be smaller than the selected flash minimum erase size <flash_min_erase_size>.
ID:24009 Block type <type> at <instance> is unknown
ID:24011 Node "<Node>" is being constrained to incompatible regions.
ID:24012 ROM name is "<name>"
ID:24013 Memory Initialization File or Hexadecimal (Intel-Format) File for ROM is not specified
ID:24014 SDC file '<filename>' from <asgn_name> assignment is not found.
ID:24015 SDC file '<filename>' has been modified during its processing for multiple instantiation of '<instance_name>' entity.
ID:24016 Invalid security range size in assignment "<assignment>" for initiator "<initiator>" and target "<target>". Valid sizes are "<valid_masks>"
ID:24017 A negative base address was assigned for initiator "<initiator>" and target "<target>".
ID:24018 Reading SDC file: <filename>
ID:24020 Port <port> on partial reconfiguration partition <partition> drives global destinations but was not a global signal in the base compile.
ID:24023 WYSIWYG primitive "<name>" uses ports that must be connected
ID:24024 Port <name> of WYSIWYG primitive "<name>" is not connected, but the port must be connected
ID:24025 WYSIWYG primitive "<name>" uses ports that require an INI, but the INI is not enabled
ID:24026 WYSIWYG primitive "<name>" uses the INI protected port <name>, but the port can only be used when the INI is enabled
ID:24027 The "<device family name>" device family is not supported.
ID:24028 Executable: <executable> not found or permission denied
ID:24030 Initiator "<initiator>" was given multiple assignments in <mask> range for target "<target>", starting at a base address of 0x<base_addr>.
ID:24031 Not all requested termination configurations can be fit in one RZQ group.
ID:24032 Bitstream is encrypted using Known Test Mode User AES Key.
ID:24033 Device <number> does not support for FULL SEU Injection.
ID:24034 Failed to find a BOS partition from flash. Ensure the flash device is formatted with a BOS partition.
ID:24035 The exported partition, "<partition>", has <num_ports> ports being driven by the same source, "<src>", outside it. Up to <max_ports> such ports are listed below. Multiple ports sharing a source external to the partition may lead to routing conflicts in compiles that reuse this partition in another context.
ID:24036 <port_name>.
ID:24039 When DSP block WYSIWYG primitive "<atom_name>" has selected operation mode "complex_mult", sub port must always set to 1'b1.
ID:24040 Programming file <name> is not a legal programming file -- specify a legal programming file
ID:24042 In "<name>", the port a data width value <port a data width value> is incompatible with port b data width value <port b data width value> for WYSIWYG RAM primitive "<name>". Change the data width for port a and port b to a supported combination or change the operating mode.
ID:24054 Auto RAM Replacement option turned off for RAM logic "<name>"
ID:24056 Weak pull-up and weak pull-down options are both set to 'ON' for pin <name>, but a pin may have only one of these options set to 'ON'
ID:24057 The <name> file does not exist.
ID:24059 "qspi_cs" option is not supported for multiple flash virtual devices.
ID:24060 "qspi_cs" option is not supported for multiple flash virtual devices.
ID:24063 <check_description> check is skipped and imported database might be incompatible with current Quartus version.
ID:24065 The <name> file does not exist. <text>
ID:24068 Verilog HDL error at <location>: target of assignment pattern cannot be a single bit type
ID:24069 Verilog HDL error at <location>: illegal use of delay expression without any value
ID:24070 Verilog HDL warning at <location>: non-net variable '<string>' cannot be connected to inout port of gate '<string>'
ID:24071 Verilog HDL warning at <location>: use of function call in disable soft constraint expression violates IEEE 1800 syntax
ID:24072 Verilog HDL warning at <location>: replication constant is negative, considering zero
ID:24073 The default value assigned for assignment (<variable type>) in QDF file is not supported. Follow 7-bit PMBus target device addressing and should be up to 2 digits hexadecimal only.
ID:24074 <message>
ID:24075 Cannot place combinational or register nodes in Logic Array Block (LAB)
ID:24076 PLL instance "<IOPLL name>" is configured with parameters that differ from the calculated optimal settings. As a result, jitter may be higher than expected. Recommended settings can be found below.
ID:24077 Current VCO frequency: <Atom VCO Freq> MHz. Recommended VCO frequency <Suggested VCO Freq> MHz.
ID:24078 Current M-counter setting: <Atom M-counter Setting>. Recommended M-counter setting: <Suggested M-counter Setting>.
ID:24079 Outclk <Output clock index> current C-counter setting: <Atom C-counter Setting>. Recommended C-counter setting: <Suggested C-counter Setting>.
ID:24082 Cannot set parameter <parameter_name> to the value <parameter_value> on the block <block_name>: <reason>
ID:24084 Assignment setting for <assignment name> (<assembler setting>) found in assembler does not match the setting found in fitter (<fitter setting>). Rerun fitter stage.
ID:24085 The following signal(s) have one or more clock routing constraints but are not guaranteed to be routed using the clock network
ID:24086 <signal> (<fanout> fanout)
ID:24087 The active revision settings file will be modified to remove errors. A backup is written to: <string>.
ID:24088 Password for the INI option "<name>" does not match for enabling virtual fusing.
ID:24089 <File Name> file was modified after Elaboration. Your change will not be reflected. Re-run Synthesis to load the new file.
ID:24090 Pre-emphasis option is set to <number> for pin <name>, but setting is not supported by I/O standard <name>. Valid pre-emphasis value are from <number> to <number>
ID:24091 VOD option is set to <number> for pin <name>, but setting is not supported by I/O standard <name>. Valid VOD value are from <number> to <number>
ID:24092 You are using an EMIF IP that has been generated using a different device. Regenerate your IP using the current device.
ID:24095 Timing requirements were met
ID:24096 Flash's minimum erase size (<min_erase_size> KB) at chip select <flash> is mismatched with flash's minimum erase size (<id> KB) at chip select <min_erase_size>. For multiple flashes support, all the connected flashes must has same supported minimum erase size.
ID:24099 Device <device position> with device string <device string> is expected to represent multiple devices that sharing same JTAG ID. However, only single device is found in device database. To resolve the issue, ensure the JTAG server version is matching with the Programmer version.
ID:24101 Tennm HBMC atom operation mode "<name>" is not supported
ID:24102 Minimum erase size that used in programming file (<min_partition_size> KB) is not supported by the flash (<min_erase_size> KB). The minimum erase size from the programming file must equal or multiplies of flash supported minimum erase size.
ID:24103 Performing metastability analysis with a non-routed snapshot. Treat any reported MTBF values as an estimate.
ID:24104 IOPLL VCO frequency and LVDS data rate are mismatched for IOPLL IP instance <name>.
ID:24105 Missing parasitic data for the pin (<Pin name>) in the custom package.
ID:24106 Failed to parse security range setting "<setting>" between initiator "<initiator>" and target "<target>".
ID:24109 Could not locate the negative I/O output buffer "<name>" at the differential I/O pin "<name>".
ID:24114 Project path "<path>" exceeds the Windows 260-character maximum path length limit. The Intel Quartus Prime software may not work properly when the project directory is on a long path. Consider moving the project directory to a shorter path.
ID:24116 I/O standard option is set to <name> for pin <name> but the <name> usage mode does not support the setting.
ID:24117 Device <name> does not support EDCRC fault injection.
ID:24118 Verilog HDL error at <location>: illegal expression for clockvar '<string>'; expected a lvalue
ID:24119 VHDL warning at <location>: ignoring unknown actual generic literal value <string> for generic '<string>'
ID:24120 User signal <text> is driving to <text> port on a periphery atom: <text> (<text>), and <text> port on a core atom: <text> (<text>). This user signal when used as dedicated I_PIN_PERST_N purpose for PCIE HIP must not be used as a general-purpose I/O (GPIO) to drive to core. The logic in the core must be driven by a different top level signal / GPIO.
ID:24122 The Hyper-Retimer was skipped due to Fitter settings.
ID:24123 Export failed. Can't export PDF file <file_name>: <error_message>. Verify that the file is closed and that you can write to the specified file and location.
ID:24124 Can't display node -- node cannot be found in schematic.
ID:24125 Can't display node -- node is encrypted. Displaying non-encrypted portions of schematic.
ID:24127 Failed to execute command: <command_name>
ID:24128 Filtering across ten or more logic levels increases processing time. Do you want to continue?
ID:24129 The following signal(s) drive clock ports in Partial Reconfiguation partition(s) but are not promoted to use the clock network. These signals cannot be used to clock M20K blocks inside the Partial Reconfiguation partition(s)
ID:24130 <signal> (driving partition <PR_partition>)
ID:24131 Failed to execute command: <command_name>
ID:24132 ECO: Target <name> is a Virtual Pin.
ID:24133 Invalid connection from initiator "<initiator>" to target "<target>" due to mismatched interface types: <interface_type_1> and <interface_type_2>. You cannot connect non-HPS variants with HPS variants.
ID:24134 RAM logic "<name>" is uninferred due to asynchronous write logic
ID:24136 RAM logic "<name>" is uninferred due to asynchronous read logic
ID:24137 The Intel Quartus Prime software has failed to create a thread.
ID:24138 <msg>
ID:24139 The device family does not support the UNUSED_IO_BANK_VOLTAGE assignment. This assignment will not take effect.
ID:24140 File <filename> could not be written to
ID:24141 RAM is inferred from mux "<name>"
ID:24146 <name>Error #<number> at sector <name> : <name> <name> in RAM ID <name>
ID:24147 The entered parameter name <param> is incorrect.
ID:24148 The log files "<log file name>.(rec|log)" are used by another instance of <app name>. "<new log file name>.(rec|log)" will be used as the log files for current instance.
ID:24149 Cannot create the log files "<log file name>.(rec|log)" for <app name>. Lack of permissions in the directory "<directory name>".
ID:24150 Failed to inject error at sector <name> : RAM ID <name> - <name>.
ID:24151 The entered parameter <param> is not modifiable by user.
ID:24155 The Quartus Partition Database File '<qdb_file>' was generated using version '<db_version>', which cannot be read by the current version of the Quartus Prime software. Regenerate '<qdb_file>' using the current version of the Quartus Prime Software.
ID:24156 Detected timing-critical high-fanout signal "<signal_name>" while placing the design.
ID:24164 VHDL warning at <location>: target entity '<string>' contains no architecture; bind is ignored
ID:24165 VHDL error at <location>: subtype of return identifier '<string>' is unconstrained in this context
ID:24166 VHDL warning at <location>: ignoring black box marking in configuration '<string>'
ID:24167 VHDL warning at <location>: actual of size <number> will overflow return type '<string>' in feedthrough function '<string>'
ID:24168 VHDL error at <location>: unexpected non-printable character with the hex value '0x<number>'
ID:24169 VHDL error at <location>: empty record declaration is only supported in VHDL 1076-2019
ID:24170 VHDL error at <location>: semicolon after last interface declaration is only supported in VHDL 1076-2019
ID:24171 VHDL error at <location>: keyword 'component' after 'end' is optional only in VHDL 1076-2019
ID:24172 VHDL warning at <location>: <string> unit '<string>' is previously defined; ignoring this definition
ID:24173 VHDL warning at <location>: RTL 'process(<string>) if(<string>)' behaves like a flop; inferring latch may cause simulation difference
ID:24174 VHDL error at <location>: variable '<string>' can only be of mode 'inout'
ID:24175 VHDL error at <location>: formal variable '<string>' should be of a protected type or composite type with a subelement of protected type
ID:24176 VHDL warning at <location>: directive <string> expects no argument
ID:24177 VHDL error at <location>: expanded name prefix '<string>' is allowed only within the construct itself
ID:24178 VHDL info at <location>: component generic's type '<string>' is declared here
ID:24179 VHDL info at <location>: entity generic's type '<string>' is declared here
ID:24180 VHDL info at <location>: component ports's type '<string>' is declared here
ID:24181 VHDL info at <location>: entity port's type '<string>' is declared here
ID:24182 VHDL warning at <location>: external name through instance not fully supported in single pass elaboration
ID:24183 VHDL error at <location>: designated type of an incomplete access type should be incomplete type
ID:24184 VHDL error at <location>: designated type of an incomplete file type should be incomplete type
ID:24185 VHDL error at <location>: '<string>' cannot be associated with unspecified '<string>' type
ID:24186 Cannot set OPERATION_MODE to <operation_mode> with <ram_block_type> block in altera_syncram megafunction
ID:24187 Can't display encrypted object(s): <encrypted_obj>
ID:24188 The file name "dni" is reserved for use by the Intel Quartus Prime software, and cannot be used.
ID:24190 User has specified a QSF location assignment to drive <text> using <text>. The <text> is on HVIO bank and is not optimal for HSSI PLL refclk usage. Try to use the HSSI native local/global refclk IO instead.
ID:24193 Cannot connect "<name>" port and "<name>" port at the same time in altera_syncram IP.
ID:24197 Cannot merge RX simplex instance '<instance_name>' with TX simplex instance '<instance_name>' because parameter '<parameter_name>' has mismatching values (<parameter_value> != <parameter_value>)
ID:24198 Cannot merge two RX simplex or two TX simplex IPs ('<instance_name>' and '<instance_name>') into the channel at relative offset <number>
ID:24199 IP '<name>' failed elaboration
ID:24200 The -add_launch_clock option can only be used when the -override option is also used.
ID:24201 The Dual Simplex Tool does not support family '<family>'. Supported family (families) are: <family_list>
ID:24202 The Dual Simplex Tool must be run on an open Quartus project.
ID:24203 <assignment_type> logic assignment value '<family_list>' must be an unsigned integer.
ID:24204 <assignment_type> logic assignment ignored - missing <assignment_type> logic assignment to DS group '<ds_group_name>'.
ID:24205 <assignment_type> logic assignment ignored - missing <assignment_type> logic assignment specifying IP instance '<instance_name>' in DS group '<ds_group_name>'.
ID:24206 DS Tool failed to create DS Group '<ds_group_name>'. Errors: <number>
ID:24207 DS Tool successfully created DS Group '<ds_group_name>'
ID:24209 <text>
ID:24222 Unable to access status db: <access_error>
ID:24225 Partition '<preserved_partition>' has the preservation level set to '<preserve_level>', which does not exist. Partition '<preserved_partition>' will be compiled from 'none'.
ID:24232 The -value_multiplier option must be a non-zero floating point number.
ID:24233 The -value_multiplier option can only be used when the -get_value_from_clock_period option is also used.
ID:24239 Project contains the QSF instance assignment "set_instance_assignment HSSI_PARAMETER "<text>=<text>" -to <text>". This assignment targeted for setting analog parameter on Transceiver pins (<text>) is invalid since <text> value <text> does not exist. Refer to the Agilex 5 transceiver User Guide for valid parameters and assignments.
ID:24240 Cannot open the <name> report database file.
ID:24241 Writing examined data from device <device> at device index <number> to file <filename>
ID:24242 The compile step: <compile step> is out of date because the file: "<filename>" has changed.
ID:24261 File I/O error has occurred. Unable to write to file "<issp_filename>".
ID:24265 Quartus detected the interface <text> is not connected. Ensure it is either connected or exported to top level pins.
ID:24273 Intel Quartus Prime software detected that the pin placement in bank <I/O bank location> has violated the placement rule. Reassign pin location assignment according to the following user guides to comply with the restrictions.
ID:24288 Default part selection is not supported for family <family_name>, you must select a specific part
ID:24289 For MIPI design, review "MIPI D-PHY Placement Rules" as outlined in the Intel Agilex 5 FPGA MIPI D-PHY IP User Guide.
ID:24290 For LVDS SERDES design, review "Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank" as outlined in the Intel Agilex 5 General-Purpose I/O User Guide.
ID:24291 For LVDS SERDES design, review "Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank" as outlined in the Intel Agilex 7 General-Purpose I/O User Guide:M-Series.
ID:24297 Cannot use 200G Hard IP location <location> and FGT channel location <location> as 200G Hard IP is currently not supported with this OPN. If you need 200G Hard IP, please reach out to Intel Field Representative.
ID:24307 The design instantiated <number> reset sequencers. This exceeds the device capacity <number>
ID:24308 User has specified location assignments for data/refclk ports, which are mutually conflict when propagated to reset sequencer <text>.
ID:24312 Intel Quartus Prime software detected that the pin placement in bank <I/O bank location> has violated the Byte I/O Standard rule. Reassign pin location assignment according to the following user guides to comply with the restrictions.
ID:24313 For MIPI design, review "Using the Remaining I/O Pin from Same Byte Location" as outlined in the Intel Agilex 5 FPGA MIPI D-PHY IP User Guide.
ID:24314 The reset sequencer <text> wants to use <number> quads while there are only <number> usable.
ID:24315 User specified location assignments for data/refclk ports are propagated to reset sequencer <text>. These assignments are not satisfiable.
ID:24317 The wrong Reset Release IP was detected in this project, use <expected ip name> not <actual ip name>. For more information about the Reset Release IP, refer to the Configuration User Guide.
ID:25000 Can't locate to Chip Planner
ID:26000 Can't find text "<text>"
ID:26001 Unable to save the Logic Lock region assignments to storage -- see messages in the System tab of the Messages window for details
ID:26002 Unable to create a new Logic Lock region -- see messages in the System tab of the Messages window for details
ID:26003 Unable to rename the Logic Lock region from "<name>" to "<new_name>" -- see messages in the System tab of the Messages window for details
ID:26004 Unable to delete the Logic Lock region named "<name>" -- see messages in the System tab of the Messages window for details
ID:26005 Unable to move the Logic Lock region named "<name>" -- see messages in the System tab of the Messages window for details
ID:26006 Unable to resize the Logic Lock region named "<name>" -- see messages in the System tab of the Messages window for details
ID:26007 Unable to perform the requested Logic Lock operation -- see messages in the System tab of the Messages window for details
ID:26009 Multiple regions are selected. Only one region can be <text> at a time.
ID:26010 Are you sure that you want to delete the selected Logic Lock region "<name>" and its descendants? You will not be able to undo the operation.
ID:26011 Can't merge the selected Logic Lock regions
ID:27000 No results for query "<name>"
ID:27001 You are about to move <number> nodes. Are you sure that you want to continue?
ID:27002 Cannot drag and drop the selected elements
ID:28000 Run Analysis and Synthesis before quartus_adb
ID:28001 Cannot run quartus_adb -- Analysis and Synthesis failed
ID:28002 Project name is required
ID:28003 Illegal project name "<name>"
ID:28004 Check and Save All Netlist Changes is currently unavailable because a compilation process is active
ID:28005 "<mask>" is not a valid <num_inputs> input LUT mask
ID:28006 Cannot change sum_to_lutc value from QFBK mode on atom "<name>"
ID:28007 Atom "<name>" does not support input port changes
ID:28008 Cannot make changes to the negative differential pin "<name>"
ID:28009 Cannot set input port <name> on atom "<name>" to <name>
ID:28010 Cannot make connection from "<name>:<name>", the output port is either not supported or in a non-supported configuration
ID:28011 Cannot make the connection because the atom already has another input port with the same source
ID:28012 Cannot disconnect signal "<name>" from input port <name> on atom "<name>"
ID:28013 Atom "<name>" does not implement port type <name>
ID:28014 Atom "<name>" does not use port usage type <name>
ID:28015 Cannot remove last usage for <name>'s port type <name>
ID:28016 LUT mask in "<name>" depends on port type <name>
ID:28017 Attempting to add output clock to pin "<name>" without data signal or output enable
ID:28018 Attempting to add a registered output to atom "<name>" but it doesn't have a clock signal
ID:28019 Attempting to add a DDIO registered output to atom "<name>" but it already has a combinational output
ID:28020 Attempting to add carry out port to atom "<name>" but DATAD is already connected
ID:28021 Atom "<name>" already uses port type <name>
ID:28022 Can't modify PLL atom "<name>"
ID:28023 Cannot set PLL parameter <name> to <value> on atom "<name>"
ID:28024 Encountered an unknown parameter type
ID:28025 Design is currently read-only. Run quartus_fit to allow ECO changes.
ID:28026 Engineering Change Order (ECO) is not supported for this device family
ID:28027 Requested modification is not supported for this device family
ID:28028 Atom "<name>" does not support modification
ID:28029 Atom "<name>" is from an encrypted source file
ID:28030 Atom "<name>" does not have DATA_TO_LUTC mux
ID:28031 Cannot change to I/O standard <name> on pin "<name>"
ID:28032 Cannot change set I/O standard <name> at <name> on pin "<name>"
ID:28033 Cannot make change to atom "<name>" because an <name> register is required
ID:28034 Cannot make change to atom "<name>" because an <name> path is required
ID:28035 Invalid destination for atom "<name>"
ID:28036 Unplacing atom "<name>"
ID:28037 The new delay chain setting "<new_setting>" is not the same as the previous setting "<old_setting>"
ID:28038 Cannot change setting on dedicated clock atom "<name>"
ID:28039 Cannot change setting. One or more destinations of atom "<name>" does not support pad-to-core delay chain paths.
ID:28040 Cannot change setting. The current location of atom "<name>" does not support pad-to-core delay chains.
ID:28041 No programmable invert on <name> port on atom "<name>"
ID:28042 Cannot invert constant signal into <name> port on atom "<name>"
ID:28043 Atom "<name>" does not support Open Drain
ID:28044 LCELL <name> has no output port dependent on the LUT Mask
ID:28045 Atom "<name>" is still connected
ID:28046 <type> output term with literal index <number> on atom "<name>" is still connected
ID:28047 Atom "<name>" still has DDIO DATA connected
ID:28048 Atom "<name>" still has DDIO REGOUT connected
ID:28049 Atom "<name>" does not have a <port> connection
ID:28050 Logic cell <name> is in Arithmetic mode and does not support equations dependent on Data D
ID:28051 Logic cell <name> is in Arithmetic mode and does not support Carry Equations dependent on Data D
ID:28052 I/O "<name>" is in Input or Bidirectional mode and requires either a COMBOUT or REGOUT output term
ID:28053 Cannot change property <property> on unplaced atom "<name>"
ID:28054 Cannot create duplicate atom name "<name>"
ID:28055 Cannot remove last fan-out from output term "<name>"
ID:28056 The last fan-out from output term "<name>" is removed. This output term does not pass Netlist Check and Save until it has at least one fan-out.
ID:28057 A fan-out is required for output term "<name>"
ID:28058 Output term "<name>" should have no fan-out
ID:28060 Atom "<name>" is not using port usage type <name>
ID:28061 Atom "<name>" has Extend OE Disable set but does not use an OE Register
ID:28062 Cannot create output port <port> on atom "<name>"
ID:28063 Cannot create atom with name "<name>"
ID:28064 Cannot change <port> input term source on atom "<atom>" to <source>
ID:28065 Cannot create <port> <input/output> term on atom "<atom>"
ID:28066 Cannot change <port> input term on atom "<atom>"
ID:28068 Cannot change <port> input term source on atom "<atom>"
ID:28069 Can't place atom <name>
ID:28070 Can't place atom <name> because the destination is not empty
ID:28071 Atom <atom> requires a data signal
ID:28072 Cannot set Current Strength <setting> on atom <atom>.
ID:28073 Cannot set on-chip termination setting <setting> on atom <atom>
ID:28074 Cannot remove last output term on <name>
ID:28075 Cannot set LUT mask to a constant on <name>
ID:28076 LUT mask on <name> does not depend on connected input to port <name>
ID:28077 LUT mask on <name> depends on unconnected input to port <port>
ID:28078 Cannot retrieve LUT mask on <name>
ID:28079 Cannot edit router inserted buffer <name>
ID:28080 Cannot connect signal to port <port> on <name>
ID:28082 Cannot move node while the carry chain is still connected
ID:28083 <change_type> operation <change_type_word2> <number> dependent operations
ID:28084 Command <number>: <cmd_text> was <change_type>
ID:28085 Failed <type> at command <num>.
ID:28086 Encountered an unknown error while attempting to execute the ECO command. <extra_info>
ID:28087 Change record <cmd_number> cannot be deleted because it is currently applied or saved to disk
ID:28088 Converted <number> Signal Probe assignments into Signal Probe ECOs
ID:28089 Cannot make connection because output term <oterm name> does not exist
ID:28090 Cannot import location change on node <node name>
ID:28091 Cannot modify global level on input port <chain type> on node <node name>
ID:28092 Cannot import carry chain connection on node <node name>
ID:28093 Cannot modify DQS-related delay chains on <node name>
ID:28094 Cannot remove the pin <node name> because it was reserved before compile
ID:28095 Cannot create a Signal Probe named <node name> because there is already a node in the design with that name
ID:28096 Cannot remove DQ I/O node <node name>
ID:28097 Cannot modify connection to DQS-related node <node name>
ID:28098 Cannot modify connection to Clock Delay Control Calibration block or related node <node name>
ID:28099 Cannot modify connection to port <port type> on node <node name>
ID:28100 There are an unbalanced number of calls to set_batch_mode. There were <call count> more calls turning batch mode on, then off.
ID:28101 Improperly connected <input port> input port on <node name>
ID:28102 Input port <name> of register node <name> has a different signal source than the <name> port of register node <name>
ID:28103 The node <node name> cannot be deleted because it is of a type that is not supported for ECO deletion.
ID:28104 The node <node name> cannot be added to the partition <part name>
ID:28105 Atom "<name>" has incorrect datac usage
ID:28106 Atom "<name>" has both <port> and <port> connected
ID:28107 Atom "<name>" requires VCC connected to <port>
ID:28108 Cannot set power mode on tile at location (<X>, <Y>) to "<setting>"
ID:28109 Cannot create <port> <input/output> term on atom "<atom>"
ID:28110 Cannot create port <name> <text> term with literal index <number> on atom "<name>"
ID:28111 Cannot set parameter <name> to <value> on atom "<name>"
ID:28112 Atom "<name>" requires registered <name> signals to have <name> and <name> input signal indices
ID:28113 Exported database does not have a valid Change Manager version
ID:28114 Can't change "<name>" property on "<name>" to <name>
ID:28115 Removed backup netlists from disk - the current netlist state may be unanticipated
ID:28116 Can't set PLL parameter <name> to <value> on atom "<name>". The value needs to be greater than zero.
ID:28117 Can't remove the <port> oterm port on <name>
ID:28118 Cannot connect input chain on atom "<name>"
ID:29000 Check Resource Properties was successful
ID:29001 Check Resource Properties failed. View the message in the System tab of the Messages window for details.
ID:29002 Can't edit connection because signal <name> does not exist
ID:29003 Can't apply all property changes. View the message in the System tab of the Messages window for details.
ID:31000 Timing data is not available because the project was not compiled using the Timing Analyzer as the default timing analyzer
ID:31001 Timing data is not available because the project was not compiled using the Timing Analyzer as the default timing analyzer
ID:31002 Timing data cannot be shown because no post-fit netlist exists
ID:31003 Failure creating a Logic Lock region. See message window for more details
ID:31004 Failure removing a Logic Lock region. See message window for more details
ID:31005 Failure creating partition. See message window for more details
ID:31006 Failure removing partition. See message window for more details
ID:31007 Run Analysis and Synthesis and Partition Merge before opening the Design Partition Planner
ID:31008 Design Partition Planner's display is based on the post-synthesis netlist
ID:31009 Design Partition Planner's display is based on the post-fit netlist
ID:31010 Retrieving timing data may take a few minutes. Do you want to continue?
ID:31011 Run Partition Merge before opening the design in the Design Partition Planner
ID:31012 Design contains Partitions but incremental compilation is now turned off. Rerun Analysis and Synthesis before opening the Design Partition Planner
ID:31013 Assigned device is not supported by the Design Partition Planner
ID:31014 Last compiled device is not supported by the Design Partition Planner
ID:31015 No failing paths were found in the design
ID:31016 Quartus Prime Auto-Partitioner is configured with the following parameters:
ID:31017 Top-level entity for partitioning: <text>
ID:31018 Quartus Prime Auto-Partitioner is retrieving timing data from the Timing Analyzer
ID:31019 Quartus Prime Auto-partitioner is loading timing data. This operation may take a few minutes.
ID:31020 Maximum number of partitions: <number>
ID:31021 Target percentage of netlist to partition: <number>
ID:31022 Random mode: ON
ID:31023 Timing-driven mode: ON
ID:31024 Logic range (LEs/Comb ALUTs + Registers): <text>
ID:31025 DSP block range: <text>
ID:31026 Memory bit range: <text>
ID:31027 Quartus Prime Auto-Partitioner's operation is starting
ID:31028 Auto-Partitioning decisions are based on the Post-Synthesis netlist. For best results, invoke Auto-Partitioner using a Post-Fit netlist.
ID:31029 Auto-Partitioning decisions are based on the Post-Fit netlist
ID:31030 Quartus Prime Auto-Partitioner has successfully completed. <number> new partitions are created.
ID:31031 Quartus Prime Auto-Partitioner has successfully completed. One new partition is created.
ID:31032 Quartus Prime Auto-Partitioner has successfully completed. No new partitions are created because no suitable candidates are found.
ID:31033 Quartus Prime Auto-Partitioner has successfully completed. No new partitions are created because no suitable candidates are found.
ID:31034 Quartus Prime Auto-Partitioner has successfully completed. No new partitions are created because all the candidates are too small for automatic partitioning.
ID:31035 Quartus Prime Auto-Partitioner has successfully completed. No new partitions are created because all the candidates are too small for automatic partitioning.
ID:31036 Created "<text>"
ID:31037 Quartus Prime Auto-Partitioner has successfully completed. <number> new partitions are created.
ID:31038 Quartus Prime Auto-Partitioner has successfully completed. One new partition is created.
ID:31039 Quartus Prime Auto-Partitioner is initializing
ID:32001 Open the Timing Analyzer before attempting to retrieve timing data
ID:33001 Open the Timing Analyzer before attempting to retrieve timing data
ID:37000 Can't generate ATMX file for the project because the encrypted source file cannot be located or attempt to overwrite the source file exists in the Export Database target directory: "<name>"
ID:37001 Line <number> in Atom Netlist File <name> contains syntax error "<text>"
ID:37002 Can't write to Atom Netlist File <name>
ID:37003 Can't generate Atom Netlist File for device family <name>
ID:37004 Line <number> in Atom Netlist File <name> contains illegal atom type "<type>"
ID:37005 Line <number> in Atom Netlist File <name> contains illegal attribute name "<name>"
ID:37006 Line <number> in Atom Netlist File <name> contains property <name> with illegal attribute value "<value>"
ID:37007 Line <number> in Atom Netlist File <name> contains illegal input port "<name>"
ID:37008 Line <number> in Atom Netlist File <name> contains atom "<name>" with illegal input port "<name>"
ID:37009 Line <number> in Atom Netlist File <name> contains atom "<name>" with illegal output port "<name>"
ID:37010 Line <number> in Atom Netlist File <name> contains illegal output port "<name>"
ID:37011 Line <number> in Atom Netlist File <name> contains illegal input port index "<name>"
ID:37012 Line <number> in Atom Netlist File <name> contains illegal output port index "<name>"
ID:37013 Line <number> in Atom Netlist File <name> contains illegal connection from "<name>" to <name>
ID:37014 Line <number> in Atom Netlist File <name> contains illegal name ID <name>
ID:37015 Line <number> in Atom Netlist File <name> contains duplicate name ID <name>
ID:37017 Can't analyze file -- file <name> is missing
ID:37018 Can't analyze include file -- file <name> is missing on line <number> in Atom Netlist File <name>
ID:37019 Can't open include file <name> on line <number> in Atom Netlist File <name>
ID:37020 Node "<name>" of <name>[<index>] property uses illegal input port "<type>"
ID:37021 Node "<name>" of <name> [<index>] property uses illegal output port "<type>"
ID:37022 Can't generate Atom Netlist File because device family version has changed
ID:37023 Can't generate Atom Netlist File because device version has changed
ID:37026 The intended use of the database file is incompatible with Backwards Compatibility or Incremental Design.
ID:37027 Cannot generate Atom Netlist File because device <name> is not installed
ID:37028 Cannot generate Atom Netlist File because family <name> is not installed
ID:37029 Line <number> in Atom Netlist File <name> contains illegal port "<name>"
ID:39001 Run Analysis and Synthesis (quartus_map) with revision "<name>" before running Partition Merge (quartus_cdb --merge)
ID:39002 Run Partition Merge (quartus_cdb --merge) with revision "<name>" before running Compiler Database Interface (quartus_cdb)
ID:39003 Run Analysis and Synthesis (quartus_map) with revision "<name>" for --rev option before running Compiler Database Interface (quartus_cdb)
ID:39004 Project name "<name>" specified for Compiler Database Interface (quartus_cdb) contains invalid characters
ID:39005 Specify a project for Compiler Database Interface (quartus_cdb)
ID:39006 Revision "<name>" specified for Compiler Database Interface (quartus_cdb) --rev option contains invalid characters
ID:39007 Generated Verilog Quartus Mapping File <name>
ID:39008 Verilog Quartus Mapping File name "<name>" specified for Compiler Database Interface (quartus_cdb) --vqm option contains invalid characters
ID:39009 Run Analysis and Synthesis (quartus_map) with device family <name> specified for --family option before running Compiler Database Interface (quartus_cdb)
ID:39010 Device name <name> specified for Analysis and Synthesis (quartus_map) --part option is invalid
ID:39011 Demotion type <name> specified for Compiler Database Interface (quartus_cdb) --back_annotate option is illegal. Refer to --help for legal demotion types.
ID:39012 Can't generate Routing Constraints File -- Compiler Database Interface (quartus_cdb) --back_annotate=routing option is not supported for <name> device family. To use --back_annotate=routing option, specify a supported target device family.
ID:39013 Can't run Compiler Database Interface with the --<name> option when the project setting files are read-only
ID:39014 Generated Routing Constraints File <name>
ID:39015 Can't generate Routing Constraints File <name>. Run Fitter (quartus_fit) before running Compiler Database Interface (quartus_cdb) with --back_annotate=routing option, and make sure Compiler settings are compatible with current version of the Quartus Prime software.
ID:39016 Run Fitter (quartus_fit) before running Compiler Database Interface (quartus_cdb) with --back_annotate option
ID:39017 Can't generate Routing Constraints File by running Compiler Database Interface (quartus_cdb) with the --write_rcf_for_vqm option -- make sure Compiler settings are compatible with current version of the Quartus Prime software
ID:39018 Run Fitter (quartus_fit) before running Compiler Database Interface (quartus_cdb) with --back_annotate option
ID:39019 Run Fitter (quartus_fit) before running Compiler Database Interface (quartus_cdb) with --write_rcf_for_vqm option
ID:39020 Successfully back-annotated assignments using demotion type <name>
ID:39021 Compiler Database Interface (quartus_cdb) --update_mif option is not supported for <name> device family. To use --update_mif option, specify a supported target device family.
ID:39022 Found no valid Memory Initialization File to process
ID:39023 Can't find Memory Initialization File <name> -- skipped updates for this file
ID:39024 Processed the following Memory Initialization File(s)
ID:39025 Processed Memory Initialization File <name>
ID:39026 Can't generate Verilog Quartus Mapping File <name> -- VQM File path specified for Compiler Database Interface (quartus_cdb) --vqm option is invalid
ID:39027 Specify a Verilog Quartus Mapping File name for Compiler Database Interface (quartus_cdb) --vqm option
ID:39036 Can't generate directory <name> -- make sure you can write to the directory
ID:39054 Generated Verilog File <name>
ID:39055 Can't generate Verilog File <name> -- Verilog File path specified for Compiler Database Interface (quartus_cdb) --write_verilog_file option is invalid
ID:39056 Generated FV4 Names Mapping File <name>
ID:39057 Can't generate FV4 Names Mapping File <name> -- make sure that you can write to the file and directory
ID:39060 Atom netlist type "<name>" specified for Compiler Database Interface (quartus_cdb) --netlist_type option is not valid
ID:39061 No compilation database found for atom netlist type "<name>" -- run the necessary Quartus Prime software to generate the database
ID:39062 VQM Writer (quartus_cdb) cannot be run -- Analysis and Synthesis (quartus_map) or Fitter (quartus_fit) failed
ID:39063 Can't generate Quartus Placement Exchange File <name> -- make sure that you can write to the file and directory
ID:39064 Can't generate Quartus Routing Exchange File <name> -- make sure you can write to the file and directory
ID:39065 Generated Quartus Placement Exchange File <name>
ID:39066 Generated Quartus Routing Exchange File <name>
ID:39067 You are either not running the Assembler (quartus_asm) with revision <name> or your license does not support all the Quartus Prime software features. Check your software version before running the Compiler Database Interface (quartus_cdb) with --generate_hc_files option
ID:39068 Skipping merge stage since incremental compilation was disabled for Analysis and Synthesis
ID:39069 Run Fitter (quartus_fit) before running Compiler Database Interface (quartus_cdb) with --generate_hc_files option
ID:39072 Run Assembler (quartus_asm) with revision <name> for --rev option before running Compiler Database Interface (quartus_cdb)
ID:39074 Can't generate Verilog Quartus Mapping File -- Compiler Database Interface (quartus_cdb) with the --vqm option is not supported for <name> device family. To use --vqm option, specify a supported target device family
ID:39075 Ignored Partition Merge command-line netlist type override to undefined partition <name>
ID:39076 Ignored Partition Merge command-line netlist type override to Imported partition <name>
ID:39077 Partition Merge does not support command-line netlist type override setting of Source File -- using previous synthesis results instead for partition <name>
ID:39078 Other Compiler Database Interface (quartus_cdb) options cannot be used when --<name> option is used. Use only the --<name> option
ID:39080 Can't remove file <name>
ID:39081 Can't write to file <name>
ID:39082 Required --netlist_type option for equation writer has not been specified.
ID:39083 Atom netlist type "<name>" specified for Compiler Database Interface (quartus_cdb) --netlist_type option is not valid for equation writer
ID:39084 Found Compiler Database Interface (quartus_cdb) options that can modify the Quartus Prime Settings File (.qsf) -- you must specify the --write_settings_files option to update the .qsf
ID:39092 The current license file does not support the --<name> option
ID:39093 Incremental compilation is not enabled -- Partition Merge is not required
ID:39097 Can't generate Verilog Quartus Mapping File -- Compiler Database Interface (quartus_cdb) with the --vqm option is not supported for <name> device family. To use --vqm option, specify a supported target device family
ID:39098 Can't generate node location assignments -- Compiler Database Interface (quartus_cdb) with the node location option (i.e. lc, lab or routing) is not supported for the target device family.
ID:39100 You must specify an option or an action to perform.
ID:40000 alt2gxb_reconfig megafunction instantiation does not use read or write_all control input. Read or write_all control input should be used.
ID:40002 NUMBER_OF_RECONFIG_PORTS should be set to be <correct_val> (number of quads). However, it is currently set to be <current_val>.
ID:40003 BASE_PORT_WIDTH should be set to be either 1 or to NUMBER_OF_CHANNELS. It is currently set to <val>.
ID:40004 Read control input is used. However, none of read data ports are used.
ID:40005 Write control input is used. None of the write data ports are used.
ID:40006 Read data ports are used. The read control port is not used.
ID:40007 Write data ports are used. Write control port is not used.
ID:40008 Read data port <read_port_name> is used. However, the corresponding write input port <write_port_name> is not used.
ID:40009 Alt2gxb_reconfig megafunction has been instantiated with <number_of_channels> channels. However, the megafunction supports 160 channels maximum.
ID:40010 Alt2gxb_reconfig megafunction has been instantiated with too few reconfig_mode_sel bits for the given options. Re-examine the selected options or increase the width of the reconfig_mode_sel bus.
ID:40011 TX_PREEMP_PORT_WIDTH should be set to be 5. It is currently set to <val>.
ID:40012 RX_EQDCGAIN_PORT_WIDTH should be set to be 3. It is currently set to <val>.
ID:40013 tx_preemphasisctrl_pretap and tx_preemphasisctrl_2ndposttap ports are not supported by Arria II alt2gxb_reconfig megafunction.
ID:40014 RX_EQDCGAIN_PORT_WIDTH should be set to be 2. It is currently set to <val>.
ID:41000 Invalid NUMBER_OF_QUADS port value
ID:41001 Invalid int_rx_dwidth_factor value
ID:41002 Invalid int_rx_word_aligner_num_byte value
ID:41003 The value of INT_TX_DWIDTH_FACTOR is invalid
ID:41004 The chosen data rate or input clock frequency cannot be implemented. (The value of tx_pll_m_divider is invalid)
ID:41005 The chosen data rate or input clock frequency cannot be implemented. (The value of tx_pll_n_divider is invalid)
ID:41006 The chosen data rate or input clock frequency cannot be implemented. (The value of rx_cru_m_divider is invalid)
ID:41007 The chosen data rate or input clock frequency cannot be implemented. (The value of rx_cru_n_divider is invalid)
ID:43000 ALTGX_RECONFIG megafunction instantiation does not use read or write_all control input. Read or write_all control input should be used.
ID:43001 ALTGX_RECONFIG megafunction is not supported for the <value> device family
ID:43002 NUMBER_OF_RECONFIG_PORTS should be set to be <correct_val> (number of quads). However, it is currently set to be <current_val>.
ID:43003 BASE_PORT_WIDTH should be set to be either 1 or to NUMBER_OF_CHANNELS. It is currently set to <val>.
ID:43004 Read data ports are used. The read control port is not used.
ID:43005 Write data ports are used. Write control port is not used.
ID:43006 Read data port <read_port_name> is used. However, the corresponding write input port <write_port_name> is not used.
ID:43007 Alt2gxb_reconfig megafunction has been instantiated with <number_of_channels> channels. However, the megafunction supports 160 channels maximum.
ID:44000 alt_dprio megafunction instantiation does not use any control inputs. At least one control input -- wren, rden or rdinc -- should be used.
ID:45000 Parameter error: RIGHT_SHIFT_DISTANCE parameter value is <integer>, but must be less than value <integer> of WIDTH_OUT parameter
ID:45001 Parameter error: WIDTH_IN parameter value is <integer>, but must be greater than 0
ID:45002 Parameter error: WIDTH_OUT parameter value is <integer>, but must be greater than 0
ID:45003 clock port must always be connected
ID:45004 Parameter error: WIDTH_IN parameter value is <integer>, but must be less than or equal to value <integer> of WIDTH_OUT parameter
ID:46000 Selected configuration device, (<string>), is illegal.
ID:46001 Value for PAGE_SIZE (<number>) is larger than the maximum value of (<number>)
ID:46002 shift_bytes port should not be used in combination with single-byte write circuit
ID:46003 shift_bytes input port must be used in combination with page write circuit
ID:46004 illegal_write output port must be used in combination with write circuit
ID:46005 illegal_erase output port must be used in combination with sector erase or bulk erase circuit
ID:46006 Selected device family, (<string>), does not support active serial memory interface (ASMI)
ID:46007 Selected configuration device, (<string>), does not support fast read instruction.
ID:46008 fast read port should not be used in combination with read port
ID:46009 Selected configuration device, (<string>), does not support read_sid instruction.
ID:46010 Selected configuration device, (<string>), does not support read_rdid instruction.
ID:46011 Selected device family, (<string>), does not support dual or quad data transfer
ID:46012 Selected configuration device, (<string>), does not support dual or quad data transfer
ID:46013 Selected configuration device, (<string>), does not support 4-byte addressing
ID:47000 In altbarrel_shift megafunction, the value of WIDTH parameter is <number>. It should be greater than or equal to 2.
ID:47001 In altbarrel_shift megafunction, the value of WIDTHDIST parameter is <number>. It must be greater than 0.
ID:47002 In altbarrel_shift megafunction, the value of WIDTHDIST parameter is <number>. It should be ceil(log2(<number>)) or less.
ID:47003 In altbarrel_shift megafunction, the value of SHIFTTYPE parameter is <text>. It should be ROTATE, LOGICAL, or ARITHMETIC.
ID:47004 In altbarrel_shift megafunction, the value of PIPELINE parameter is <number>. It should be in the range from 0 to WIDTHDIST, which is <number>.
ID:47005 In altbarrel_shift megafunction, the value of <text> parameter is <text>. It is not supported in current version.
ID:47006 In altbarrel_shift megafunction, the value of parameter SHIFTDIR is <text>, but the input port direction is not connected
ID:48002 Parameter error: CLK_NUM parameter set to value <integer> is illegal -- CLK_NUM parameter must be greater than zero!
ID:48003 Parameter error: WIDTH_CLKSELECT parameter set to value <integer> is illegal -- WIDTH_CLKSELECT parameter must be greater than one if clkselect port is used!
ID:48004 Parameter error: CLK_NUM parameter set to value <integer> is illegal for NON LE implementation -- legal values for CLK_NUM parameter are 1, 2, 3 or 4!
ID:48005 Parameter error: WIDTH_CLKSELECT parameter set to value <integer> is illegal for NON LE implementation-- legal values for WIDTH_CLKSELECT parameter are 1 or 2!
ID:48006 Parameter error: NUMBER_OF_CLOCKS parameter value is <integer>, but must be less than or equal to 2 to the power of the value <integer> of WIDTH_CLKSELECT parameter
ID:53003 DUAL PORT RAM for <name> not possible with the altsyncram megafunction. Implementing using benchmarking mode, trying to tie up the inputs using available clocks. Output behavior will not be the same
ID:53004 Value of the parameter BYTE_SIZE <byte_size> is illegal for the current set of parameters. The legal range of values are <range>
ID:53006 Ignoring parameter <name> that uses input register with clear signal -- MLAB block for device family <name> of altdpram megafunction cannot use input registers with clear signals
ID:53007 Ignoring <name> control register and clear parameters of altdpram megafunction, as the <name> control parameters should be the same as the <name> address parameters for the specified configuration
ID:53008 Port <name> can be used only when the <ctrl> address is registered
ID:53009 Ignoring port because the <name> block for the device family <name> of the ALTDPRAM megafunction cannot use the rden port signal
ID:53010 Port <name> is connected in the ALTDPRAM megafunction, but it cannot be used with the <name> block for the device family <name>
ID:53011 Can't convert MLAB design to use block RAM when the read address is unregistered or an initialization file is used
ID:54000 Parameter error: DDIOINCLK_INPUT parameter of altdq megafunction has value DQSB_BUS, but parameter value must be NEGATED_INCLK when using <value> device family
ID:56000 Parameter error: INPUT_FREQUENCY parameter value is <value>, but must be a numeric frequency value
ID:56001 Parameter error: NUMBER_OF_DQS_CONTROLS parameter value is <value>, but can only be 1 or <value>
ID:56002 Parameter error: DLL_PHASE_SHIFT parameter value is <value>, but must be an unsigned floating point value
ID:56003 Parameter error: <name> parameter value is <value>, but can only be <value>
ID:56004 Parameter error: <name> parameter value is <value>, but can only be <value>
ID:56005 Parameter error: DQSN_MODE parameter value is <value>, but must be NONE or OUTPUT when parameter GATED_DQS is set to TRUE
ID:56006 Parameter error: DQSN_MODE parameter value is <value>, but must be NONE when parameter GATED_DQS is set to TRUE
ID:56007 Parameter error: DQSN_MODE parameter value is <value>, but must be NONE or INPUT
ID:56008 Altdqs megafunction is not supported for <value> device family
ID:56009 Parameter error: DQS_DELAY_REQUIREMENT parameter of altdqs megafunction is not specified, but is required when HAS_DQS_DELAY_REQUIREMENT parameter is set to TRUE
ID:56010 Parameter error: DQS_DELAY_REQUIREMENT parameter of altdqs megafunction has value <value>, but value must be a numeric time value
ID:56011 Parameter ignored: when DQS_DELAY_CHAIN_LENGTH parameter is set to 0, the DLL_DELAYCTRL_MODE parameter value must be set to none
ID:56012 Parameter ignored: when DQS_OE_REGISTER_MODE parameter is set to NONE, <name> parameter value must be set to <value>
ID:56013 INPUT_FREQUENCY parameter value has no units -- assigning default units of <value> for the INPUT_FREQUENCY parameter value
ID:57000 Parameter warning : LPM_PIPELINE value is <integer>, which is > 2! This increases the latency, and no optimization in the circuit.
ID:57001 Parameter error : WIDTH_DATAWORD value is <integer>, which is out of the range from 1 to 64
ID:57002 Parameter error : WIDTH_CODEWORD value is <integer>, which is out of the range from 4 to 72
ID:57003 Parameter error : WIDTH_CODEWORD value is <integer>, which does not match the expected value for WIDTH_DATAWORD value of <integer>
ID:57004 Parameter error : LPM_PIPELINE value is <integer>, which is invalid!
ID:57005 Port error : Port clock cannot be used when LPM_PIPELINE is set to 0!
ID:57006 Port error : Port clock must be used when LPM_PIPELINE is set to greater than 0!
ID:57007 Port error : Port clocken cannot be used when LPM_PIPELINE is set to 0!
ID:57008 Port error : aclr cannot be used when LPM_PIPELINE is set to 0!
ID:58000 Parameter warning : LPM_PIPELINE value is <integer>, which is > 2! This only increases the latency, and not the optimization in the circuit.
ID:58001 Parameter error : WIDTH_DATAWORD value is <integer>, which is out of the range from 1 to 64
ID:58002 Parameter error : WIDTH_CODEWORD value is <integer>, which is out of the range from 4 to 72
ID:58003 Parameter error : WIDTH_CODEWORD value is <integer>, which does not match the expected value for WIDTH_DATAWORD value of <integer>
ID:58004 Parameter error : LPM_PIPELINE value is <integer>, which is invalid!
ID:58005 Port error : Port clock cannot be used when LPM_PIPELINE is set to 0!
ID:58006 Port error : Port clock must be used when LPM_PIPELINE is set to > 0!
ID:58007 Port error : Port clock cannot be used when LPM_PIPELINE is set to 0!
ID:58008 Port error : aclr cannot be used when LPM_PIPELINE is set to 0!
ID:82000 Ignored parameter WIDTH_S -- parameter not supported
ID:82001 Ignored parameter NUMBER_OF_COEFFICIENTS -- parameter not supported
ID:82002 Ignored parameter MAX_CLOCK_CYCLES_PER_RESULT -- parameter not supported
ID:82003 Ignored input port sel -- port not supported
ID:82004 Ignored input port sload_data -- port not used in current design
ID:82005 Ignored input port sclr -- port not used in current design
ID:82006 Current design must use input port sload_data
ID:82007 Value <integer> for constant coefficient is out of range for WIDTH_C parameter with value <integer>
ID:82008 Parameter error: value <integer> for NUMBER_OF_COEFFICIENTS parameter is greater than value <integer> of WIDTH_S parameter
ID:82009 Parameter error: value <integer> for SHIFT_DISTANCE parameter of lpm_shiftreg megafunction must be less than or equal to value <integer> for LPM_WIDTH parameter
ID:82013 RAM_BLOCK_TYPE <text> is not supported by device family <text> for altmemmult megafunction. Use AUTO instead.
ID:82014 Parameter error: value <integer> of TOTAL_LATENCY parameter is less than the minimum legal value <integer>
ID:83000 Parameter error: In altmult_accum megafunction, WIDTH_RESULT parameter with illegal value <value> must be greater than or equal to WIDTH_A parameter value (<value>) + WIDTH_B parameter value (<value>) if overflow port is used
ID:83001 Parameter error: In altmult_accum megafunction, parameter <name> has illegal value <value> -- value must be greater than 0
ID:83002 Parameter error: In altmult_accum megafunction, parameter <name> has illegal clock value <value>
ID:83003 Parameter error: In altmult_accum megafunction, parameter <name> has illegal asynchronous clock source value <value>
ID:83004 Can't use <name> port of altmult_accum megafunction with <name> device family
ID:83005 Can't use feature <name> of altmult_accum megafunction with <name> device family
ID:83006 Can't use feature <name> in altmult_accum megafunction with <value> device family and current set of parameters
ID:83007 Ignored accum_sload_upper_data port of altmult_accum megafunction because you did not specify accum_sload port
ID:83008 altmult_accum megafunction has illegal width value <value> for accum_sload_upper_data port -- width value must be between 1 and <value>
ID:83009 In altmult_accum megafunction with current set of ports and parameters, accum_sload_upper_data, signa (if used), and signb (if used) ports must share the same clocks and clears for their registers and pipeline registers
ID:83010 Can't use accum_sload_upper_data port of altmult_accum megafunction when scan chain ports are used
ID:83011 Can't generate output port <name> of altmult_accum megafunction when <name> parameter is not set to USED
ID:83012 <name> register is being cleared by the asynchronous clear <clear>
ID:83013 The current configuration of altmult_accum cannot be implemented in dsp blocks. Using Logic Elements instead.
ID:83014 Can't use both <name> and <name> ports in altmult_accum megafunction with <name> device family in DSP block
ID:83015 Can't use both <name> and <name> ports in altmult_accum megafunction with <name> device family in DSP block. Switch the implementation to logic cells.
ID:83016 Can't use <name> port of altmult_accum megafunction with <name> device family
ID:83017 Can't use feature <name> of altmult_accum megafunction with <name> device family
ID:83018 Can't use <name> port of altmult_accum megafunction with <name> device family in DSP block, the implementation will be put into logic cells
ID:83019 Can't use <name> feature of altmult_accum megafunction with <name> device family in DSP block, the implementation will be put into logic cells
ID:83020 Can't use <name> for <name> in altmult_accum megafunction with <name> device family inside DSP block, <name> must have the same CLOCK/clear parameters as the other nodes in the same DSP block slice
ID:83021 Cannot use <name> with unsigned data in altmult_accum megafunction with <name> device family inside DSP block
ID:84000 In altmult_add megafunction, NUMBER_OF_MULTIPLIERS parameter setting is <number>, but value of NUMBER_OF_MULTIPLIERS parameter must be less than or equal to 4
ID:84001 Parameter error: illegal value <text> for DEDICATED_MULTIPLIER_CIRCUITRY parameter
ID:84002 In altmult_add megafunction, NUMBER_OF_MULTIPLIERS parameter setting is <number>, but altmult_add megafunction cannot use scanouta or scanoutb when value of NUMBER_OF_MULTIPLIERS parameter is 3
ID:84003 Value for <name> parameter must be greater than 0
ID:84004 Clock source error: illegal value <text> for <name> parameter
ID:84005 Asynchronous clear source error: illegal value <text> for <name> parameter
ID:84006 Data source error: illegal value <text> for <name> parameter
ID:84007 Data source error: illegal value <text> for <name> parameter
ID:84008 Number representation error: illegal value <text> for <name> parameter
ID:84009 Adder direction error: illegal value <text> for <name> parameter
ID:84010 Cannot connect addnsub1 port when NUMBER_OF_MULTIPLIERS parameter has value <number> -- value must be greater than or equal to 2
ID:84011 Cannot connect addnsub3 port when NUMBER_OF_MULTIPLIERS parameter has value <number> -- value must be greater than or equal to 2
ID:84012 Parameter error: In altmult_add megafunction, <name> parameter has illegal value <text>
ID:84013 Parameter error: In altmult_add megafunction, <name> parameter has illegal value <text>
ID:84014 Cannot use input port <name> of altmult_add megafunction with <name> device family
ID:84015 Asynchronous clear port <name> of altmult_add megafunction clears register <name>
ID:84016 Cannot implement the specified configuration of altmult_add megafunction using DSP blocks -- using logic elements instead.
ID:84018 Cannot use <name> for <name> in altmult_add megafunction with <name> device family inside DSP block, <name> must have the same CLOCK/clear parameters as the other nodes in the same DSP block slice
ID:84019 Cannot use <name> for <name> in altmult_add megafunction with <name> device family inside DSP block, <name> must have the same CLOCK/clear parameters as the other nodes in the same DSP block slice
ID:84020 the <name> device family doesn't support two input scan chain
ID:84021 Cannot use output port <name> of altmult_add megafunction with <name> device family
ID:84022 Parameter <name> has illegal value in altmult_add megafunction with <name> device family in the operation mode <name>. In this operation mode, it only supports up to 18 bit by 18 bit multiplier.
ID:84023 only one loopback port is supported in altmult_add megafunction with <name> device family in the operation mode <name>
ID:84024 Parameter <name> has illegal value in altmult_add megafunction with <name> device family in the operation mode <name>. It only support up to 2 multipliers
ID:84025 Parameter <name> has illegal value in altmult_add megafunction with <name> device family in the operation mode <name>. It supports only up to 44-bit output
ID:84026 Parameter <name> has illegal value in altmult_add megafunction with operation mode <name>.
ID:84027 Parameter <name> has illegal value in altmult_add megafunction with port <name>.
ID:84028 When mode <name> has been selected with device family <name> output bit width can only be up to 36 bits when one of the input is unsigned.
ID:84029 When mode <name> has been selected with device family <name>, port <name> is not supported
ID:84030 When PARAM <name> has the specified parameter value, port <name> is not supported
ID:84031 When mode <name> has been selected with device family <name>, parameter <name> should be 32
ID:84032 When mode <name> has been selected, parameter <name> and parameter <name> should the same
ID:84033 DSP block is using rounding, but the parameter WIDTH_MSB is out of the range. The range of the WIDTH_MSB is decided by the input data width, result width and the operation mode.
ID:84034 DSP block is using saturation, but the parameter WIDTH_SATURATE_SIGN is out of the range. The range of the WIDTH_SATURATE_SIGN is decided by the input data width, result width and the operation mode.
ID:84035 Function <name> in accumulator is not supported in device family <name>. Please use chainout rounding.
ID:84036 Function <name> need <name> data in device family <name>
ID:84037 When width_result bigger than the mathematical width of result and dynamic sign is used, the mega function will sign extends the mathematical result to match the requested width of result
ID:84038 DSP block is using symmetric saturation, but the combination of parameters WIDTH_RESULT, WIDTH_A and WIDTH_B do not allow symmetric saturation
ID:84039 DSP block can only fit one multiplier in <name> mode in <name> device family
ID:84040 <name> mode is only supported with dedicated multipliers in <name> device family
ID:84041 <name> mode must have output_register in <name> device family
ID:84042 <name> mode do not support round and saturation in <name> device family
ID:84043 <name> mode must have at least one register in the path with <name> device family
ID:84044 <name> must use register for input scan chain with <name> device family
ID:84045 <name> must be 44 in chainout mode with <name> device family when chainout saturation is turned on
ID:84046 <name> must be 44 or width_a + width_b + 8 in chainout mode with <name> device family
ID:84047 <name> has illegal value <name> for <name> device family
ID:84048 <name> must select "NO" for <name> device family in <name> mode
ID:84049 <name> should not be "symmetric" for <name> device family when chainout_rounding is turned on
ID:84050 <name> should be 18 + width_a in <name> device family when <name> mode is selected
ID:84051 <name> should be 8 + width_a + width_b to support port <name> in <name> device family
ID:84052 In order to use scan input in <name> device family, 4 multipliers are needed
ID:84053 When inputs are 18 bits and output is 37 bits in sum2 mode, the MSB is generated by logic cell, no rounding and saturation support
ID:84054 When scanout register is applied, the corresponding input data must be from a scanchain, chainout data should be turned on, and the width_a should be 18
ID:84055 When scan chain is selected, all the corresponding input of multipliers should be included except the first multiplier
ID:84056 <name> feature is not supported for the <name> device family
ID:84057 Can't select more than three clock and clock enable pairs in the <name> device family
ID:84058 Can't select more than two asynchronous clear signals for <name> device family
ID:84059 WIDTH_COEF parameter value is illegal
ID:84060 Illegal parameter value: <name> is greater than <name> for PREADDER_MODE=INPUT
ID:84061 Invalid setting: <name> is greater than <name> for PREADDER_MODE=INPUT
ID:84062 Illegal parameter value: SYSTOLIC_DELAY1 and SYSTOLIC_DELAY3 can only be used when NUMBER_OF_MULTIPLIERS equals to 2 or 4
ID:84063 Invalid setting: SYSTOLIC_DELAY1 and SYSTOLIC_DELAY3 are not supported for PREADDER_MODE=<name>
ID:84064 Invalid setting: PREADDER_MODE=SQUARE is not supported for <name>=<name>
ID:84065 Invalid setting: <name> is greater than 17 for PREADDER_MODE=SQUARE
ID:84066 Illegal parameter value: SYSTOLIC_DELAY1 and SYSTOLIC_DELAY3 are used without chainin port
ID:84067 Illegal parameter value: datab port is not instantiated
ID:84068 Illegal parameter value: LOADCONST_VALUE of <name>
ID:84069 Illegal parameter value: parameter <name> = SUB is supported only for signed operations
ID:84070 Illegal parameter value: WIDTH_B is not equal to WIDTH_COEF for PREADDER_MODE=CONSTANT
ID:84071 Illegal parameter value: port <name> is not instantiated for PREADDER_MODE=<name>
ID:84072 Double Accumulator feature is not supported when Accumulator is not used. To use Accumulator, please set "ACCUMULATOR" parameter to "YES"
ID:85000 Parameter error: In altmult_complex megafunction, WIDTH_A parameter value must be greater than 0
ID:85001 Parameter error: In altmult_complex megafunction, WIDTH_B parameter value must be greater than 0
ID:85002 Parameter error: In altmult_complex megafunction, WIDTH_RESULT parameter value must be greater than 0
ID:85003 Illegal parameter value: unsupported input pin used for <name> device family
ID:85004 Illegal parameter value: WIDTH_A and WIDTH_B must be <= 36 and WIDTH_RESULT must be <= 72
ID:85005 Illegal parameter value: the input width for dynamic complex mode must be an even number
ID:85006 Illegal parameter value: for dynamic complex mode, the number of multiplier must be 1
ID:85007 Illegal parameter value: the ALTMULT_COMPLEX megafunction does not support UNSIGNED operation <name> device family
ID:86000 Minimum LPM_PIPELINE setting allowed is <number>. However, LPM_PIPELINE should be more than <number>.
ID:86001 Width of <text> cannot be less than or equal to half of <text>'s width
ID:87000 Selected device family, (<text>), does not support one time programmable (OTP) blocks
ID:90000 In altpriority_encoder megafunction, the value of WIDTH parameter is <number>. It should be at least 2.
ID:90001 Parameter error: In altpriority_encoder megafunction, the value of WIDTHAD parameter is <number> while the WIDTH parameter is <number>. WIDTHAD should be set to <number>, which is the value of ceil(log2(WIDTH)) if WIDTH >= 2, or 1 when WIDTH=1.
ID:90002 In altpriority_encoder megafunction, the value of LSB_PRIORITY parameter is <text>. It should be either YES or NO.
ID:90003 In altpriority_encoder megafunction, the value of PIPELINE parameter is <number>. It should be 0 or more.
ID:90004 In the altpriority_encoder megafunction, the value of the PIPELINE parameter is 0. However, the <text> input port is connected. The input port will be ignored.
ID:90005 In altpriority_encoder megafunction, the value of PIPELINE parameter is <number>. However, the input clock port is not connected.
ID:91000 Illegal device family for Remote Update
ID:91001 Illegal input data width for <string> device family, the legal value is <number>
ID:91002 Illegal output data width for <string> device family, the legal value is <number>
ID:92000 Can't enable option for In-System Memory Content Editor because both clocks are used on ROM
ID:93001 TAP_DISTANCE value is <number>, but must be at least 3
ID:95000 Port <namename> is connected in the ALTDPRAM megafunction -- <name> block for device family <name> of the ALTDPRAM megafunction cannot use wraddrstall signal
ID:95001 Cannot implement altsyncram megafunction because RAM size is too large to use with OPERATION_MODE parameter set to value <value>
ID:95002 Cannot use Memory Initialization File with M-RAM block in altsyncram megafunction
ID:95003 Cannot use READ_DURING_WRITE_MODE_MIXED_PORTS parameter value set to OLD_DATA with M-RAM block in altsyncram megafunction
ID:95004 Cannot use aclr input ports with M-RAM block in altsyncram megafunction
ID:95005 Cannot use byte enable ports with M512 block in altsyncram megafunction
ID:95006 In altsyncram megafunction, clock0 port must always be connected
ID:95007 In altsyncram megafunction, clocken1 port can only be used when clock1 port is used
ID:95008 In altsyncram megafunction, clocken3 port can only be used when clock1 port is used
ID:95009 <par> parameter cannot be set to value <value> for <family> device family
ID:95010 Parameter error: parameter <name> of altsyncram megafunction set to value <value> is illegal -- legal values for parameter <name> are <values>
ID:95011 Parameter error: parameter <name> of altsyncram megafunction set to value <value> is illegal -- legal values for parameter <name> are <choices>
ID:95012 Parameter error: WIDTH_BYTEENA parameter of altsyncram megafunction set to value <value> is illegal -- legal values for WIDTH_BYTEENA parameter must be <name>
ID:95013 Cannot use <name> port when parameter <name> is less than or equal to 1
ID:95014 Connected <name> port of the ALTSYNCRAM megafunction is unused with the current set of parameters
ID:95015 Must connect <name> port of altsyncram megafunction when using current set of parameters
ID:95016 Cannot use OPERATION_MODE parameter value set to ROM with M-RAM block in altsyncram megafunction
ID:95017 Cannot use different clear ports for <name> port and <name> port of altsyncram megafunction when RAM is deeper than one RAM block
ID:95018 Cannot use different <clock or clear> ports for <name> port and <name> port in altsyncram megafunction
ID:95019 Cannot use clear port with <name> port of altsyncram megafunction and OPERATION_MODE parameter set to value <value>
ID:95020 Cannot use OPERATION_MODE set to value BIDIR_DUAL_PORT with <ram_block> block in altsyncram megafunction
ID:95021 In altsyncram megafunction, when OPERATION_MODE parameter is set to <value>, total number of bits (width x depth) between port A and port B must be the same
ID:95022 Cannot use rden_b port with M-RAM block in altsyncram megafunction
ID:95023 Cannot use port A width with port B width in altsyncram megafunction
ID:95024 Cannot use port A and port B width values with RAM_BLOCK_TYPE parameter value set to AUTO and current set of parameters in altsyncram megafunction
ID:95025 Device family <name> does not have <name> blocks -- using available memory blocks
ID:95026 Cannot use <name> port with device family <name> in altsyncram megafunction
ID:95027 Cannot use <name> port with RAM block type <name> in altsyncram megafunction
ID:95028 Cannot use value <name> of parameter <name> with device family <name> in altsyncram megafunction
ID:95029 Ignoring parameter <name> that uses input register with clear signal -- RAM block for device family <name> of altsyncram megafunction cannot use input registers with clear signals
ID:95030 Cannot have disabled and enabled clock enables in <name> registers and on different sides of RAM block of altsyncram megafunction -- if using the same clock, clock enables must be either disabled or enabled on both sides of RAM block
ID:95031 Cannot have different clock enable setting for Port A inputs, Port B inputs and Port B outputs, as they use the same clock
ID:95032 Not using extra address lines in altsyncram megafunction design -- <number> memory words in side <name> specified but total number of address lines is <value>
ID:95033 Insufficient address lines in altsyncram megafunction design -- <number> memory words in side <name> specified but total number of address lines is <value>
ID:95040 Logic cell implementation of Altsyncram megafunction is not supported for <mode> operation mode
ID:95041 Logic cell implementation of Altsyncram megafunction doesn't support initialization file
ID:95042 Device family <name> does not have <name> blocks
ID:95046 CYCLONEII_M4K_COMPATIBILITY variable is set to OFF, but CYCLONEII_SAFE_WRITE parameter is set to <cycii_safe_write>. The CYCLONEII_SAFE_WRITE parameter should be set to NO_CHANGE to be compatible with the CYCLONEII_M4K_COMPATIBILITY setting
ID:95047 In altsyncram megafunction, ECC feature cannot be used for the specified combination of ports and parameters
ID:95048 In altsyncram megafunction, the parameter <par> cannot be set to the value <name> for the RAM block <RAM_BLOCK>
ID:95049 In altsyncram megafunction, output latch for port <port> cannot be asynchronously cleared for the specified device family <dev>, the clear will be ignored.
ID:95050 Ignoring <name> port -- <name> block for device family <name> of altsyncram megafunction cannot use rden signal
ID:95051 Cannot use READ_DURING_WRITE_MODE_PORT_A parameter value set to DONT_CARE with <name> block in altsyncram megafunction
ID:95052 <name> device family does not support the specified configuration. Altsyncram megafunction will support it by tying the byte-enable to the write enable of the relevant slices.
ID:96000 In the ALTTEMP_SENSE megafunction, the value of CLK_FREQUENCY divided by CLK_FREQUENCY_VALUE must be less than 1 MHz
ID:98001 Parameter error: value for LPM_WIDTH parameter of a FIFO buffer must be greater than or equal to 1
ID:98002 Parameter error: value for LPM_NUMWORDS parameter of a FIFO buffer must be greater than or equal to 2
ID:98003 Parameter error: illegal value for USE_EAB parameter of a FIFO buffer
ID:98004 Parameter error: illegal value for LPM_SHOWAHEAD parameter of a FIFO buffer
ID:98005 Parameter error: illegal value for UNDERFLOW_CHECKING parameter of a FIFO buffer
ID:98006 Parameter error: illegal value for OVERFLOW_CHECKING parameter of a FIFO buffer
ID:98007 Parameter error: illegal value for DCFIFO_INVALID_CLOCKS_ARE_SYNCHRONIZED parameter of a FIFO buffer
ID:98008 LPM_WIDTHU parameter has been set to illegal value <value>, but should be set to value <value>
ID:98009 Cannot use Write port width <value> with Read port width <value> in DCFIFO megafunction. The width ratio should be a power of 2.
ID:98010 Cannot set different values for LPM_WIDTH and LPM_WIDTH_R for the specified <value> device family.
ID:98011 Cannot set parameter ADD_USEDW_MSB_BIT to ON if USE_EAB is set to OFF.
ID:98012 Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2
ID:98013 Cannot use Write port width <value> with Read port width <value> for the specified RAM type <value> in DCFIFO megafunction.
ID:99000 Parameter error: In lpm_add_sub megafunction, LPM_WIDTH parameter value must be greater than 0
ID:99001 lpm_add_sub megafunction must use clock port when LPM_PIPELINE parameter is greater than 0, or when lpm_add_sub megafunction uses clock port, LPM_PIPELINE parameter must be greater than 0
ID:100000 In lpm_clshift megafunction, the value of WIDTH parameter is <number>. It should be greater than or equal to 2.
ID:100001 In lpm_clshift megafunction, the value of WIDTHDIST parameter is <number>. It must be greater than 0.
ID:100002 In lpm_clshift megafunction, the value of WIDTHDIST parameter is <number>. It should be ceil(log2(<number>)) or less.
ID:100003 In lpm_clshift megafunction, the value of SHIFTTYPE parameter is <text>. It should be ROTATE, LOGICAL, or ARITHMETIC.
ID:100004 lpm_clshift megafunction must use clock port when LPM_PIPELINE parameter is greater than 0, or when lpm_clshift megafunction uses clock port, LPM_PIPELINE parameter must be greater than 0
ID:100005 In lpm_clshift megafunction, the value of PIPELINE parameter is <number>. It should be in the range from 0 to WIDTHDIST, which is <number>.
ID:101000 lpm_compare megafunction must use at least one output port
ID:101001 Parameter error: In lpm_compare megafunction, LPM_WIDTH parameter must be greater than 0
ID:101002 lpm_compare megafunction must use clock port when LPM_PIPELINE parameter is greater than 0, or when lpm_compare megafunction uses clock port, LPM_PIPELINE parameter must be greater than 0
ID:102000 LPM_MODULUS input value is <integer>. It should be within the range of 1 to 2^<integer>. Assume no modulus input
ID:102001 The data port is not connected or grounded when ALOAD is used
ID:102002 The data port is not connected or grounded when SLOAD is used
ID:102003 CLOCK port is not connected
ID:102004 UPDOWN port is connected and LPM_DIRECTION parameter is used
ID:102005 LPM_WIDTH parameter is not used
ID:102006 LPM_WIDTH parameter should be set to positive integer value
ID:102007 LPM_AVALUE input value is <integer>. It should be less than 2^LPM_WIDTH or less than LPM_MODULUS(if used). Behavior of counter is not defined.
ID:102008 LPM_AVALUE is used when LPM_WIDTH is more than 31. LPM_AVALUE behavior is undefined.
ID:102009 LPM_SVALUE is used when LPM_WIDTH is more than 31. LPM_SVALUE behavior is undefined.
ID:102010 Counter will power up to an undefined state. An asynchronous signal should be asserted before the counter reaches a known state.
ID:103001 Parameter error: LPM_WIDTH parameter value is <integer>, but must be greater than 0
ID:103002 Parameter error: LPM_DECODES parameter value is <integer>, but must be greater than 0
ID:103003 Parameter error: LPM_DECODES parameter value is <integer>, but must be less than or equal to 2 to the power of the value <integer> of LPM_WIDTH parameter
ID:103004 clock input port must be connected when value of LPM_PIPELINE parameter is greater than 0
ID:103005 clock input port must be disconnected when value of LPM_PIPELINE parameter is equal to 0
ID:104000 In lpm_divide megafunction, LPM_WIDTHN must be greater than 0
ID:104001 In lpm_divide megafunction, LPM_WIDTHD must be greater than 0
ID:104002 In lpm_divide megafunction, <CODE>LPM_NREPRESENTATION can only be <CODE>SIGNED or <CODE>UNSIGNED
ID:104003 In lpm_divide megafunction, LPM_DREPRESENTATION can only be SIGNED or UNSIGNED
ID:104004 In lpm_divide megafunction, LPM_REMAINDERPOSITIVE can only be TRUE or FALSE
ID:104005 In lpm_divide megafunction, clock port must be used if LPM_PIPELINE parameter has value more than 0
ID:104006 In lpm_divide megafunction, at least one of output port quotient or remain must be used
ID:104007 In lpm_divide megafunction, LPM_WIDTHN must be less than or equals to 64
ID:104008 In lpm_divide megafunction, LPM_WIDTHD must be less than or equal to 64
ID:105000 Parameter error: value of <name> parameter must be greater than 0
ID:105001 Parameter error: In lpm_mult megafunction, value of LPM_PIPELINE parameter is <integer>, but must be greater than 0 if clock input port is used
ID:105002 Parameter error: DEDICATED_MULTIPLIER_CIRCUITRY parameter with value <text> must be set to AUTO, YES, or NO
ID:105003 Parameter error: USE_EAB parameter with value <text> must be set to ON or OFF
ID:105004 Parameter error: parameter <text> with value <text> must be set to YES or NO
ID:105005 Parameter error: LPM_REPRESENTATION parameter with value <text> must be set to SIGNED or UNSIGNED
ID:106001 Parameter error: LPM_WIDTH parameter value is <integer>, but must be greater than 0
ID:106002 Parameter error: LPM_WIDTHS parameter value is <integer>, but must be greater than 0
ID:106003 Parameter error: LPM_SIZE parameter value is <integer>, but must be greater than 1
ID:106004 Parameter error: LPM_SIZE parameter value is <integer>, but must be less than or equal to 2 to the power of the value <integer> of LPM_WIDTHS parameter
ID:106005 clock input port must be connected when value of LPM_PIPELINE parameter is greater than 0
ID:106006 clock input port must be disconnected when value of LPM_PIPELINE parameter is equal to 0
ID:107000 Can't enable option for In-System Memory Content Editor because both clocks are used on RAM
ID:108000 Parameter error: value of <name> parameter of a FIFO buffer must be greater than or equal to <integer>
ID:108001 Parameter error: value of <name> parameter of a FIFO buffer must be ON or OFF
ID:108002 Parameter error: value of <name> parameter of a FIFO buffer must be less than or equal to value of <integer> of LPM_NUMWORDS parameter
ID:108003 LPM_WIDTHU parameter has been set to illegal value <value>, but should be set to value <value>
ID:109000 "<name>" has an invalid trigger condition
ID:109001 "<name>" has incrementally routed nodes defined, but they are not used by any trigger
ID:110000 Advanced trigger contains a condition for incrementally routed nodes which is no longer supported by this version of Quartus Prime software
ID:110001 Advanced trigger contains an event counter which is no longer supported by this version of Quartus Prime software
ID:111000 Can't open file <name>
ID:112000 <text>
ID:112001 <text>
ID:112002 <text>
ID:113000 Memory Initialization File or Hexadecimal (Intel-Format) File "<name>" contains illegal syntax at line <number>
ID:113001 Memory Initialization File "<name>" contains illegal width value at line <number>
ID:113002 Memory Initialization File "<name>" contains illegal depth value at line <number>
ID:113003 Memory Initialization File "<name>" contains illegal address radix at line <number>
ID:113004 Memory Initialization File "<name>" contains illegal memory radix at line <number>
ID:113005 Can't generate RAM Initialization File <name> from MIF or HEX file -- data word's radix at address <number> not converted properly
ID:113006 Word addressed memory initialization file "<name>" was read in the byte-addressed format
ID:113007 Byte addressed memory initialization file "<name>" was read in the word-addressed format
ID:113008 Memory contents at address "<number>" are already initialized. Overwriting data at line (<number>) of Memory Initialization File "<name>".
ID:113009 Data at line (<number>) of memory initialization file "<name>" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
ID:113010 Data width of the data at line (<number>) of memory initialization file "<name>" is smaller than that of the memory word. Padding with "<name>" on the MSB.
ID:113011 Data width of the data at line (<number>) of memory initialization file "<name>" is smaller than that of the memory word. Padding with "<name>" on the LSB.
ID:113012 Address at line <number> exceeds the specified depth (<number>) in the Memory Initialization File "<name>"
ID:113013 Memory contents are already initialized at the specified addresses. Overwriting data. Found <number> warnings, reporting <number> .
ID:113014 Width of data items in "<name>" is smaller than the memory width. Padding data items to fit in memory. Found <number> warnings, reporting <number> .
ID:113015 Width of data items in "<name>" is greater than the memory width. Wrapping data items to subsequent addresses. Found <number> warnings, reporting <number>
ID:113016 Width of data items in "<name>" is smaller than the memory width. Padding data items with <name> on MSB to fit in memory.
ID:113017 Width of data items in "<name>" is smaller than the memory width. Padding data items with <name> on LSB to fit in memory.
ID:113018 Width of data items in "<name>" is greater than the memory width. Truncating data items to fit in memory.
ID:113019 Width not specified in Memory Initialization File "<name>"
ID:113020 Depth not specified in Memory Initialization File "<name>"
ID:113021 Generated checksum value does not match the value specified at line <number> in Hexadecimal (Intel-Format) File "<name>"
ID:113022 Hexadecimal (Intel-Format) File contains an invalid record type at "<name>" line <number>
ID:113024 Data at line <number> exceeds the specified width (<number>) in the Memory Initialization File "<name>"
ID:113025 Missing syntax END in the Memory Initialization File "<name>"
ID:113026 Memory Initialization File Address <number> is not initialized
ID:113027 Addresses ranging from <number> to <number> are not initialized
ID:113028 <number> out of <number> addresses are uninitialized. The Quartus Prime software will initialize them to "<name>". There are <number> warnings found, and <number> warnings are reported.
ID:113029 Data size does not match the number of bytes at line <number> in Hexadecimal (Intel-Format) File "<name>"
ID:113030 Memory Initialization File address <number> is reinitialized
ID:113031 <number> out of <number> addresses are reinitialized. The latest initialized data will replace the existing data. There are <number> warnings found, and <number> warnings are reported.
ID:113032 RAM Initialization File and Value Change Dump File generation are no longer supported by Hexadecimal (Intel-Format) File and Memory Initialization File. For further information contact Intel Technical Support.
ID:114000 Time value <time> and time unit are illegal
ID:114001 Time value "<time>" truncated to "<time>"
ID:114002 Path "<name>" exceeds <number> characters in length
ID:114003 Path "<name>" exceeds <number> characters in length
ID:114004 Path "<name>" exceeds <number> characters in length
ID:114005 Unable to locate database file "<name>".
ID:114006 Database file "<name>", created by Quartus <sku> <version number> software, is not compatible with current Quartus Prime <version number> software
ID:114007 Database file "<name>" is corrupted. Database error: <text>.
ID:114008 Unable to open database file "<name>" for reading. Database error: <text>.
ID:114009 Unable to write to database file "<name>". Database error: <text>.
ID:114010 Invalid database file name "<name>" -- file name is too long.
ID:114011 Unable read database directory "<name>" due to lack of directory read permission.
ID:114012 Unable to read database file "<name>" due to lack of file read permission.
ID:114013 Unable to write to database file "<name>" due to lack of file write permission.
ID:114014 Unable to write to database directory "<name>" due to lack of directory write permission.
ID:114016 Out of memory in module <name> (%%d megabytes used).
ID:114017 Out of memory in module <name> (%%d megabytes used) while running 32-bit Quartus Prime on a 64-bit Operating System platform. Use the 64-bit Quartus Prime to increase memory capacity.
ID:114018 Disk is full -- current compilation halted.
ID:114020 Invalid option "<name>"
ID:114021 Too many unconstrained timing paths for setup analysis.
ID:114022 Too many unconstrained timing paths for a hold analysis.
ID:114023 Design is fully constrained for <name> requirements.
ID:114024 Design is not fully constrained for <name> requirements.
ID:114025 Found <name> unconstrained clocks. Aborting Timing Constraint Check.
ID:114026 Number of unconstrained <name>: <name>.
ID:114030 <module> (<executable>) failed with <number> error(s) for the revision "<revision>"
ID:114032 Part name "<device part>" is illegal -- specify a target device part belonging to the <device family> device family for the revision "<revision>"
ID:114033 Run a Full Compilation for the revision "<revision>"
ID:114044 Assignment to suppress error messages # <number> has no effect. Suppression rules apply only to info and warning messages.
ID:114045 Assignment to suppress message # <number> has no effect.
ID:114046 Assignment to suppress message # <number> by instance name or entity has no effect.
ID:114047 Assignment at <location> to suppress error message # <number> has no effect. Suppression rules apply only to info and warning messages.
ID:114048 Assignment at <location> to suppress message # <number> has no effect.
ID:114049 Assignment at <location> to suppress message # <number> by instance name or entity has no effect.
ID:115001 Can't generate netlist output files because the encrypted file "<name>" is not the same file for Analysis & Synthesis.
ID:115002 Can't generate programming files for your project because design file "<name>" is encrypted and the license file does not support programming files generation.
ID:115004 Unlicensed encrypted design file: "<name>"
ID:115005 Unlicensed IP: "<name>"
ID:115006 Can't generate programming files for the project because the encrypted source file cannot be located: "<name>"
ID:115007 User bypassed logging of encrypted IP.
ID:115008 Release clears before tri-states option turned on. If you are using EP1S25 revision A or B devices, contact Intel Applications.
ID:115009 Release clears before tri-states option turned on. If you are using EP1S25 revision A or B devices, contact Intel Applications.
ID:115010 To ensure correct operation of the GXB receivers, transmitters and transmitter PLLs on the device, a user reset sequence is required (RELEASE_CLEARS_BEFORE_TRI_STATES option is set to ON)
ID:115011 Synchronous clear or synchronous set signal used on I/O cell register. Programming file will work only on EP1S25 revision C or later devices. If you are using EP1S25 revision A or B devices, contact Intel Applications.
ID:115012 On-chip termination used on banks 3, 4, 7, or 8 is not supported for EP1S40 engineering sample devices. Recompile for EP1S40 production ordering code devices. For more information, contact Intel Applications.
ID:115013 Assembler Options File "<name>", line <number>, column <number>: <text>
ID:115014 Bit settings found in Assembler Options File(s). Programming files will be modified accordingly.
ID:115017 Design contains a time-limited core -- only a single, time-limited programming file can be generated
ID:115018 Design was synthesized in a benchmarking mode. No programming file will be generated.
ID:115026 EP2S60ES device is not POF compatible with the production EP2S60 device. You must recompile the design when you receive production devices.
ID:115027 Intel recommends you read the EP2S60ES errata available on our web site for additional information
ID:115029 Partition "<name>" was compiled when netlist type was set to Empty - the logic dependent on this partition will not operate as specified in the HDL
ID:115030 Assembler is generating device programming files
ID:115031 Writing out detailed assembly data for power analysis
ID:115032 Current device family does not support OpenCore Plus IP cores
ID:115035 No memory initialization file will be produced. The device <name> only has advanced support.
ID:119000 Cannot recognize the specified device family <name>
ID:119001 Cannot select a device from device family <name> because no devices in family are installed
ID:119002 Cannot recognize device <name>
ID:119003 Cannot find device that meets Compiler settings specifications
ID:119004 Automatically selected device <name> for design <name>
ID:119005 Fitting design with smaller device may be possible, but smaller device must be specified
ID:119006 Selected device <name> for design "<name>"
ID:119007 Compilation Report contains advance information. Specifications for device <name> are subject to change. Contact Intel for information on availability. No programming file will be generated.
ID:119009 Compilation Report contains advance information. Specifications for device(s) in the current compile are subject to change. Contact Intel for information on availability. No pin-out will be generated.
ID:119010 Specifications for device <name> are subject to change. Contact Intel for information on availability.
ID:119011 Cannot select a device because the settings are too restrictive: package = <name>, pin count = <name>, speed grade = <name>
ID:119012 Current license file does not support the <name> device family
ID:119013 Current license file does not support the <name> device. Go to the Self-Service Licensing Center on the Intel FPGA website to manage your licenses (https://fpgasupport.intel.com/Licensing/license/index.html).
ID:119014 Insufficient I/O pins in selected migration devices to support device migration
ID:119015 Selected migration devices are illegal
ID:119016 Illegal migration device(s) <names> selected
ID:119017 Conflicting migration devices selected, named <names>
ID:119018 Selected Migration Device List
ID:119019 Selected <name> for migration
ID:119020 Cannot carry out device migration because selected device list contains uninstalled device <name>
ID:119021 Selected migration device list is legal with <number> total of migratable pins
ID:119022 Cannot generate Pin-Out File and floorplan package views relative to the largest SameFrame device -- option is turned off
ID:119023 <name> is an illegal device name and cannot be used for device migration
ID:119024 Selected Technology Migration Device <name> is illegal
ID:119025 <name> is an illegal device name and cannot be used for technology device migration
ID:119026 Design requires too many <name> resources to fit in the selected device or any device in the device family
ID:119027 Design requires <number> <name> resources -- too many to fit in <number> available in the selected device or any device in the device family
ID:119028 I/O standard <name> is not supported for selected device family
ID:119029 Illegal value in Compiler setting <name> changed to family default value <name>
ID:119030 Auto-restart configuration after error option turned on because Local or Remote configuration mode is used
ID:119031 Design requires a UFM block with address width of <number> bits, which does not fit in the selected device or any device in the device family
ID:119032 Auto device selection -- assigned I/O standards are not available in <name>
ID:119033 I/O standard <name> is not available
ID:119034 Auto device selection -- one or more assigned I/O standards are not available in <name>
ID:119035 Auto device selection -- PCI I/O clamp diode is not available in <name>
ID:119036 Auto device selection -- PCI I/O clamp diode is not available in <name>
ID:119037 Ignoring migration device list(s), because an auto device is specified in Quartus Prime Settings File
ID:119038 Default I/O standard <name> converted to I/O standard <name>
ID:119039 User selected device <name> differs from device for post-fit partitions
ID:119040 Partition <name> was previously fit on device <name>
ID:119041 Detected post-fit partitions used with auto device selection -- re-using device <name>
ID:119043 Atom "<name>" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled
ID:120000 Run Fitter (quartus_fit) before Assembler (quartus_asm)
ID:120001 Run Analysis and Synthesis (quartus_map) with top-level entity name "<name>" before running the Assembler (quartus_asm)
ID:120002 Illegal project name "<name>"
ID:120003 Project name is required
ID:120004 Illegal top-level entity name "<name>"
ID:120005 Fitter must be run using device family <name> before running Assembler
ID:120006 Fitter (quartus_fit) must be run using device part <name> as the value for the --part option before running Assembler (quartus_asm)
ID:120007 Device part <name> is illegal
ID:120008 File name "<name>" is illegal
ID:120009 Project name "<name>" is not needed
ID:120010 XML file name required. Refer to --help for legal options.
ID:125000 File <name> is read-only
ID:125001 Cannot open file <name>
ID:125002 Cannot open file <name> for writing.
ID:125003 Invalid section name "<name>". Ignore assignments in section.
ID:125004 Invalid section name "<name>". Ignore assignments in section.
ID:125005 Invalid section name. Ignore assignments in section.
ID:125006 Invalid section name. Ignore assignments in section.
ID:125007 Invalid assignment keyword "<name>". Ignore the assignment.
ID:125008 Invalid assignment keyword "<name>". Ignore the assignment.
ID:125009 Invalid assignment keyword. Ignore the assignment.
ID:125010 Invalid assignment keyword. Ignore the assignment.
ID:125011 Invalid freeform assignment value "<name>". Ignore the assignment.
ID:125012 Invalid freeform assignment value "<name>". Ignore the assignment.
ID:125013 Invalid freeform assignment value. Ignore the assignment.
ID:125014 Invalid freeform assignment value. Ignore the assignment.
ID:125015 Entity name "<name>" not required
ID:125016 Entity name "<name>" not required
ID:125017 Entity name missing or not required
ID:125018 Entity name missing or not required
ID:125019 Section identifier "<name>" not required
ID:125020 Section identifier "<name>" not required
ID:125021 Section identifier missing or not required
ID:125022 Section identifier missing or not required
ID:125023 Assignment value "<name>" specified in -to option for assignment <name> not required
ID:125024 Assignment value "<name>" specified in -to option for assignment <name> not required
ID:125025 Assignment value "<name>" specified in '-to' option not required
ID:125026 Assignment value "<name>" specified in '-to' option not required
ID:125027 Invalid or missing assignment value in '-to' option
ID:125028 Invalid or missing assignment value in '-to' option
ID:125029 Assignment value "<name>" specified in '-from' option for assignment <name> not required
ID:125030 Assignment value "<name>" specified in '-from' option for assignment <name> not required
ID:125031 Assignment value "<name>" specified in '-from' option not required
ID:125032 Assignment value "<name>" specified in '-from' option not required
ID:125033 Invalid or missing assignment value in '-from' option
ID:125034 Invalid or missing assignment value in '-from' option
ID:125035 Assignment value <name> for assignment <name> is invalid.
ID:125036 Assignment value <name> for assignment <name> is invalid.
ID:125037 Assignment value <name> is invalid.
ID:125038 Assignment value "<name>" is invalid.
ID:125039 Invalid assignment value
ID:125040 Invalid assignment value
ID:125041 Invalid assignment value on line <number>
ID:125042 Invalid assignment value on line <number>
ID:125043 Assignment value already exists for assignment <name>. Replacing the existing assignment value with a new assignment value
ID:125044 Assignment already exists for this assignment. Replacing the existing assignment value with a new assignment value
ID:125045 Error reading Quartus Prime Settings file <name>
ID:125046 Error reading Quartus Prime Settings file <name>
ID:125047 Error reading Quartus Prime Settings file <name>, line <number>
ID:125048 Error reading Quartus Prime Settings file <name>, line <number>
ID:125050 Cannot convert file <name>. The file contains one or more syntax errors and its assignments will not be included in the new file format.
ID:125051 Cannot open the project <name>. No Quartus Prime Settings files exist for the revisions listed in Quartus Prime Project file.
ID:125052 Cannot open the project <name>. No Quartus Prime Settings files exist for the revisions listed in Quartus Prime Project file.
ID:125053 Cannot find the revision "<name>" in the project <name>
ID:125054 Cannot find the revision "<name>" in the project <name>
ID:125055 Cannot open revision "<name>". Cannot find the Quartus Prime Settings file for the revision
ID:125056 Cannot open revision "<name>". Cannot find the Quartus Prime Settings file for the revision
ID:125057 Cannot open the project. Cannot find the Quartus Prime Project file <name>
ID:125058 Cannot open the project. Cannot find the Quartus Prime Project file <name>
ID:125059 Converted the project <name> to the new Intel Quartus Prime software file format. Using newly created Quartus Prime Project file <name> and Quartus Settings file in place of all old project files (with extensions .quartus, .psf, .csf, .ssf, .esf).
ID:125060 Assignment "<name>" is no longer supported. The assignment in the Intel Quartus Prime Settings file (.qsf) will be ignored
ID:125061 Changed top-level design entity name to "<name>"
ID:125062 Cannot import assignments from Comma-Separated Value file <name>. The file does not contain at least 'Assignment Name' and 'Value' columns
ID:125063 <text>
ID:125064 <text>
ID:125065 Assignment import was successful. The following assignments were successfully imported from Comma-Separated Value file <name>.
ID:125066 Cannot import all assignments from Comma-Separated Value file <name>. The following lines are missing required columns or contain other errors.
ID:125067 Cannot import assignment information from Comma-Separated Value file <name>. The following lines contain assignment information that was not imported.
ID:125068 Revision "<name>" was previously opened in Quartus <sku> software version <number>. Created Quartus Prime Default Settings file <name>, which contains the default assignment setting information from Quartus <sku> software version <number>.
ID:125069 Default assignment values were changed in the current version of the Intel Quartus Prime software. Change to default assignments values are contained in file <name>
ID:125070 Invalid argument specified for the assignment.
ID:125071 Truncated specified assignment value "<name>" to "<value>"
ID:125072 Specified assignment value "<name>" must be either On or Off
ID:125073 Specified assignment value <name> must be an integer
ID:125074 Specified assignment value "<name>" must be an integer ranging from <number> to <number>
ID:125075 Specified assignment value "<name>" must be of type double
ID:125076 Specified assignment value "<name>" must include one of the following values: <value>
ID:125077 Cannot convert assignments. The following assignments contain errors and were not imported to the converted project
ID:125078 Cannot import settings. Settings file <name> has unrecognized file extension
ID:125079 The project setting files are read-only and will not be updated with any changes made.
ID:125080 Cannot open the project. Quartus Prime Settings file contains one or more errors
ID:125081 Cannot open the project. Quartus Prime Settings file contains one or more errors
ID:125082 Settings file for current revision has changed. The Intel Quartus Prime software will reset this dialog/window with assignment values from the updated settings file and discard any changes made in the dialog/window
ID:125083 Arguments associated with the following assignment have been removed because the assignment was changed
ID:125084 The Intel Quartus Prime Settings file changed outside of the Intel Quartus Prime software and contains errors. Rewriting the Intel Quartus Prime Settings file with the current state of assignments in the Intel Quartus Prime software.
ID:125085 The Intel Quartus Prime Settings file changed outside of the Intel Quartus Prime software and contains errors. Rewriting the Intel Quartus Prime Settings file with the current state of assignments in the Intel Quartus Prime software.
ID:125086 Cannot open the project. The project or revision name, or the path containing the project, contains one or more of the following invalid characters: <string>. Rename the project or revision, or the folders in the project path, so that it does not contain the specified characters.
ID:125087 Cannot open the project. The project or revision name, or the path containing the project, contains one or more of the following invalid characters: <string>. Rename the project or revision, or the folders in the project path, so that it does not contain the specified characters.
ID:125088 The value for assignment <string> is being truncated from <string> to <string>
ID:125089 Include file "<name>" does not exist
ID:125090 Include file "<name>" does not exist
ID:125091 Tcl error: <name>
ID:125092 Tcl Script file <name> not found.
ID:125093 Tcl Script file <name> contains infinite recursion.
ID:125094 Family name "<name>" is invalid.
ID:125095 Part name <name> is invalid.
ID:125096 Overriding device family setting <name>. Part <name> belongs to device family <name>
ID:125097 The value for assignment <string> is being converted from <string> to <string> because no units were specified
ID:125098 The -family option is invalid.
ID:125099 File name <string> exceeds the maximum number of <number> characters. Specify a file name with fewer characters.
ID:125100 <string> global assignments are not allowed in .qip files.
ID:126000 Node "<name>" is modified or duplicated by <algorithm> -- node is set to Always Allow
ID:126001 Cannot modify or duplicate node "<name>" with <algorithm> -- node is set to USER_DONT_TOUCH
ID:126002 Cannot modify or duplicate node "<name>" with <algorithm> -- node is set to USER_DONT_TOUCH
ID:126003 Cannot modify or duplicate node "<name>" with <algorithm> -- node is set to Don't Touch
ID:126004 Cannot modify or duplicate node "<name>" with <algorithm> -- node is set to Don't Touch
ID:126005 Cannot modify or duplicate virtual I/O node "<name>" with <algorithm>
ID:126006 Cannot modify or duplicate virtual I/O node "<name>" with <algorithm>
ID:126007 Node "<name>" is modified or duplicated by <algorithm> -- node is the destination of an asynchronous transfer
ID:126008 Node "<name>" will not be modified or duplicated by <algorithm> -- node is the destination of an asynchronous transfer
ID:126009 Node "<name>" is modified or duplicated by <algorithm> -- node directly drives an output pin that does not have a tco requirement
ID:126010 Node "<name>" not modified or duplicated by <algorithm> -- node directly drives an output pin that does not have a tco requirement
ID:126011 Node "<name>" is modified or duplicated by <algorithm> -- node directly drives a global signal
ID:126012 Node "<name>" not modified or duplicated by <algorithm> -- node directly drives a global signal
ID:126013 Node "<name>" is modified or duplicated by <algorithm> -- node drives a clock signal
ID:126014 Node "<name>" not modified or duplicated by <algorithm> -- node drives a clock signal
ID:126015 Cannot modify or duplicate node "<name>" with <algorithm> -- node is not a logic cell
ID:126016 Node "<name>" is modified or duplicated by <algorithm> -- node is on a path that crosses clock domains
ID:126017 Node "<name>" is modified or duplicated by <algorithm> -- asynchronous data/load port on node will be routed on a non-global network
ID:126018 Node "<name>" is modified or duplicated by <algorithm> -- asynchronous clear port on node will be routed on a non-global network
ID:126019 Post-fit node "<name>" is modified or duplicated by <algorithm>
ID:126020 Cannot modify or duplicate post-fit node "<name>" with <algorithm>
ID:126021 Post-fit node "<name>" is modified or duplicated by <algorithm> -- node is marked with preserve location
ID:126022 Cannot modify or duplicate post-fit node "<name>" with <algorithm> -- node is marked with preserve location
ID:126023 Post-fit node "<name>" is modified or duplicated by <algorithm> -- node is marked with preserve location and routing
ID:126024 Cannot modify or duplicate post-fit node "<name>" with <algorithm> -- node is marked with preserve location and routing
ID:126025 Post-fit node "<name>" is modified or duplicated by <algorithm> -- node is marked with preserve location, routing, and tile
ID:126026 Cannot modify or duplicate post-fit node "<name>" with <algorithm> -- node is marked with preserve location, routing, and tile
ID:126027 Node "<name>" is modified or duplicated by <algorithm> -- node directly drives an asynchronous port
ID:126028 Cannot modify or duplicate node "<name>" with <algorithm> -- node belongs to a cascade chain
ID:126029 Cannot modify or duplicate node "<name>" with <algorithm> -- node belongs to a carry chain
ID:126030 Node "<name>" is modified or duplicated by <algorithm> -- node directly drives logic in an entity with a partition boundary
ID:126031 Cannot modify or duplicate node "<name>" with <algorithm> -- node directly drives logic in an entity with a partition boundary
ID:126032 Node "<name>" is modified or duplicated by <algorithm> -- node is directly driven by logic in an entity with a partition boundary
ID:126033 Cannot modify or duplicate node "<name>" with <algorithm> -- node is directly driven by logic in an entity with a partition boundary
ID:126034 Node "<name>" is modified or duplicated by <algorithm> -- node is an output node of an entity with a partition boundary
ID:126035 Cannot modify or duplicate node "<name>" with <algorithm> -- node is an output node of an entity with a partition boundary
ID:126036 Node "<name>" is modified or duplicated by <algorithm> -- node is an input node of an entity with a partition boundary
ID:126037 Cannot modify or duplicate node "<name>" with <algorithm> -- node is an input node of an entity with a partition boundary
ID:126038 Cannot perform <algorithm> -- the following nodes are in different partitions
ID:126039 Node "<name>"
ID:126040 Cannot modify or duplicate node "<name>" with <algorithm>. The node is part of a latch.
ID:126041 Cannot modify ECO modified node "<name>" with <algorithm>
ID:126042 Node "<name>" is modified or duplicated by <algorithm> -- node is part of a synchronization register chain
ID:126043 Node "<name>" will not be modified or duplicated by <algorithm> -- node is part of a synchronization register chain
ID:127000 Can't read Memory Initialization File or Hexadecimal (Intel-Format) File <name> for ROM instance <name>. If the file exists, it is not in correct format.
ID:127001 Can't find Memory Initialization File or Hexadecimal (Intel-Format) File <name> for ROM instance <name>
ID:127002 Can't read Memory Initialization File or Hexadecimal (Intel-Format) File <name> -- setting all initial values to 0
ID:127003 Can't find Memory Initialization File or Hexadecimal (Intel-Format) File <name> -- setting all initial values to 0
ID:127004 Memory depth (<number>) in the design file differs from memory depth (<number>) in the Memory Initialization File "<name>" -- truncated remaining initial content value to fit RAM
ID:127005 Memory depth (<number>) in the design file differs from memory depth (<number>) in the Memory Initialization File "<name>" -- setting initial value for remaining addresses to 0
ID:127006 Memory depth (<number>) in the design file differs from memory depth (<number>) in the Memory Initialization File "<name>" -- setting initial value for remaining addresses to 1
ID:127007 Memory Initialization File or Hexadecimal (Intel-Format) File "<name>" contains "don't care" values -- overwriting them with 0s
ID:127009 Reading initial Memory Initialization File or Hexadecimal (Intel-Format) File <name>
ID:127011 Memory depth (<number>) in the design file differs from memory depth (<number>) in the Memory Initialization File "<name>" -- setting initial value for remaining addresses to never match
ID:127013 Memory width (<number>) in the design file differs from memory width (<number>) in the Memory Initialization File "<name>" -- setting initial value for remaining bits to "don't care"
ID:129000 Input port <name> on atom "<name>", which is a <name> primitive, is not legally connected and/or configured
ID:129001 Input port <name> on atom "<name>", which is a <name> primitive, is not legally connected and/or configured
ID:129002 Input port <name> is not connected, but the Compiler expects this input port to be connected
ID:129003 Input port <name> is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal
ID:129004 Input port <name> of the atom "<name>" is driven by the output port <name> of the atom "<name>", which is a <name> primitive
ID:129005 Input port <name> of the atom "<name>" is not connected
ID:129006 Input port <name> is connected to atom "<name>", but the Compiler expects this input port to be disconnected
ID:129007 Compiler expects input port <name> to be disconnected because the <type> atom "<name>" has its <name> parameter is set to "<number>"
ID:129008 Compiler expects input port <name> to be connected because the <type> atom "<name>" has its <name> parameter is set to "<number>"
ID:129009 Compiler expects input port <name> to be driven by a real signal because the <type> atom "<name>" has its <name> parameter is set to "<number>"
ID:129010 Input port <name> is connected to atom "<name>", which is a <name> primitive, but the Compiler expects this input port to be connected to a <name> primitive
ID:129011 Input port <name> is connected to output port <name> on atom "<name>", but the Compiler expects this input port to be connected to output port <name>
ID:129012 Input port <name> is connected to atom "<name>" and input port <name> is connected to atom "<name>", but the Compiler expects these input ports to be connected by the same source atom
ID:129013 Input port <name> on atom "<name>", which is a <name> primitive, is not legal because <name>
ID:129014 Output port <name> on atom "<name>", which is a <name> primitive, is not legally connected and/or configured
ID:129015 Output port <name> on atom "<name>", which is a <name> primitive, is not legally connected and/or configured
ID:129016 Output port <name> is disconnected, but the Compiler expects this output port to be connected
ID:129017 Output port <name> is connected, but the Compiler expects this output port to be disconnected
ID:129018 Output port <name> is connected to multiple destinations, but the Compiler expects this output port to have exactly one destination
ID:129019 Output port <name> is connected to <number> destinations, but the Compiler expects this output port to have no more than <number> destinations
ID:129020 Output port <name> is connected to atom "<name>", which is a <name> primitive, but the Compiler expects this output port to be connected to a <name> primitive
ID:129021 Output port <name> is connected to input port <name> on atom "<name>", but the Compiler expects this output port to be connected to input port <name>
ID:129022 Output port <name> is connected to atom "<name>" and output port <name> is connected to atom "<name>", but the Compiler expects these output ports to be connected to the same destination atom
ID:129023 The Compiler expects output port <name> to be connected to a <name> primitive
ID:129024 The Compiler expects output port <name> to be connected to input port <name> on a <name> primitive
ID:129025 Output port <name> of atom "<name>" is driving the <name> input port of atom "<name>", which is a <name> primitive
ID:129026 Output port <name> of atom "<name>" is driving the <name> input port of atom "<name>", which is a <name> primitive. This connection is illegal
ID:129027 Atom "<name>" has parameter <name>="<name>"
ID:129029 Input port <name> on atom "<name>", which is a <name> primitive, is not connected to a valid source
ID:129030 Output port <name> of a <name> primitive is a valid source for input port <name> on atom "<name>"
ID:129031 Expecting atoms to be driven by a common source atom:
ID:129032 Expecting atoms to be driven by a common source atom of type <name>:
ID:129033 Input port <name> of <name> atom "<name>" is driven by the output port <name> of <name> atom "<name>"
ID:129034 Input port <name> and input port <name> of atom "<name>", which is a <name> primitive, must be driven by the same source atom.
ID:129035 Input port <name> is driven by output port <name> of atom <name>
ID:129036 Output port <name> on atom "<name>", which is a <name> primitive, is not connected to a valid destination
ID:129037 Output port <name> on atom "<name>", which is a <name> primitive, is driving one or more illegal destinations
ID:129038 Input port <name> of a <name> primitive is a valid destination for output port <name> on atom "<name>"
ID:129039 The <name> parameter of atom "<name>", which is a <name> primitive, must be set to NONE or CLEAR when POWER_UP parameter is set to LOW
ID:129040 The <name> parameter of atom "<name>", which is a <name> primitive, must be set to NONE or PRESET when POWER_UP parameter is set to HIGH
ID:129041 Input port <name> of atom <name> must be sourced by an atom which is placed in a common <name> location
ID:129042 Output port <name> of atom <name> must drive destinations that are placed in a common <name> location
ID:129043 Atom <name>, which is a <name> primitive, is placed at location <name>. Location <name> is part of a <name> placement hierarchy at location <name>.
ID:129044 Atom <name>, which is a <name> primitive, is placed at location <name>. Location <name> is not part of a <name> placement hierarchy.
ID:129045 The <name> node "<name>" has no connected output ports, but it must have at least one.
ID:129046 The <name> node "<name>" has no connected output ports.
ID:129047 Atom "<name>" of type "<name>" is not supported for <name> in the current version of the Quartus Prime software
ID:129048 Atom "<name>" of type "<name>" has "<name>" port "<name>" connected. Use of this atom port is not supported for <name> devices in the current version of the Quartus Prime software
ID:129049 Atom "<name>" of type "<name>" has Boolean parameter "<name>" set to "<name>". This parameter value is not supported for <name> devices in the current version of the Quartus Prime software
ID:129050 "<name>" port has a maximum fan-out node restriction of <name> destinations, which may have exceeded the value specified as the maximum number of fan-out allowed from the node
ID:129051 Atom "<name>" of type "<type>" has time parameter "<param>" set to "<value>". The valid range for this parameter is "<range_min>" to "<range_max>"
ID:130000 The <name> primitive "<name>" has parameter "<name>"="<number>", which is incompatible with <name> primitive "<name>"
ID:130001 The <name> primitive is driven by the "<name>" output port of a <name> primitive "<name>". This configuration requires the PHYSICAL_CLOCK_SOURCE parameter of the "<name>" primitive to be "<number>"
ID:130002 <name> primitive "<name>" is driving <name> primitives that have different values for WYSIWYG parameter "<name>". All <name> destinations must have the same value for the "<name>" parameter.
ID:130003 <name> primitive "<name>" is configured to drive both DQS and nDQS buses simultaneously. All <name> destinations with parameter <name>="TRUE" must be driven by this <name> on the same CLK or CLKN port.
ID:130004 DDIO_OUT primitive "<ddio_name>" must have half-rate mode set to TRUE because it is driven by PHY_CLKBUF primitive "<phy_clkbuf_name>"
ID:130005 When the <port> port of a <atom> primitive is driving out to the <port> port of a <atom> it may not fanout to other destinations
ID:130006 "<name>" parameter of <name> atom <name> is set to "<name>", but should be set to only "dqs" or "dq" when "<name>"=true
ID:130007 The <type> atom "<name>" with <name> set to "<name>" must not have the <name> parameter set to "<name>"
ID:130008 The <name> parameter of atom "<name>" is unspecified or is set to an invalid value "<name>"
ID:130009 Compiler expects <name> primitive "<name>" to have its USE_PVT_COMPENSATION parameter set to "TRUE" because it is driving a <name> primitive that has its USE_PVT_COMPENSATION parameter set to "TRUE".
ID:130010 Found single T7 DELAY_CHAIN primitive "<name>" on DQS postamble/sampling path. The Compiler expects two T7 delay chains on the DQS postamble/sampling path, which are connected in series.
ID:130011 If the specified primitive is instantiated inside an Altera UNIPHY IP Core, make sure that top-level ports of the UNIPHY core are connected properly.
ID:130012 <name> input port of the <name> primitive "<name>" is not connected to VCC.
ID:130013 Source of the <name>[<name>] input port of the <name> primitive "<name>" is invalid. The source must be driven by an <name> primitive or connected to VCC.
ID:131000 Non-calibrated on-chip termination has been disabled due to device temperature settings
ID:132000 Can't update database file <name>
ID:132001 Can't remove incompatible database file <name> from database directory
ID:132002 Database format is incompatible with current version of Quartus Prime software -- Analysis and Synthesis (quartus_map) must be run first
ID:132003 Run Analysis and Synthesis (quartus_map) with top-level entity name "<name>" before running the current Quartus Prime software
ID:132004 Can't create database directory for project in project directory <name>
ID:132005 Can't open project -- at least one file is read-only or you do not have permission to create new files in the project's database directory
ID:134000 Syntax error in file <name>
ID:134001 Parsing line number <number>, column number <number> : <message>
ID:134002 Parsing line number <number>, column number <number> : <message>
ID:134003 The file <name> is write-protected
ID:134004 The file <name> could not be found
ID:136000 Top-level entity name "<name>" specified for revision "<name>" contains illegal characters
ID:136001 Value "<text>" for LPM_HINT parameter contains syntax error(s)
ID:136002 Ignored duplicate of assignment <name> for node "<name>"
ID:136003 Ignored duplicate of assignment <name> = <value> for node "<name>"
ID:136004 Ignored <name> logic option assignment--illegal setting "<value>"
ID:136005 Can't write to Quartus Prime Settings File <name>
ID:136006 Found illegal assignment group name "<name>" -- conflicts with top-level node name
ID:136007 Can't find clock settings "<name>" in current project
ID:136008 Clock settings "<name>" must have specified frequency
ID:136009 Assignment <name> is a negative number or zero, but must be a positive number
ID:136010 Assignment <name> is a negative number or zero, but must be a positive number. Assignment will be ignored
ID:136011 Clock settings "<name>" specifies duty cycle of <number>, but must specify duty cycle between 1 and 99
ID:136012 Delay <delay> is out of acceptable range
ID:136013 Can't find clock settings "<name>" in current project -- ignoring clock settings
ID:136014 Assigned <name> is 0, but must be a positive number greater than 0. Using default fmax requirement.
ID:136015 Found conflicting wildcards in <name> assignments
ID:136016 Node name <name> matches the following wildcards <name> that carry conflicting assignments. Quartus Prime used the assignment from <name>
ID:136017 Ignored <name> assignment to name <name> because the ACF assignment does not support wildcards
ID:136018 Can't read from Quartus Prime Settings File <name>
ID:136019 Can't write to Quartus Prime Settings File <name>
ID:136020 Quartus Prime Settings File <name> is older than the original <name>
ID:136021 Ignored assignment <name> which contains an invalid node name "<name>"
ID:136022 Ignored assignment which contains a Timing Analyzer node name "<name>"
ID:136023 Incompatible bus dimensions on node name "<name>", expecting <= <dimensions> dimension(s)
ID:136024 Wildcard assignments have conflicts involving <number> node<s>. Example matching node is "<node name>". The first wildcard assignment has priority.
ID:136025 Conflicting wildcard "<name>"
ID:137000 Can't generate HDBX file for the project because the encrypted source file cannot be located or attempt to overwrite the source file exists in the Export Database target directory: "<name>"
ID:137001 Can't write to file <name>
ID:137002 Can't analyze version-compatible database file -- file <name> is missing. Refer to file <name> line <number>.
ID:137003 Can't open version-compatible database file <name> -- refer to file <name> line <number>
ID:137004 Can't parse file <name> -- line <number> contains syntax error "<name>"
ID:137006 Ignored assignment <name> -- assignment no longer supported
ID:137007 Ignored assignment <name> containing illegal property "<name>"
ID:137008 Ignored submodule assignment <name> because section identifier <name> is already used in design
ID:139000 Syntax error in XML Keypoint Database <name> at line number <number>, column number <number> : <message>
ID:139001 The keypoint DB name "<name>" is not valid. Use a valid non-empty string name
ID:140000 Can't read LogicLock assignments. The Quartus Prime Settings File <name> is unreadable.
ID:140001 Can't write LogicLock assignments. The Quartus Prime Settings File <name> is unwritable.
ID:140002 Can't write LogicLock assignments. The Quartus Prime Settings File <name> is read-only.
ID:140003 Current license file does not support LogicLock regions. The Quartus Prime software removes all the LogicLock regions in your design automatically.
ID:140004 Can't load LogicLock assignments because the current device family does not support the LogicLock feature
ID:140005 Region requested cannot be found -- it may have been deleted
ID:140006 Region name "<name>" is invalid. A region name cannot have more than <number> characters, must not be empty, and must only contain alphanumeric characters, ASCII punctuation characters, and/or spaces.
ID:140007 Region name "<name>" is reserved -- specify a different name
ID:140008 Name "<name>" is already used by another region -- specify a different name
ID:140009 LogicLock region "<name>" is marked as the root region when a root region already exists -- region is ignored
ID:140010 Maximum number of regions is <number> -- unable to create more regions
ID:140011 Regions exceeded the limit of <number>. Failed to load at least one region.
ID:140012 LogicLock region "<name>" can't have "<name>" as parent region -- either the parent region does not exist or a circular linkage is detected
ID:140013 Invalid origin "<name>" for current device for LogicLock region "<name>" -- resetting to default origin
ID:140014 Origin (<number>, <number>) exceeds parent region boundary for LogicLock region "<name>" -- setting origin to (<number>, <number>)
ID:140015 Invalid size (width: <number>, height: <number>) for LogicLock region "<name>" -- setting width to <number> and height to <number>
ID:140016 LogicLock region "<name>" cannot have members with membership exception because it is not supported -- the exception settings are ignored
ID:140017 LogicLock region "<name>" cannot be disabled because disabled region is not supported -- the setting is ignored
ID:140018 LogicLock region "<name>" cannot be auto-sized because it is not supported -- the setting is ignored
ID:140019 LogicLock region "<name>" cannot have floating region because it is not supported -- the setting is ignored
ID:140020 LogicLock region "<name>" cannot be reserved because it is not supported -- the setting is ignored
ID:140021 LogicLock region "<name>" cannot be auto-sized and have a locked location at the same time
ID:140022 LogicLock region "<name>" cannot be auto-sized when a child region has a locked location
ID:140023 LogicLock region "<name>" cannot have a locked location when the parent region is auto-sized
ID:140024 LogicLock region "<name>" cannot have a locked location when the current device is auto
ID:140025 LogicLock region "<name>" cannot have a fixed size when the current device is auto
ID:140026 Can't resize LogicLock region "<name>" because the resulting origin is illegal
ID:140027 Can't resize LogicLock region "<name>" because the resulting origin and/or size is illegal
ID:140028 Illegal size for LogicLock region "<name>" -- size will make region exceed bounds of its parent LogicLock region
ID:140029 Illegal size for LogicLock region "<name>" -- size will make region too small to contain its child LogicLock regions
ID:140030 Illegal size for LogicLock region "<name>" -- size will make region too small to contain its back-annotated nodes
ID:140031 Can't move LogicLock region "<name>" because the resulting origin is illegal
ID:140032 Can't move or resize LogicLock region "<name>" when the current device is automatically selected
ID:140033 Can't move LogicLock region "<name>" -- at this location, the region will exceed the bounds of its parent LogicLock region
ID:140034 Can't move LogicLock region "<name>" -- device resources at this location don't match resources required by region's back-annotated nodes
ID:140035 Can't move LogicLock region "<name>" -- one or more of it child regions cannot be moved
ID:140036 Root LogicLock region "<name>" is not supported for the current project -- the region is ignored
ID:140037 Operation is not allowed because the current project does not support the root region concept
ID:140038 Can't delete LogicLock region "<name>" because it is the root region
ID:140039 Can't move or resize LogicLock region "<name>" because it is the root region
ID:140040 Can't specify LogicLock region "<name>" as imported because it is the root region
ID:140041 Can't disable LogicLock region "<name>" because it is the root region
ID:140042 Can't specify LogicLock region "<name>" as auto-sized because it is the root region
ID:140043 Can't specify LogicLock region "<name>" as floating because it is the root region
ID:140044 Can't specify LogicLock region "<name>" as reserved because it is the root region
ID:140045 Can't specify a parent region for LogicLock region "<name>" because it is the root region
ID:140046 Can't make LogicLock region "<name>" child of LogicLock region "<name>" because region "<name>" is bigger than region "<name>"
ID:140047 Can't make LogicLock region "<name>" child of LogicLock region "<name>" because region "<name>" is not inside region "<name>"
ID:140048 Can't make LogicLock region "<name>" child of LogicLock region "<name>" because region "<name>" has a locked origin and region "<name>" is auto-sized
ID:140049 Logic lock region "<name>" can't have a member with an invalid destination "<name>" -- the member is ignored
ID:140050 LogicLock region membership exception string "<name>" for member "<name>" of Logic lock region "<name>" is invalid -- the setting is ignored
ID:140051 LogicLock region "<name>" does not contain member with destination "<name>"
ID:140052 Can't add member "<name>" to LogicLock region "<name>" because it already exists in LogicLock region "<name>"
ID:140053 Can't use LL_EXCLUDE assignment due to invalid node name "<name>"
ID:140054 Can't add invalid back-annotated node "<name>" to LogicLock region "<name>"
ID:140055 Can't add back-annotated node "<name>" with invalid location string "<name>" to LogicLock region "<name>"
ID:140056 Can't add back-annotated node "<name>" to LogicLock region "<name>" because it is outside the boundary of the region
ID:140057 Can't add LogicLock back-annotated nodes to region "<name>", because LogicLock region content back-annotation is no longer supported. Use the incremental compilation feature for results preservation.
ID:140058 Can't add LogicLock back-annotated nodes to region "<name>" because the current device is AUTO
ID:140059 Can't use LL_SOURCE_PARTITION_HIERARCHY assignment for LogicLock region "<name>" because it specifies an invalid hierarchy path "<name>"
ID:140060 Can't use LL_SOURCE_REGION assignment for LogicLock region "<name>" because it specifies an invalid region name "<name>"
ID:140061 Can't use LL_SOURCE_REGION assignment for LogicLock region "<name>" because a corresponding LL_SOURCE_PARTITION_HIERARCHY assignment is missing.
ID:140062 Can't use LL_SOURCE_PARTITION_HIERARCHY assignment for LogicLock region "<name>" because a corresponding LL_SOURCE_REGION assignment is missing
ID:140063 Location <name> is not a valid origin for LogicLock region <name>
ID:140064 Can't specify LogicLock region "<name>" as secured because it is the root region
ID:140065 LogicLock region "<name>" cannot contain child regions and be secured at the same time
ID:140066 LogicLock region "<name>" cannot be a child of another user-created region and be secured at the same time
ID:140067 Can't specify LogicLock region "<name>" as secured because the current device is automatically selected
ID:140068 LogicLock region "<name>" cannot be Auto, Floating, or Non-Reserved because it is secured
ID:140069 LogicLock region "<name>" cannot be secured when it is Auto, Floating, or Non-Reserved
ID:140070 Can't specify the security level of LogicLock region "<name>" to be "<name>", either because you do not have the required license or the currently selected device family does not support specifying security level
ID:140071 LogicLock region "<name>" cannot have security routing member because it is not a security routing interface
ID:140072 Can't turn off the security routing interface property of LogicLock region "<name>" because it contains security routing members
ID:140073 LogicLock region "<name>" cannot be a security routing interface because it contains placement-controlling members
ID:140074 LogicLock region "<name>" cannot be a security routing interface because it contains security level assignments to its output signals
ID:140075 LogicLock region "<name>" cannot be a security routing interface because it is the root region
ID:140076 LogicLock region "<name>" cannot contain child regions and be a security routing interface at the same time
ID:140077 LogicLock region "<name>" cannot be a child of another user-created region and be a security routing interface at the same time
ID:140078 Can't specify LogicLock region "<name>" as a security routing interface because the current device is automatically selected
ID:140079 LogicLock region "<name>" cannot be Auto, Floating, and/or Non-Reserved when it is a security routing interface
ID:140080 LogicLock region "<name>" cannot be a security routing interface when it is Auto, Floating, and/or Non-Reserved
ID:140081 LogicLock region "<name>" cannot have an LL_SECURITY_LEVEL assignment when it is a security routing interface. A security routing interface automatically has a security level equal to the maximum security level of all signals assigned to it.
ID:140082 LogicLock region "<name>" cannot have LL_SIGNAL_SECURITY_LEVEL assignments when it is a security routing interface. A security routing interface is reserved for routing signals, and cannot contain logic that generates signals.
ID:140083 LogicLock region "<name>" cannot have placement-controlling members (that is, LL_MEMBER_OF) when it is a security routing interface. A security routing interface is reserved for routing signals, and cannot contain user logic.
ID:140084 Can't specify LogicLock region "<name>" as a security routing interface, either because you do not have the required license or the currently selected device family does not support the separation design flow
ID:140085 Signal name "<name>" is invalid. Ignoring security routing member to Logic lock region "<name>".
ID:140086 LogicLock region "<name>" does not contain a security routing member with signal name "<name>"
ID:140087 LogicLock region "<name>" cannot have LL_SIGNAL_SECURITY_LEVEL assignments because it is not specified as a secured region. Only secured regions can change the security level of their signals.
ID:140088 Can't set LogicLock region "<name>" to unsecured because it contains security level assignments for its signals (that is, LL_SIGNAL_SECURITY_LEVEL). Remove the assignments from the "Security" tab of the LogicLock Region property sheet, and then try the operation again.
ID:140089 Can't specify "<name>" as a signal of LogicLock region "<name>" because LogicLock region "<name>" has already specified it as a signal
ID:140090 Signal name "<name>" is invalid. Ignoring output signal assignment for Logic lock region "<name>".
ID:140091 LogicLock region "<name>" does not contain a signal with name "<name>"
ID:140092 Can't specify security level "<name>" for signal "<name>", because it is higher than "<name>", which is the security level of its source region "<name>"
ID:140093 Can't specify security level "<name>" for region "<name>", because at least one signal of the region has a higher security level
ID:140094 Can't specify a non-rectangular shape for LogicLock region "<name>" because the selected device family does not support non-rectangular LogicLock region
ID:140095 Can't specify a size and location for LogicLock region "<name>" that exceeds the physical boundary of the currently selected device
ID:140096 Can't specify a non-contiguous shape for LogicLock region "<name>" because it is secured
ID:140097 Can't specify LogicLock region "<name>" as secured because it has a non-contiguous shape
ID:140098 LogicLock region "<name>" cannot contain child regions and be non-rectangular at the same time
ID:140099 LogicLock region "<name>" cannot be a child region of another user-created region and be non-rectangular at the same time
ID:140100 LogicLock region "<name>" cannot be Auto and/or Floating, and be non-rectangular at the same time
ID:140101 LogicLock region "<name>" cannot contain back-annotated nodes and be non-rectangular at the same time
ID:140102 Requested operation is not supported because LogicLock region "<name>" is non-rectangular
ID:140103 Attempted merging operation causes a non-rectangular region to be created, but non-rectangular region is not supported by the currently selected device family. The requested operation is ignored.
ID:140104 LogicLock region "<name>" cannot be merged with other region(s) because it is the root region
ID:140105 LogicLock region "<name>" cannot be merged with other region(s) because it is a child region of another user-created region
ID:140106 LogicLock region "<name>" cannot be merged with other region(s) because it contains child region(s)
ID:140107 LogicLock region "<name>" cannot be merged with other region(s) because it contains back-annotated node(s)
ID:140108 LogicLock region "<name>" has an ll_rect assignment that specifies an invalid origin "<name>" - assignment is ignored
ID:140109 LogicLock region "<name>" has an ll_rect assignment that specifies an invalid height "<name>" - assignment is ignored
ID:140110 LogicLock region "<name>" has an ll_rect assignment that specifies an invalid width "<name>" - assignment is ignored
ID:140111 LogicLock region "<name>" has Partial Reconfiguration enabled. The assignment is not supported
ID:140112 LogicLock region "<name>" has Partial Reconfiguration enabled and must be fixed-sized, locked, and reserved.
ID:140113 LogicLock region "<name>" is set to soft. Assignment is ignored because soft regions are no longer supported.
ID:140114 LogicLock region "<name>" is set to limited-reserved. Assignment is ignored because limited-reserved regions are no longer supported.
ID:140115 LogicLock region "<name>" has path-based members. Assignment is ignored because path-based LogicLock members are no longer supported.
ID:140116 One or more LogicLock region membership assignments are unused
ID:140117 "<name>" in region "<name>"
ID:140118 Importing LogicLock region routing constraints from "<name>" for entity "<name>"
ID:140119 Can't import LogicLock region assignments -- Quartus Prime Settings File <name> is read-only
ID:140120 Import completed. <name> assignments were written (out of <name> read). <name> non-global assignments were skipped because of entity name mismatch.
ID:140121 The Import options specified require that the design be elaborated
ID:140122 The specified filename "<name>" does not have a .QSF extension. You will not be able to import this file.
ID:140123 Export completed. <name> of <name> non-LogicLock assignments and <name> of <name> LogicLock Regions were exported.
ID:142000 Run Partition Merge (quartus_cdb --merge) with revision "<name>" before running Incremental Compilation Export (quartus_cdb --incremental_compilation_export)
ID:142001 Incremental compilation export does not support exporting a Post-Fit netlist for a project using an Auto device
ID:142002 The currently selected device family does not support partition export.
ID:142003 Incremental compilation export does not support exporting a project that was not compiled with incremental compilation enabled
ID:142004 Routing cannot be exported because the currently specified device family does not support it
ID:142005 Found atoms of unsupported types during design partition export
ID:142006 Node <name> is an atom of type <name>. It is unsupported for bottom-up design flows using incremental compilation in this version of the Quartus Prime software.
ID:142007 Exported design partition includes one or more complex I/O elements
ID:142008 Node <name> is a complex I/O
ID:142009 Name of export file is unspecified
ID:142010 Name of export file must have .qxp file extension
ID:142011 No LogicLock regions detected in the exported post-fit netlist. No-fit error and circuit performance degradation likely in parent project.
ID:142012 Partition "<name>" is empty. Exported netlist might be invalid.
ID:142013 Cannot perform design partition export because partition boundaries were not preserved
ID:142014 Found "<name>" assigned to the Root Region
ID:142015 Found the following logic assigned to the Root Region -- location constraint conflicts may occur after import
ID:142016 Signal Tap Logic Analyzer is used in the design. You must disable the Signal Tap Logic Analyzer before exporting project as a design partition.
ID:142017 Found Signal Tap Logic Analyzer instance <name>
ID:142018 Incremental compilation export of partition <name> failed -- no partition by that name existed for the last successful compilation
ID:142019 Incremental compilation export of partition <name> failed -- the hierarchy <name> specified for the partition does not exist
ID:142020 Incremental compilation export of partition <name> failed -- sub-partition export is supported only for incremental compilation
ID:142021 Partition "<name>" is empty
ID:142022 Incremental compilation export of post-synthesis netlist failed. Post-fit logic found.
ID:142023 Incremental compilation export failed -- detected illegal assignments
ID:142024 Partition "<name>" contains OpenCore Plus logic -- the bottom-up incremental OpenCore Plus is not supported in this version of the Quartus Prime software
ID:142025 Incremental compilation export failed -- no compilation results available for revision <name>. Compile the specified revision before performing incremental compilation export.
ID:142026 Can't generate version-compatible database file <name> -- make sure you can write to the file and directory
ID:142027 Can't generate directory <name> -- make sure you can write to the directory
ID:142028 Incremental compilation export failed -- partition <name> does not exist in the current project compilation results
ID:142029 Sub-partition "<name>" contains a JTAG debug module -- sub-partition bottom-up incremental compilation with a JTAG debug module is not supported in this version of the Quartus Prime software
ID:142030 Multi-hierarchy partition "<name>" cannot be exported in this version of the Quartus Prime software
ID:142031 Partition "<name>" contains a signal or variable declared in the VHDL or System Verilog packages. Bottom-up incremental compilation flow for the signal or variable declared in the VHDL or System Verilog packages is not supported in this version of the Quartus Prime software
ID:142032 Partition export was unable to export the post-synthesis netlist. The generated Quartus Prime Exported Partition file only includes the post-fitter netlist.
ID:142033 Partition export failed -- no files were written
ID:142034 Post-fit database does not exist -- the generated Quartus Prime Exported Partition File includes only the post-synthesis netlist
ID:142035 At least one hierarchy in the multi-hierarchy partition "<name>" is assigned to the secured LogicLock region "<name>". This is illegal and will cause an error during Fitting.
ID:142036 Incremental compilation export does not support exporting a project after applying ECO changes.
ID:142037 Disabling multiple persona usage for partition "<name>" because it has not been assigned to a reconfigurable LogicLock region
ID:142038 Enabling multiple persona usage for partition "<name>" because it has been assigned to reconfigurable LogicLock region "<name>"
ID:142039 Reconfigurable partition "<name>" contains periphery node "<name>"
ID:142040 Detected illegal nodes in reconfigurable partitions. Only core logic is reconfigurable in this version of the Quartus Prime software
ID:142041 Persona file specified for partition "<name>" could not be read.
ID:142042 Persona file specified for partition "<name>" could not be used. The file was generated with an incompatible version of the Quartus Prime software.
ID:142043 Persona file "<name>"
ID:142044 Detected illegal reconfigurable partition "<name>" with unsupported child partition "<name>"
ID:142045 Detected unsupported compiler-generated partition "<name>" in a project with partial reconfiguration enabled.
ID:142046 Generating persona file "<name>" for reconfigurable partition "<name>"
ID:142047 Generating persona file "<name>" for static logic.
ID:142048 Static persona includes partition "<name>"
ID:142049 Removing all preexisting persona files because static persona is being regenerated in this compilation.
ID:142050 Partition "<name>" is a multi-hierarchy partial reconfiguration partition. This feature is not supported in this version of the Quartus Prime software.
ID:143000 Can't parse Routing Constraints File <name>, line <number>: label "<name>" does not exist. Constraints for all connections relying on this branch point are ignored.
ID:143001 Can't parse Routing Constraints File <name>, line <number>: routing element name "<name>" is not recognized
ID:143002 Can't open Routing Constraints File "<name>"
ID:143003 Device <name> used in the creation of the Routing Constraints File and the current device do not match -- ignoring Routing Constraints
ID:143004 Can't parse Routing Constraints File <name> on line <number> -- string "<name>" is not valid
ID:143005 No routing information was back-annotated because the Fitter failed to route the design
ID:143006 Routing back-annotation is not a supported feature of the target device family
ID:143007 Routing back-annotation for the currently selected device may not port to the next release of Quartus Prime software because the routing for this device is not yet finalized
ID:143008 Routing back-annotation failed because it could not open the Routing Constraints File for writing.
ID:143009 Routing Elements Netlist could not be imported
ID:143010 There were problems parsing the RCF file. Because vpr_cr_die_if_parser_messages is set to ON, the compilation will be aborted immediately.
ID:143011 Can't parse Routing Constraints File <name>, line <number>. The line does not represent a valid routing choice. All routing constraints are ignored.
ID:143012 Cannot parse Routing Constraints File <name>, line <number>: the line does not represent a valid routing resource for an exclusion list.
ID:144000 Can't open report database to get panel data -- place cmp get_report_panel_data Tcl command between cmp start_batch and cmp end_batch Tcl commands
ID:144001 Generated suppressed messages file <name>
ID:146000 The following signals will be compared in waveform comparison
ID:146001 Signal - <name>
ID:146002 The following signals do not exist, either in compared or expected vector source file. Comparison is ignoring them.
ID:146003 Signal - <name>
ID:146004 The following signals do not exist in expected vector source file
ID:146005 Signal - <name> does not exist in the expected waveform
ID:146006 Signal - <name> used to trigger waveform comparison in current vector source file
ID:146007 Clock <name> used to trigger waveform comparison in current vector source file
ID:146008 Waveform comparison is triggered by changes in transitions of <name>
ID:146009 Current vector source file <name> <name>matches compared vector source file <name>
ID:146010 Simulation results from <name> <name>match expected results from vector source file <name>
ID:146011 Simulation results from <name> <name>do not match expected results from vector source file <name>
ID:146012 Simulation results from <name> <name>do not match expected results from vector source file <name>
ID:146013 Current vector source file <name> <name>does not match compared vector source file <name>
ID:146014 Logic level(s) do not match expected level(s)
ID:146015 Logic level(s) do not match expected level(s)
ID:146016 Logic level <number or text> does not match expected logic level <number or text> for node "<name>" at time <time>
ID:146017 Logic level <text> [user type <text>] does not match expected logic level <text> [user type <text>] for node "<name>" at time <time>
ID:146018 Logic level <text> [width <number>] does not match expected logic level <text> [width <number>] for node "<name>" at time <time>
ID:146019 Detected more than <number> mismatched levels -- stopped comparison
ID:146020 File details of compared files do not match
ID:146021 File details of compared files do not match
ID:146022 Current vector source file ends at time <time> and compared vector source file ends at time <time>
ID:146023 Current vector source file ends at time <time> and compared vector source file ends at time <time>
ID:146024 Compared vector source file does not contain node "<name>"
ID:146025 Compared vector source file contains extra node "<name>"
ID:146026 Compared vector source file contains extra node "<name>"
ID:146027 Node "<name>" in compared vector source file is a different type from node in original vector source file
ID:146028 <name> <name>, skip comparison on compared vector source file <name>
ID:146029 Vector source file <name> contains corrupted display information -- correcting display information
ID:146030 Error detected in vector source file <name> -- can't open file
ID:146031 Vector source file <name> contains a syntax error at line <number> -- can't open file
ID:146032 Syntax error encountered in vector source file <name>, line <number>, found text "<text>"
ID:146033 Semantic error encountered in vector source file <file name>, line <line number>, <explanation> <text>
ID:146035 Syntax error in vector source file <name>, bus signal "<name>" found but one or more individual signals within the bus were NOT found -- can't open file
ID:146036 Comment <name> has negative time -- defaulting to zero
ID:146037 Found invalid display line - <name>
ID:146038 Pattern Section of vector source file <name> contains incomplete pattern
ID:146039 Vector source file <name> contains time <time> and time unit <time unit>, but time and unit cannot exceed a maximum of 32 characters
ID:146040 Vector source file <name> contains unsupported feature <name> at line <number>, column <number>
ID:146041 Can't open vector source file <name> because it contains an illegal stop time in relative pattern. The STOP time setting either has an illegal value or is missing entirely
ID:146042 Can't open vector source file <name> because absolute time <time> came after <time> in Pattern Section
ID:146043 Group "<name>" already exists in vector source file <name> -- ignoring second definition
ID:146044 Conflicting vector exists for <input or output> node "<name>" at time "<time>" in vector source file <name> -- ignoring earlier vector
ID:146045 End time not specified in vector source file <name> -- setting end time to 1 ps
ID:146046 Can't open MAX+PLUS generated vector source file <name>
ID:146047 Can't open corrupted vector source file <name>.
ID:146048 Grid period <grid period text> <time unit> is invalid -- defaulting to 10 ns
ID:146049 Vector source file contains syntax error in <name>, line <number>, <reason>
ID:146050 Vector source file contains syntax error in <name>, line <number>, <reason>
ID:146051 Vector source file contains this syntax error in <name>, line <number>, <reason>
ID:146052 Ignore writing the following signals to disk. The Quartus Prime software found signal with same name as signals listed below, but with different properties.
ID:146053 Signal - <name>, width - <number>
ID:146054 Vector file <name> is saved in text format. You can compress it into Compressed Vector Waveform File format in order to reduce file size
ID:146055 Failed to convert vector file <name> into compressed format. It is still saved in text format.
ID:146056 The specified vector file <name> does not exist. No file compression is performed.
ID:146057 Waveform comparison is performed with the following rules
ID:146058 <name>
ID:146059 Unable to stretch or compress the selected waveform interval of "<name>" (<name> ps to <name> ps) to fit into another duration (<name> ps to <name> ps)
ID:146060 Count end value in binary: <name>
ID:146061 Duplicate signals are not written out to vector file <name>
ID:146062 Signal - <name>
ID:146063 Vector file <name> has an extension <extension>, but the vector file content is <name> in compressed format
ID:146064 Pattern Section of vector source file <name> contains incorrect relative pattern for output signal. Pattern must be started with an equal sign "="
ID:146065 This group signal <name> has not been declared before in the GROUP_CREATE section. Quartus Prime may not be able to interpret the transition values of this group signal in the correct order
ID:148000 Found an amendment delay management file (DMF)
ID:149000 Instance name already exists
ID:149001 Illegal instance name
ID:149002 Block name conflicts with name of primitive symbol
ID:149003 Alias "<name>" already exists. Do you want to replace the signals for the new alias with the ones from "<name>"?
ID:149004 Symbol "<name>" already exists. Do you want to reset all the block's I/Os and parameters with the ones from "<name>" and erase all current I/Os and parameters?
ID:149005 Specify a value in the <name> field
ID:149006 Can't name block "<name>" because the name represents the current Block Design File
ID:149007 One or more illegal characters are contained in "<name>"
ID:149008 "<name>" is too long.
ID:149009 Name already exists
ID:150000 Reached end of document. Do you want to continue searching from the start of the document?
ID:150001 Created Block Symbol File <name>
ID:150002 Created AHDL Include File <name>
ID:150003 File <name> is a MAX+PLUS II Graphic Design File. Saving to this file now will overwrite it in Quartus format, which cannot be read by MAX+PLUS II
ID:150004 File <name> is a Quartus II version 2.2 or earlier file. Overwrite the file in current Quartus Prime format?
ID:150005 Can't find Block Symbol File for symbol "<name>" -- if the file exists, it is not located in the Intel-provided or user-defined libraries
ID:150006 Can't find Block Symbol File for block "<name>" -- if the file exists, it is not located in the Intel-provided or user-defined libraries
ID:150007 Created design file <name>
ID:150008 Can't generate design file <name>
ID:150009 Design file <name> already exists. Do you want to update it?
ID:150010 Block Design File <name> already exists. Do you want to overwrite it?
ID:150011 Found unknown error in a Block Symbol File <name>
ID:150012 Block Symbol File <filename> is not generated from MegaWizard Plug-In Manager.
ID:150014 Can't open file <name>. Files created in MAX+PLUS II (DOS version) and earlier are not supported
ID:150015 Enter name of symbol to insert
ID:150016 Can't generate design file -- document is not saved or a project is not opened
ID:150017 Can't open read-only file <name>
ID:150018 File <name> is not a Quartus-generated file. Placed the <type> code for this block at the end of the design file
ID:150019 Can't insert symbol into Block Design File <name> because the symbol represents the current Block Design File
ID:150020 Can't update Block Design File because Block Symbol File for symbol(s) cannot be found -- save current BDF before updating
ID:150021 Can't update Block Design File because Block Symbol File for block(s) cannot be found -- save current BDF before updating
ID:150022 Finished searching document
ID:150023 Finished searching document. Can't find search text
ID:150024 File with the same name as the VHDL or Verilog Design File already exists. Do you want to overwrite the file?
ID:150025 Can't remove VHDL or Verilog HDL Design File
ID:150026 Finished searching document. Replaced <number> occurrences of text "<text>" with replacement text "<text>"
ID:150027 Can't replace with empty string
ID:150028 Finished searching document. No replacements made
ID:150030 Alias "<name>" already exists. Do you want to replace the signals for the new alias with the ones from "<name>"?
ID:150031 Specify a value in the <name> field
ID:150032 One or more illegal characters are contained in "<name>"
ID:150033 Instance name already exists in current Block Design File -- enter a unique instance name
ID:150034 Illegal instance name -- enter a legal instance name
ID:150035 Block name conflicts with name of primitive symbol
ID:150036 Symbol "<name>" already exists. Do you want to reset all the block's I/Os and parameters with the ones from "<name>" and erase all current I/Os and parameters?
ID:150037 Can't name block "<name>" because the name represents the current Block Design File
ID:150038 Block Design File has not been saved yet
ID:150039 Symbol "<name>" has changed. Do you want to update it?
ID:150040 Megafunction <symbol name> is not supported by the selected device family (<family name>)
ID:150041 Megafunction <symbol name> is not supported by the default device family (<family name>)
ID:150042 Updated design file <name>
ID:150043 Filename was too long. Please specify a valid filename.
ID:150044 Created VHDL Component Declaration File <name>
ID:150045 Created Verilog Instantiation Template File <name>
ID:150046 Cannot locate design file for entity "<name>"
ID:150047 File <path> is read-only
ID:150048 Cannot locate top-level file in hierarchy
ID:150049 Cannot open selected entity
ID:150050 Can't open file <name>
ID:151006 Converting MAX+PLUS II netlist arc to connector
ID:151007 Encountered unknown disk error while writing to file <name>
ID:151008 Ignoring corrupt symbol(s) in file <name>
ID:151009 Ignored title block(s) in Graphic Design File <name>
ID:151010 Ignored port <name> in symbol <name> -- port is illegal
ID:151011 Block Design File <name> has an unsupported version number <name>
ID:151012 Can't create Block Symbol File <name> because it has <number> ports which exceed the limit
ID:151013 The design <file_name> is not parsed successfully. <symbol_name> is primitive type in Quartus. Change it to a different name using MAX+PLUS II.
ID:152001 Converting MAX+PLUS II netlist arc to connector
ID:152002 Ignoring corrupt symbol(s) in file <name>
ID:152003 Ignored title block(s) in Graphic Design File <name>
ID:152008 Block Design File <name> has an unsupported version number <name>
ID:152009 Encountered unknown disk error while writing to file <name>
ID:152010 Can't create Block Symbol File <name> because it has <number> ports which exceed the limit
ID:152011 Ignored port <name> in symbol <name> -- port is illegal
ID:152012 The design <file_name> is not parsed successfully. <symbol_name> is primitive type in Quartus. Change it to a different name using MAX+PLUS II.
ID:153000 Can't open file <name> -- error reading file
ID:153001 Reached end of document
ID:153002 Reached start of document
ID:153003 Can't write to file <name>
ID:153004 Can't open file <name>
ID:153005 Can't open file <name> -- file contains no memory cell values
ID:153006 Can't open file <name> -- the address range exceeds operating system limits
ID:153007 File <name> contains error at line <number>
ID:153008 Can't replace memory cell contents
ID:153009 Memory word "<number>" is too long
ID:153010 Memory value "<number>" must be of radix <type>
ID:153011 Selected range does not match the range cut or copied to the clipboard
ID:153012 Can't paste to clipboard contents to read-only memory cells
ID:153013 Insufficient room to paste memory cell values
ID:153014 Number of memory words in MIF or HEX File must be greater than zero
ID:153015 New word size must be greater than zero
ID:153016 No memory devices exist in simulation
ID:153017 Can't replace one or more memory cells
ID:153018 Memory cell cannot be empty
ID:153019 A large value was entered for the Number of words box, and this may affect performance of the Memory Editor depending on the speed of your machine. Do you want to continue with this value?
ID:153020 The entry "<number>" contains an illegal character for radix <type>
ID:153021 The starting address must be less than the ending address
ID:153022 Empty values are not allowed
ID:153023 The address range exceeds the number of words in the open document
ID:153024 One or more data words in the Memory Editor contained don't care values. Changing the Memory Radix may have caused the data word(s) to lose some precision of their values.
ID:153025 Enter an integer between 1 and <number>
ID:154000 Removing the input ports might cause the transition equation and action condition verification to fail. Delete the selected input ports?
ID:154001 Renaming the input port may cause the transition equation and action condition verification to fail. Do you want to rename the selected input port?
ID:154002 State Machine File <name> at (line:<number>, col:<number>) has error : <type>
ID:154003 State Machine File <name> at (line:<number>, col:<number>) has warning : <type>
ID:154004 State <name> contains multiple outgoing transitions to the same destination state
ID:154005 Adding more than one self-feedback transition on a state is not allowed, append equation to the existing self-feedback transition
ID:154006 The entry in <type> table is incomplete.
ID:154007 List <type> is empty
ID:154008 Can't save read-only file <name>
ID:154009 HDL File <name> already exists. Do you want to overwrite the file?
ID:154010 HDL file generation was NOT successful
ID:154011 SMF File <name> has been modified since last change. Save changes to <name>?
ID:154012 Component string name is empty
ID:154013 Component <name> contains an illegal name character combination
ID:154014 Component <name> has already been defined
ID:154015 Component <name> is a reserved VHDL keyword or Verilog HDL keyword. Use a different component name.
ID:154016 Component <type> does not have a name
ID:154017 State machine does not contain any states
ID:154018 State machine does not contain any transition
ID:154019 State machine does not contain a default state
ID:154020 State machine does not contain reset input port
ID:154021 State machine does not contain clock input port
ID:154022 State machine does not drive output port
ID:154023 State <name> does not contain outgoing transition
ID:154024 State <name> does not contain incoming transition
ID:154025 State <name> contains only transition with self-feedback
ID:154026 State <name> does not assign any values to all output ports
ID:154027 State <name> contains multiple outgoing transitions to the same destination state
ID:154028 Syntax error: <text>
ID:154029 State <name> contains only Others <type>
ID:154030 State <name> contains multiple Others <type>
ID:154031 Transition does not have source state, destination state, or both
ID:154032 Action is not tied to a state. This action is ignored.
ID:154033 Action does not have output port, output assignment value, or both
ID:154034 Location <name> contains syntax error <text>
ID:154035 Bus index <name> is either in the opposite direction, or out of the defined range allowed
ID:154036 Input port <name> uses an undefined identifier <name>
ID:154038 State <name> contains multiple outgoing transitions, but one of the transition is always TRUE. As a result, the remaining transitions do not occur.
ID:154039 State <name> contains multiple transitions, but more than one transition equation are TRUE when <text>. As a result, the next state cannot be decided.
ID:154040 State <name> has no transition specified for <text>
ID:154041 State <name> contains multiple incoming transitions, but all equations are always FALSE
ID:154042 All outgoing transitions of state <name> are always FALSE
ID:154043 State <name> contains multiple action assignments to output port <name>, but one of the action assignments is always TRUE. As a result, the remaining actions do not occur.
ID:154044 State <name> has has all action conditions of assignment to port <name> that are are always FALSE
ID:154045 State <name> has a port assignment that cannot be determined when <text>
ID:154046 Transition equation <name> is always FALSE
ID:154047 One of the action equations for the state <name> is always FALSE
ID:154048 Port <name> is created but not used
ID:154049 Output port <name> is assigned an output value <number> in all the action assignments. The port value will not change, unless during reset.
ID:154050 Bus index <name> is either in the opposite direction, or out of the defined range allowed
ID:154051 Identifier <name> is undefined
ID:154052 Number of digits <number> overflow in the base number system
ID:154053 Component <name> contains an illegal name character combination
ID:154054 Component name <name> has been defined
ID:154055 Component <name> is a reserved VHDL keyword or Verilog HDL keyword. Use a different component name.
ID:154056 Component string name is empty
ID:154057 State <name> contains multiple Others <type>
ID:154058 Transition does not have source state, destination state, or both
ID:154059 Action does not have output port, output assignment value, or both
ID:154060 State machine does not contain any states
ID:154061 Syntax error <text>
ID:154062 Uses an undefined identifier <name>
ID:154063 Reached the start of the document. Do you want to continue searching from the end of the document?
ID:154064 Reached the end of the document. Do you want to continue searching from the start of the document?
ID:154065 Finished searching the document
ID:154066 Finished searching document. Can't find searched text.
ID:154067 Files generated to <text>
ID:156000 User templates have been changed since the last save. Do you want to save the user templates?
ID:156001 Do you want to clear all bookmarks in current file?
ID:156002 Do you want to clear all bookmarks in all open files?
ID:156003 Can't create user template directory
ID:156004 Invalid template name
ID:156005 Cannot open selected entity
ID:156006 No matches found
ID:156007 Cannot read file <file_name> <error_message>
ID:156008 Cannot write file <file_name> <error_message>
ID:156009 No selected text in the whole document
ID:156010 Finished search selection
ID:156011 Finished searching document
ID:156012 Reached end of document
ID:156013 Reached start of document
ID:157000 The waveform file successfully converted to <name>.
ID:170000 Node "<name>"
ID:170001 Node "<name>" (dual-output)
ID:170002 Registered output is "<name>"
ID:170003 Combinational output is "<name>"
ID:170004 Cannot allocate memory required -- terminating compilation
ID:170005 Fitter cannot fit the design with the requested ECO changes
ID:170006 Cannot satisfy the ECO changes on the following cells
ID:170007 Ignoring PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES, because it is not between 0.0 and 1.0, inclusive.
ID:170008 Violating the PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES limit because there are more LAB tiles forcibly constrained to high-speed mode than this limit.
ID:170009 Ignoring PLACEMENT_EFFORT_MULTIPLIER because it is not greater than 0
ID:170010 ROUTER_EFFORT_MULTIPLIER option is ignored because the option must be a floating point number greater than or equal to 0.25.
ID:170011 Design contains <number> blocks of type <text>. However, the device contains only <number> blocks.
ID:170012 Fitter requires <number> LABs to implement the design, but the device contains only <number> LABs
ID:170014 Design requires <number> LABs, but device contains only <number> LABs -- attempting to pack register-only logic cells with combinational logic cells
ID:170015 LAB legality constraint that was not satisfied: <name>
ID:170016 Atom <text> is an illegal atom. This atom can not be placed in any LAB because by itself it overuses the available resources. <text>
ID:170017 Cannot place nodes in a single ALM -- the ALM would be illegal because <text>
ID:170018 Cannot place nodes in a single LE -- the LE would be illegal because <text>
ID:170019 Project requires <number> RAM blocks, but the selected device can contain only <number> RAM blocks
ID:170020 Project requires <number> general purpose I/O cells, but the selected device can contain only <number> general purpose I/O pins
ID:170021 Found illegal MIGRATION_RAM_INFORMATION setting in Quartus Prime Settings File for atom <name>
ID:170023 RAM packing for companion revision differs from original RAM packing
ID:170024 Cannot place node "<name>" -- node assigned conflicting sublocation assignments
ID:170025 Fitter requires that more entities of type <type> be placed in a region than are available in the region
ID:170026 Region "<name>" corner: <name>; Region "<name>" corner: <name>
ID:170027 Logic Lock region: "<name>"
ID:170029 The following resources need to be used in this region
ID:170030 Region covers unusable area due to reserved Logic Lock region "<name>"
ID:170031 LE location constraint: <text> came from <text>
ID:170032 Memory usage in current device: <text>
ID:170033 Memory usage required for the design in the current device: <text>
ID:170034 Selected device has <number> memory locations of type <text>. The current design requires <number> memory locations of type <text> to successfully fit.
ID:170035 Logic Lock region <name> is too small to contain its members
ID:170036 The following sample cells belong to the region being placed.
ID:170037 Cannot place following RAM cells or portions of RAM cells -- design does not contain enough RAMs of the required type(s)
ID:170038 Cannot place following RAM cells or portions of RAM cells -- a legal placement which satisfies all the RAM requirements could not be found
ID:170039 The Fitter cannot place <number> RAM cells or portions of RAM cells in the design. Make sure there are enough RAM blocks in the selected device, the address and control signals are properly assigned, and that there are no overly restrictive assignments or Logic Lock regions.
ID:170040 Can't place all RAM cells in design
ID:170041 Cannot place RAM cell "<name>" in assigned location -- RAM too deep, too wide, or location does not support RAM features
ID:170042 The Fitter setting for Equivalent RAM and MLAB Power Up is currently set to Care. More RAMs may be placed in MLAB locations if a different power up behavior is allowed.
ID:170043 The Fitter setting for Equivalent RAM and MLAB Paused Read Capabilities is currently set to Care. More RAMs may be placed in MLAB locations if a different paused read behavior is allowed.
ID:170045 Cannot place RAM cell "<name>" in assigned location - location out of memory
ID:170046 Cannot place RAM cell "<name>" in assigned location -- location cannot support two incompatible RAM assignments
ID:170047 Cannot place RAM cell "<name>" in assigned location -- location cannot support more than two incompatible RAM assignments
ID:170048 Selected device has <number> RAM location(s) of type <name>. However, the current design needs more than <number> to successfully fit. The current design uses <number> RAM location(s) of type <name>.
ID:170049 Migration device has <number> RAM location(s) of type <name>. However, the current design needs more than <number> to successfully fit
ID:170051 You have limited the RAM location(s) of type <name> to <number> . However, the current design needs more than <number> to successfully fit
ID:170053 Fitter has implemented the following <number> RAMs using MLAB locations, which can behave differently during power up than dedicated RAM locations
ID:170054 Fitter has implemented the following <number> RAMs using MLAB locations, which will behave the same as dedicated RAM locations during power up
ID:170055 Fitter has implemented the following <number> RAMs using MLAB locations, which can have different paused read capabilities than dedicated RAM locations
ID:170056 Fitter has implemented the following <number> RAMs using MLAB locations, which will have the same paused read capabilities as dedicated RAM locations
ID:170057 List of RAM cells constrained to <name> locations
ID:170059 List of failed RAM cells
ID:170060 Can't find legal locations for <number> of the <type> slice(s) in the design
ID:170061 Can't place <type> slice <name>, which contains <number> nodes
ID:170062 Cannot place node "<name>" of type <type>
ID:170063 Cannot place node "<name>" constrained to location <name>, but without the location constraint the Fitter would have found a legal location for this node
ID:170064 Node "<name>" of type <type> has no legal location
ID:170067 Cannot place clique "<name>" containing <number> logic cells
ID:170068 List of logic cells in the clique
ID:170069 List of logic cells in the chain (ordered from chain start to end)
ID:170070 Cannot place logic cells assigned to one LAB into a single LAB
ID:170071 Group of cells has been assigned to a single LAB. Some or all of these cells do not have a specific LE sublocation. The Quartus Prime software failed to find a legal sublocation for these cells in the LAB
ID:170072 List of <number> nodes in the ALM
ID:170073 List of <number> nodes in the LE
ID:170074 List of <number> logic cells constrained to a LAB
ID:170075 Cannot find legal location for node "<name>" of type <type>
ID:170076 Cannot place cells because they are locked down to the same physical location
ID:170078 Cannot place node "<name>" of type <type> with location constraints <name> from <name>
ID:170079 Cannot place node "<name>" of type <type>
ID:170083 Cannot route source node "<name>" of type <type> to destination node "<name>" of type <type>
ID:170084 Can't route signal "<name>" to atom "<name>"
ID:170085 Cannot route signal "<name>" to atom "<name>"
ID:170086 Routing constraint for signal "<name>" to atom "<name>" was removed because it caused the Fitter to violate internal hold time guarantees enforced by Quartus
ID:170087 Performance of this circuit may degrade because the Fitter Delay Information is not loaded.
ID:170088 <number> (of <number>) connections in the design require a large routing delay to satisfy hold requirements. Refer to the Estimated Delay Added for Hold Timing Fitter report panel for a summary of the relevant clock transfers. Also, check the timing constraints of the circuits and clocking methodology, especially multicycles and gated clocks.
ID:170089 <text> of routing delay (approximately <text> of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
ID:170090 Routing constraints for signal "<name>" seem to be causing unresolvable routing congestion. The constraints for the signal were removed
ID:170091 Routing constraints for signal "<name>" specify an invalid routing resource
ID:170092 Routing constraints section "<name>" specifies an invalid routing resource
ID:170093 Routing constraints for signal "<name>" specify multiple usages of a single routing resource
ID:170094 Cannot route signal "<name>" to atom "<name>" in the best possible way
ID:170096 Error on line number <number> in constrained routing file. Non-global signal "<name>" is constrained to use a global routing resource. The constraints for this destination will be thrown away by the router
ID:170097 Routing for this connection is constrained
ID:170098 Error on line number <number> in Routing Constraints File
ID:170099 Cannot parse Routing Constraints File on line <number> -- string "<name>" is not valid. Constrained routing will be turned off.
ID:170100 Signal "<name>" in line <number> of Routing Constraints File does not exist
ID:170101 Signal "<name>" in line <number> of Routing Constraints File exists but is not routed. Routing constraints cannot be used for this signal
ID:170102 Cannot parse Routing Constraints File line <number> because label <name> does not exist
ID:170104 Cannot parse Routing Constraints File line <number> -- atom "<name>" does not exist
ID:170105 Atom "<name>" on line <number> of the Routing Constraints File has exact routing constraints but does not have sufficient location constraints
ID:170106 Atom "<name>" does not have sufficient location constraints to preserve its routing
ID:170107 The following atoms have insufficient location constraints to safely use routing constraints
ID:170108 Cannot parse Routing Constraints File line <number> because either the input port <name> or the bus index <number> is not valid for atom "<name>"
ID:170109 Cannot parse Routing Constraints File line <number> -- The atom "<name>" and port <name> are not a target on signal "<name>"
ID:170110 Cannot parse Routing Constraints File line <number> -- The atom "<name>" and port <name>[<number>] are not a target on signal "<name>"
ID:170111 Error on line <number> of Routing Constraints File. Cannot use route port <name> with atom "<name>" due to atom's current configuration
ID:170112 Can't use route port <name> with atom "<name>" due to atom's current configuration. However, the use of this port is highly preferred.
ID:170113 Can't satisfy hard routing constraints for signal "<name>". Remove the "hard" routing specification, remove the constraints for the specified signal, or for DDIO or DQS logic, remove the location constraints that force other logic into the same LAB. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
ID:170114 Cannot parse Routing Constraints File line <number> -- a route port cannot be specified unless the atom is an LE
ID:170115 Cannot parse Routing Constraints File line <number> -- route port <name> is not valid
ID:170116 Routing Constraints File <name> does not exist, using file <name> instead
ID:170117 Cannot open a Routing Constraints File -- routing will continue without constraints
ID:170118 Using constrained routing from file <name>
ID:170119 To finish routing, the Quartus Prime software will remove the routing constraints for this fan-out and will make another attempt at routing this fan-out after all other fan-outs of this signal are routed
ID:170120 Another set of routing constraints encountered for signal "<name>" on line <number>. To finish routing, the Quartus Prime software will disregard this set of routing constraints
ID:170122 Destination port was not specified at line <number>. Correct destination port cannot be guessed. To finish routing, the Quartus Prime software will disregard constraint for this connection
ID:170123 Cannot use DDIO_LOW setting on atom "<name>" because <name>
ID:170124 Detected DDIO low registers in unexpected configurations. Incorrect use of DDIO assignments may create unroutable designs
ID:170125 The following nodes could not be optimally routed by the Fitter to improve DDIO timing
ID:170126 The following nodes could not be optimally routed by the Fitter to improve DDIO timing
ID:170127 DDIO Node "<name>" could not be optimally routed to improve DDIO timing
ID:170128 Fitter could not properly route signals from DQ I/Os to DQ capture registers because the DQ capture registers are not placed next to their corresponding DQ I/Os
ID:170129 DQ capture register <name> at (<number>, <number>) is not assigned to the adjacent LAB of the corresponding DQ I/O <name> at (<number>, <number>)
ID:170130 There was a problem reading the RCF file. vpr_cr_die_if_parser_messages is set to ON so the Fitter will exit now
ID:170131 Fitter routing phase terminated due to predicted failure from <name>
ID:170132 Routing phase ended with <number> interconnect resources used by multiple signals
ID:170133 The likelihood of this design fitting with aggressive routability optimizations is <name>
ID:170134 Cannot fit design in device -- retrying with increased optimization that can result in longer processing time
ID:170135 Fitting attempt failed -- retrying
ID:170137 Fitter placement was successful
ID:170138 Failed to route the following <number> signal(s)
ID:170139 Signal "<name>"
ID:170140 Cannot fit design in device -- following <number> routing resource(s) needed by more than one signal during the last fitting attempt
ID:170141 Routing resource <name>
ID:170142 Disabling physical synthesis netlist optimizations for the next fit attempt
ID:170143 Final fitting attempt was unsuccessful
ID:170144 Signal Probe routing in progress -- routing <number> pins
ID:170145 Incremental routing to signal "<name>" NOT successful
ID:170146 Signal Probe routing successful: successfully routed <number> pins
ID:170147 Nodes or entities assigned to <Logic Lock branding> region "<name>" require <number> cells, but region contains only <number> cells
ID:170148 Reserved locked Logic Lock region "<name>" overlaps with another locked Logic Lock region
ID:170149 Cannot place <Logic Lock branding> region "<name>"
ID:170150 Carry chain spans multiple unrelated <Logic Lock branding> regions
ID:170151 Node "<name>" is in <Logic Lock branding> Region "<name>"
ID:170152 Initial placement of <Logic Lock branding> hierarchy failed after <number> attempts. <Logic Lock branding> region "<name>" had the largest number of placement failures, but may or may not be the cause of the problem. You may be able to correct the situation and achieve placement, by manually altering one or more <Logic Lock branding> regions
ID:170153 Fixed size <Logic Lock branding> region "<name>" is too small for its contents. It requires <number> blocks, but can only accommodate <number>
ID:170154 Fixed size <Logic Lock branding> region "<name>" is not wide enough for its contents. It must be at least <number> LABs wide, but is only <number> LABs wide
ID:170155 Fixed size <Logic Lock branding> region "<name>" is not tall enough for its contents. It must be at least <number> LABs tall, but is only <number> LABs tall
ID:170160 Cannot perform incremental compilation for preferred locations because node "<name>" of type <type> is not assigned to a specific location
ID:170161 Cannot perform incremental compilation for preferred locations due to unplaced or illegally placed carry or cascade chain
ID:170162 Node "<name>"
ID:170163 Incremental compilation for preferred locations cannot place node "<name>"
ID:170167 Incremental compilation for preferred locations cannot place the following nodes
ID:170168 Node "<name>"
ID:170169 Node "<name>" assigned to <Logic Lock Plus> region with lower-left corner <location> and upper-right corner <location>
ID:170178 Ignoring illegal initialization setting <name> = <name> in the quartus.ini file or ini_vars line in the Quartus Settings File
ID:170179 Ignoring illegal setting for setting INITIAL_PLACEMENT_CONFIGURATION = <name> in the Quartus Settings File
ID:170180 Carry chain containing following nodes spans multiple related <Logic Lock branding> regions -- moved all nodes on chain into region "<name>"
ID:170181 Node "<name>" is in Logic Lock Region "<name>"
ID:170182 Logic Lock region "<name>" has Reserved unused logic cells turned on -- ignored soft property for this region
ID:170183 Logic lock Region "<name>" has Soft property turned on -- ignored back-annotated node locations in this region
ID:170184 Logic lock Region "<name>" has Soft property turned on -- ignored locked locations of child Logic Lock regions
ID:170185 Cannot reserve all unused logic cells in Logic Lock region "<name>" -- placed the following additional nodes inside the boundaries of this region
ID:170186 Placed node "<name>" inside boundaries of Logic Lock region "<name>"
ID:170187 The Fitter is enabling the conservative CRC routing mode
ID:170188 Some power optimizations are not enabled because Timing Driven Compile is off
ID:170189 Fitter placement preparation operations beginning
ID:170190 Fitter placement preparation operations ending: elapsed time is <time>
ID:170191 Fitter placement operations beginning
ID:170192 Fitter placement operations ending: elapsed time is <time>
ID:170193 Fitter routing operations beginning
ID:170194 Fitter routing operations ending: elapsed time is <time>
ID:170196 Router estimated peak interconnect usage is <number>%% of the available device resources in the region that extends from location <location> to location <location>
ID:170197 The Fitter will not skip routability optimizations in all subsequent fit attempts
ID:170198 Cannot perform Auto Fit compilation because Auto Fit compilation is not supported for the selected device family
ID:170199 The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
ID:170200 Optimizations that may affect the design's timing were skipped
ID:170201 Optimizations that may affect the design's routability were skipped
ID:170202 The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
ID:170203 Found <number> Logic Lock regions
ID:170204 Region "<name>" is <name>, <name>, location: <name>, size = (<number>,<number>), parent = <name>
ID:170205 Logic Lock region <name>
ID:170206 <Logic Lock branding> region "<name>" has <text>
ID:170207 Following cells are locked down to the device
ID:170208 Cannot place <number> nodes into a single ALM
ID:170209 Cannot place <number> nodes into a single LE
ID:170210 Carry-chain of <number> logic cells and starting on logic cell "<name>" could not be split into legal LABs. The chain will be broken into multiple chains in order to make it legal
ID:170212 Number of LABs at the end of packing: <number>
ID:170213 Number of <name>s at the end of packing: <number>
ID:170214 Number of <name>s at the end of packing: <number>
ID:170217 Fitter has combined <number> register-only logic cells with unrelated combinational logic cells
ID:170218 Fixed size Logic Lock region "<name>" cannot be placed due to its locked location constraint
ID:170219 Logic Lock region has a width of <number> and a height of <number> and is constrained to the region "<location>" corner: <location>; "<location>" corner: <location>
ID:170227 Following cells have incompatible location and/or Logic Lock assignments
ID:170230 Illegal floating Logic Lock region assignments for logic cells from region "<name>"
ID:170231 Fitter will exit after packing is finished
ID:170233 Initial placement failed to reserve space for locked Logic Lock region "<name>" with Reserved property
ID:170234 Fitter stopped after generation of congestion map
ID:170235 Fitter stopped because incompatible FFs have been constrained to the same CBE. FF "<name>" must cluster into a "<text>", FF "<name>" must cluster into a "<text>".
ID:170236 <name> optimizations have been running for <number> hour(s)
ID:170238 <number> interconnect resources are used by multiple signals.
ID:170239 Router is attempting to preserve <percent> percent of routes from an earlier compilation, a user specified Routing Constraints File, or internal routing requirements.
ID:170241 For more information about RAMs, refer to the Fitter RAM Summary report.
ID:170242 <number> out of <number> signals have been routed.
ID:171000 Can't fit design in device
ID:171001 Fitter is performing a Fast Fit compilation, which decreases Fitter effort to reduce compilation time
ID:171002 Current optimization assignments may cause the Fitter to introduce hold timing violations on connections clocked by global signals
ID:171003 Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
ID:171004 Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
ID:171006 The Fitter cannot add location assignment <name> to node <name> with existing location assignment <name>
ID:171007 Demoted location assignment <name> on embedded cell "<name>" to EAB location <name>
ID:171008 Conflicting Constraints Found. See Logic Lock Region Conflict Panel in Fitter Report for details.
ID:171010 Can't assign node "<name>" to index <name> -- node is type <name> and the location assignment is type <name>.
ID:171011 Can't assign node "<name>" to location <name> -- node is type <name>
ID:171012 Can't assign node "<name>" of type <name> in Logic Lock region <name> to location <name>
ID:171013 Can't assign node "<name>" to location <name> -- can't find location
ID:171014 Can't assign node "<name>" in Logic Lock region "<name>" to location <name> -- can't find location
ID:171015 Can't place node "<name>" -- illegal custom region location assignment <name>. Preferred location assignments cannot be custom regions.
ID:171016 Can't place node "<name>" -- illegal location assignment <name>
ID:171017 Can't place node "<name>" with location assignment <name> in Logic Lock region "<name>"
ID:171018 Can't place node "<name>" -- node has multiple location assignments on output ports
ID:171019 Output port <name> assigned to location <name>
ID:171020 Removed Logic Lock region assignments -- nodes in carry chain contain both location assignments and Logic Lock region assignments
ID:171021 Removed Logic Lock region assignments -- nodes in cascade chain contain both location assignments and Logic Lock region assignments
ID:171022 Removed Logic Lock region assignments -- nodes in DSP block slice contain both location assignments and Logic Lock region assignments
ID:171023 Following nodes have location assignments
ID:171024 Node "<name>" assigned to location <name>
ID:171025 Modified Logic Lock region assignments on the following nodes -- nodes belong to a carry chain
ID:171026 Modified Logic Lock region assignments on the following nodes -- nodes belong to a cascade chain
ID:171027 Modified Logic Lock region assignments on the following nodes -- nodes belong to a DSP block slice
ID:171028 Can't place the following nodes in a carry chain -- cannot find a common child Logic Lock region
ID:171029 Can't place the following nodes in a cascade chain -- cannot find a common child Logic Lock region
ID:171030 Can't place the following nodes in a DSP block slice -- cannot find a common child Logic Lock region
ID:171031 Changed Logic Lock region assignment of node "<name>" from Logic Lock region "<name>" to Logic Lock region "<name>"
ID:171032 Assigned node "<name>" to Logic Lock region "<name>"
ID:171033 Removed Logic Lock region assignment <name> from node "<name>"
ID:171034 Assigned node "<name>" to Logic Lock region "<name>"
ID:171035 Changed Logic Lock region assignments on the following nodes
ID:171036 Found Logic Lock region assignments on the following nodes
ID:171037 Removed Logic Lock region assignments from the following nodes
ID:171038 Removed node "<name>" from Logic Lock region "<name>" -- node is used for JTAG programming
ID:171039 Removed node "<name>" from Logic Lock region "<name>" -- node used with a PLL
ID:171040 Removed nodes used for dedicated differential I/O from Logic Lock regions
ID:171041 Removed node "<name>" from Logic Lock region "<name>" -- node is used for dedicated differential I/O
ID:171042 Removed nodes using local clock from Logic Lock regions
ID:171043 Removed node "<name>" from Logic Lock region "<name>" -- node has a local clock assignment that is incompatible with its Logic Lock region assignment
ID:171044 Removed node "<name>" from Logic Lock region "<name>" -- node is used to drive an internal global signal
ID:171045 Removed node "<name>" from Logic Lock region "<name>" -- node is a DQS I/O pin
ID:171046 Removed nodes having a Fast Input or Output Register assignment from Logic Lock regions
ID:171047 Removed node "<name>" from Logic Lock region "<name>" -- node has a Fast Input or Output Register assignment
ID:171048 Removed node "<name>" from Logic Lock region "<name>"
ID:171049 Assigned node "<name>" to location <name>
ID:171050 Can't fit design in device -- nodes in regions on the device require more global signals than are available
ID:171051 Region with lower-left corner at <number>, <number> and upper-right corner at <number>, <number> requires <number> globally routed signals but can contain only <number> globally routed signals
ID:171052 Region with lower-left corner at <number>, <number> and upper-right corner at <number>, <number> has been allocated <number> globally routed signals and can contain up to <number> globally routed signals
ID:171053 Can't globally route <number> more signal(s) into a region -- <number> global signals have been allocated to the region but the hardware only allows <number> global signals
ID:171054 Previous top-level message of the same type contains full explanation of why no more global signal can be routed in this region
ID:171055 Can't globally route signal "<name>" into a region -- total global routing resources requested would exceed hardware limits
ID:171056 No global signals drive into the region with lower-left corner at <number>, <number> and upper-right corner at <number>, <number>, but the region has <number> global routing resources
ID:171057 Signal "<name>" is globally routed to <number> nodes in the region with lower-left corner at <number>, <number> and upper-right corner at <number>, <number>
ID:171058 Signal "<name>" shares global routing with signal "<name>" and is globally routed to <number> nodes in the region with lower-left corner at <number>, <number> and upper-right corner at <number>, <number>
ID:171059 Signal "<name>" is globally routed to node "<name>" in the region with lower-left corner at <number>, <number> and upper-right corner at <number>, <number>
ID:171060 Pin name "<name>", assigned to an I/O cell at location <number>, <number> sublocation <number>, is not connected to the I/O cell on the device
ID:171061 Pin name "<name>", assigned to an I/O cell at location <number>, <number> sublocation <number>, is not connected to the I/O cell on the device selected for migration
ID:171062 ECO Fitter applying ECOs to previous post-fitting netlists
ID:171063 Engineering Change Order (ECO) Fitter is skipping Place and Route
ID:171064 ECO Fit NOT successful
ID:171065 Can't use previous post-compilation netlist in Fitter -- netlist contains duplicates of signal name "<name>"
ID:171066 Can't use previous post-compilation netlist in Fitter -- netlist contains an illegal connection from node "<name>"
ID:171067 Performing incremental routing
ID:171068 Information required for future Signal Probe compilations will not be saved
ID:171069 All pins were used during last compilation -- new Signal Probe assignment(s) not available
ID:171070 Can't duplicate node "<name>" -- node does not exist
ID:171071 Can't duplicate logic when timing-driven compilation options are turned off
ID:171072 Can't duplicate source node "<name>" -- no path exists between source node and destination node "<name>"
ID:171073 Duplicated node "<name>" -- node has only one fan-out
ID:171074 Duplication created possible illegal path between source node "<name>" and destination node "<name>"
ID:171080 Node "<name>" has conflicting location assignments
ID:171081 Ignored location assignment <name> to node "<name>"
ID:171082 Can't place node "<name>" in location or region "<name>" -- location is not compatible with current location of <name> for the node -- location added due to <name>
ID:171083 The Fitter has identified <number> logical partitions of which <number> have a previous placement to use
ID:171084 Detected <number> design partitions (excluding Top) used without floorplan location assignments.
ID:171085 Detected <number> design partitions (excluding Top) used with floating Logic Lock regions
ID:171086 Detected <number> design partitions (excluding Top) used with auto-size Logic Lock regions
ID:171087 Design partition <name> has no floorplan location assignments
ID:171088 Design partition <name> is used with floating Logic Lock region assignments
ID:171089 Design partition <name> is used with auto-size Logic Lock region assignments
ID:171090 Detected <number> design partitions (excluding Top) using post-fit netlists and Logic Lock region assignments -- ignoring Logic Lock region assignments
ID:171091 Design partition <name> contains nodes with a previous placement -- ignoring Logic Lock region assignments
ID:171092 Ignoring previous placement locations for the following nodes because they have conflicting user assignments
ID:171093 Node <name> will be placed according to its user assignment to <name> and ignore its previous placement at <name>
ID:171094 Ignoring location assignments for the following nodes because they are being preserved at their previous Fitter locations.
ID:171095 Node <name> will be placed according to its previous placement at <name> and ignore the location assignment to <name>
ID:171096 Ignoring relative previous placement for following nodes. Specified location of Logic Lock region makes required relative placement illegal.
ID:171097 Node <name> cannot be set at its previous placement relative to its Logic Lock region <name>. That location is invalid for placement.
ID:171098 Found design partitions containing atoms that have an invalid previous placement -- ignoring previous placement
ID:171099 Design partition <name> has atoms with an invalid previous placement
ID:171100 Found <number> conflicting nets in partitions preserving placement and routing
ID:171101 Routing in partition "<name>" conflicts with routing in partition "<name>"
ID:171102 Found conflicting placement requirements for partitions preserving placement
ID:171103 Found conflicting placement requirements for partitions preserving placement
ID:171104 Following nodes simultaneously request to be placed at "<name>"
ID:171105 Node "<name>" in partition "<name>"
ID:171106 Discarding previous placement for node "<name>" in partition "<name>"
ID:171107 Discarding previous placement and routing for node "<name>" in partition "<name>"
ID:171108 Preserving previous placement and routing for node "<name>" in partition "<name>"
ID:171109 Node "<name>" assigned to <text> due to <text>
ID:171110 Nodes could not be merged because their location constraints do not overlap
ID:171111 No atoms of type <name> may be placed in the region with lower left corner at <number>, <number> and upper right corner at <number>, <number>
ID:171112 No atoms of type <name> may be placed at location <location>
ID:171113 The design contains <number> blocks of type "<type>" but the selected device <device> does not support such blocks
ID:171114 This design attempted to replay Physical Synthesis operations on the <string> device that were recorded from the compile on the <string> device. This led to the circuit being unable to fit on the <string> device.
ID:171115 Routing Constraints File is specified in the Quartus Prime Settings File, but the feature is not supported in this device family. The file will be ignored.
ID:171116 Ignoring user specified Routing Constraints File (.rcf) -- Incremental Compile will preserve previous routing instead
ID:171117 Ignoring changes to Logic Lock region "<name>" because it only contains logic preserving a previous placement
ID:171118 Ignoring changes to Logic Lock regions containing logic preserving placement -- previous Logic Lock placement will be used
ID:171119 Ignored routing constraints for partitions preserving relative placement to moved Logic Lock regions
ID:171120 Ignored routing constraints for partition "<name>"
ID:171121 Fitter preparation operations ending: elapsed time is <time>
ID:171122 Fitter is preserving placement for <number> percent of the design from <number> Post-Fit partition(s) and <number> imported partition(s) of <number> total partition(s)
ID:171123 Timing-driven compilation is disabled - no timing information is available
ID:171124 Timing-driven compilation is disabled - timing performance will not be optimized
ID:171125 Separation design flow failed due to the following <number> errors
ID:171126 Region "<name>"
ID:171127 Assignment of security level "<number>" to signal "<name>"
ID:171128 Signal "<name>" <type> security level "<number>", but feeds node "<name>" which is in a region with a lower security level of "<number>"
ID:171129 Signal "<name>" has an LL_SIGNAL_SECURITY_LEVEL assignment to region "<name>", but is an output of a different region
ID:171130 Found multiple LL_SIGNAL_SECURITY_LEVEL assignments to names that refer to signal "<name>"
ID:171131 Found multiple conflicting LL_SIGNAL_SECURITY_LEVEL assignments to names that refer to signal "<name>"
ID:171132 Signal "<name>" is an output of secured region "<name>", and is missing a security routing interface assignment to route from region "<name>" to node "<name>" in secured region "<name>"
ID:171133 Signal "<name>" is an output of secured region "<name>", and is missing a security routing interface assignment to route from region "<name>" to unsecured logic node "<node>"
ID:171134 Signal "<name>" is an output of unsecured logic, and is missing a security routing interface assignment to route from unsecured logic to node "<node>" in secured region "<name>"
ID:171135 Security routing interface "<name>" does not abut one or two secured regions
ID:171136 Security routing interface "<name>" abuts more than two secured regions
ID:171137 Security routing interface "<name>" abuts two secured regions as well as one or more unsecured regions
ID:171138 Fencing for region "<name>" is violated by <number> other regions
ID:171139 Region "<name>" and region "<name>" overlap, but this overlap is not allowed due to one or more <name> settings.
ID:171140 Region "<name>" has its size set to Auto, but this functionality is not supported in the separation design flow
ID:171141 Region "<name>" has its state set to Floating, but this functionality is not supported in the separation design flow
ID:171142 Secured region "<name>" is less than eight units tall or eight units wide
ID:171143 Secured region "<name>" has nodes assigned to it that are neither pins nor design partitions
ID:171144 Partial reconfiguration region "<name>" has nodes assigned to it that are not design partitions.
ID:171145 Secured region "<name>" has <number> design partitions assigned to it, but only one partition is supported
ID:171146 Partial reconfiguration region "<name>" has <number> design partitions assigned to it, but only one partition is supported.
ID:171147 Secured region "<name>" has at least one hierarchy from the multi-hierarchy partition "<name>" assigned to it. Multi-hierarchy partitions may not be assigned to secured regions.
ID:171148 LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE assignment of signal "<name>" to region "<name>" was ignored
ID:171149 LL_SIGNAL_SECURITY_LEVEL assignment of signal "<name>" to region "<name>" was ignored
ID:171150 Found pin "<name>" in secured region "<name>", but that pin is not connected to a port in "Top"
ID:171151 Secured region "<name>" is invalid - assigning the top partition to a secured region is not allowed
ID:171152 Secured region "<name>" is invalid - assigning a non-leaf partition "<name>" to a secured region is not allowed
ID:171153 Found logic belonging to the same composite I/O group in multiple secured regions
ID:171154 Node "<name>" belongs to secured region "<name>"
ID:171155 Adding node "<name>" to secured region "<name>"
ID:171156 Found conflicting placement constraints for node "<name>" assigned to secured region "<name>"
ID:171157 Can't place node "<name>" in location or region "<name>" -- location is covered by Reserved Logic Lock region "<name>"
ID:171158 Node name: <name>. Implement the design block using soft logic by choosing the relevant option in the related megafunction
ID:171159 Node name: <name>
ID:171160 Found wire connection between input port "<name>" and output port "<name>" in partition "<name>"
ID:171161 Found wire connections through partitions -- inserting buffer nodes to ensure that the secured region assignments are honored
ID:171162 Signal "<name>" has <number> destinations in secured region "<name>" with different PAD_TO_CORE_DELAY settings. Only one setting is allowed.
ID:171163 Signal "<name>" has <number> destinations in unsecured logic with different PAD_TO_CORE_DELAY settings. Only one setting is allowed.
ID:171164 Previous placement for node "<name>" conflicts with current secured region assignments.
ID:171165 Node "<name>" assigned to secured region "<name>" has conflicting location constraint "<name>"
ID:171166 Ignoring secured region assignments - Engineering Change Order (ECO) changes are incompatible with secured regions in this release of the Quartus Prime software
ID:171167 Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
ID:171168 Compilation error may be caused by optimized reuse of previous compilation results for one or more partitions.
ID:171170 Previous compilation result cannot be reused because the device name "<name>" does not match current project device name "<name>"
ID:171171 Current release of the Quartus Prime software does not support routing preservation for the Stratix V device family
ID:171172 Detected conflicting assignments for the following nodes.
ID:171173 Node <name> from partition <name> cannot preserve previous placement at <name> and honor the location assignment to <name>
ID:171174 Potential clock network overuse. Nodes in regions on the device require more global signals than are available
ID:173000 Node or entity "<name>" assigned to undefined Logic Lock region "<name>"
ID:173001 Ignored back-annotated node locations in Logic Lock region <name>
ID:173002 Logic Lock region <name> is disabled for this compile
ID:173003 Detected <number> disabled Logic Lock regions
ID:175000 The Fitter is having trouble placing the periphery of the design, and is increasing its effort in an attempt to find a solution.
ID:175001 The Fitter cannot place <type>.
ID:175003 The <type> location is occupied
ID:175004 Sublocation of type <location_type> not found.
ID:175005 Could not find a location with: <text>
ID:175006 There is no routing connectivity between <name> and <name>
ID:175007 Could not find uncongested path between <name> and <name>
ID:175008 Location was not in the legal region
ID:175009 Encountered the following type of detailed legality issue:
ID:175010 Location failed detailed legality checks
ID:175011 Conflicting region assignments found for <name>
ID:175012 There are no <type> locations on the device that are compatible with the region constraints on the following logic.
ID:175013 The <type> is constrained to the region <name> due to related logic
ID:175014 Component must be in region from <name> due to <text>
ID:175015 The <type> is constrained to the <name> <text>
ID:175016 <name> is constrained by several assignments
ID:175017 Constrained to the <name> <text>
ID:175018 Excluded from the region <text>
ID:175019 Illegal constraint of <cell> to the location <location>
ID:175020 The Fitter cannot place logic <cell> in region <region>, to which it is constrained, because there are no valid locations in the region for logic of this type.
ID:175021 The <cell description> was placed in location <location>
ID:175022 The <cell description> could not be placed in any location to satisfy its connectivity requirements
ID:175023 <number> additional periphery cells could not be placed.
ID:175024 Fitter encountered difficulty placing periphery elements due to the complexity of your design.
ID:175025 <number of competing connections> connections are competing for <number of available resources> available routing resources:
ID:175026 Source: <source cell>
ID:175027 Destination: <dest cell>
ID:175028 The <cell description> name(s): <long name>
ID:175029 <cell>
ID:175030 Unroutable signal:
ID:175031 Competing signal:
ID:175032 <number of destinations> destinations including: <any destination cell>
ID:175033 The <type> was placed in location <location>
ID:175034 Assignment <number>: Region must be in <name> due to <text>
ID:176024 Can't place memory block type <type> in a location for memory block type <type>
ID:176025 Can't place memory block <name> in memory block type <type>
ID:176026 Can't place memory block <name> in any memory block type
ID:176027 Memory block type <type> does not support port <name> and/or port <name>
ID:176028 Memory block <name> has memory block type <type>, which is not supported in the selected device family
ID:176029 Memory block <name> uses a global signal on its clock-enable1 port. This is not allowed for this family.
ID:176030 Memory block type <type> does not support parameter <name>
ID:176031 Memory block type <type> does not support operation mode <name>
ID:176032 Memory block type <type> does not support parameter <name> in operation mode <name>
ID:176033 Memory block type <name> does not support a Memory Initialization File
ID:176034 Memory block type <type> does not support parameter(s) <name>
ID:176035 Memory block type <type> does not support operation mode <name>
ID:176036 Memory block type <type> does not support port <name> in operation mode <name>
ID:176037 Data port <name> width exceeds memory block type <type> limit of <number> bits
ID:176038 Address port <name> width exceeds memory block type <type> limit of <number> bits
ID:176039 RAM size configuration exceeded memory block type <type> limit of <number> bits
ID:176040 Memory block type <type> does not support port <name> in operating mode <name>
ID:176041 Can't place memory block type <type> with operation mode <name> and mixed data widths of <number> bits for read port and <number> bits for write port
ID:176042 Memory block <name> type <type> cannot be assigned to location of memory block type <type>
ID:176043 Memory block size configuration of <number> by <number> for byte enable port does not support port <name>
ID:176044 Memory block <name> cannot be assigned to a location of type <type>
ID:176046 Ignored duplicate Global Signal option for I/O cell <name> from node <name>
ID:176047 Ignored Global Signal option from source node <name> to destination node <name> -- source does not feed directly to destination
ID:176048 Ignored Global Signal option for node <name> -- node name does not match output signal names
ID:176049 Output signal <name> can be used with Global Signal option
ID:176050 Can't implement Global Signal option for node "<name>" that drives nodes that cannot change routing due to incremental compilation -- other nodes are not affected
ID:176051 Illegal location "<text>" specified in the global signal clkctrl location assignment for "<name>"
ID:176052 Can't create <text> named "<name>" because another node already has the same name
ID:176053 Node <name> is assigned to a secured region, but it is automatically promoted to use global routing
ID:176054 Skipped processing of the Auto Global Clock logic options because the separation design flow is on
ID:176055 Can't pack DDIO_in registers into differential I/O cells <name> and <name>
ID:176056 Failed to pack DDIO input registers into differential I/Os <name> and <name>
ID:176057 The Receiver, driven by I/O pin <name> at data rate <number> Mbps, exceeds maximum allowed data rate of <number> Mbps
ID:176058 The Transmitter driving I/O pin <name> at data rate <number> Mbps exceeds the maximum allowed data rate of <number> Mbps
ID:176059 The Receiver, driven by I/O pin <name> at data rate <number> Mbps, exceeds maximum allowed data rate of <number> Mbps for <name> input
ID:176060 The transmitter driving I/O pin <name> at data rate <number> Mbps exceeds the maximum allowed data rate of <number> Mbps for <name> output
ID:176061 I/O pin "<name>", driven by a transmitter at <number> Mbps, cannot be placed at slow-speed pin <name>. The maximum allowed data rate for slow-speed LVDS is <number> Mbps.
ID:176062 Transmitters driving the following I/O pins will have degraded duty cycle performance
ID:176063 The Transmitter driving I/O pin <name> at data rate <number> Mbps will have degraded duty cycle performance. Maximum data rate for non-degraded duty cycle performance is <number> Mbps.
ID:176064 Can't merge fast PLLs -- counter values of <number> and <number> for advanced parameter <name> do not match
ID:176065 Can't place LVDS input register <name>
ID:176066 Found two LVDS high registers instead of one!
ID:176067 Found two LVDS low registers instead of one!
ID:176068 LVDS DDIO input high register "<name>" has no corresponding LVDS DDIO input low register.
ID:176069 LVDS DDIO input low register "<name>" has no corresponding LVDS DDIO input high register.
ID:176070 Can't merge fast PLL <name> and fast PLL <name> -- merged fast PLL would drive <number> DPA channels, but a fast PLL can drive a maximum of <number> DPA channels when placed in center (based on the maximum distance allowed between DPA channels per bank and using both the top and bottom banks)
ID:176071 Can't merge fast PLL <name> and fast PLL <name> -- merged fast PLL would drive <number> DPA channels and exceed the maximum number of DPA channels allowed to be driven by a PLL per bank, which is <number>. Design can have up to two fast PLLs that exceed this value (by using center PLL locations and driving in both the top and bottom banks), and two such fast PLLs already exist.
ID:176072 Can't place one or more fast PLLs -- there are more than two fast PLLs that drive more than <number> DPA channels (the maximum number of DPA channels a PLL can drive per bank). However, only two PLL locations (one center PLL location on each side of the device) can drive more than that by feeding DPA channels in both the top and bottom quadrants.
ID:176073 Can't place fast PLL <name> -- the number of DPA channels driven by fast PLL <name>, <number>, exceeds the limit. The maximum distance between DPA channels per PLL per bank, <number>, should be satisfied so that a center PLL can drive a maximum of <number> DPA channels.
ID:176074 Can't place center fast PLL <name> and center fast PLL <name> because both center fast PLLs drive DPA channels within quadrant <name>
ID:176075 Can't merge fast PLL <name> and fast PLL <name> -- fast PLLs contain <number> unique DPA counters, but only one DPA counter is available on single fast PLL
ID:176076 Can't merge fast PLL <name> and fast PLL <name> -- fast PLLs contain <number> unique LVDS counters driving SCLKs, but only <number> LVDS counters driving SCLKs are available on single fast PLL
ID:176077 Can't merge PLL <name> and PLL <name> -- PLLs contain a total of <number> unique counters of which <number> drive external clock output pins, but only one is allowed
ID:176078 Can't merge fast PLL <name> and fast PLL <name>: fast PLLs contain a total of <number> unique counters, but only <number> counters are available on single fast PLL
ID:176079 Can't place flexible LVDS or differential I/O <name> in row <number> <name> side -- flexible LVDS or differential I/O is within the dynamic phase alignment group defined between rows <number> and <number>
ID:176080 Can't place Flexible LVDS or differential I/O <name> in row <number> <name> side -- minimum spacing must be <number> row(s) away from the I/O in row <number>
ID:176081 Transmitter SERDES groups overlap -- in rows (<number>-<number>) <name> side, fast PLL <name> group1 Y-range=(<number>-<number>) overlaps with fast PLL <name> group2 Y-range=(<number>-<number>)
ID:176082 DPA-mode SERDES groups overlap -- in rows (<number>-<number>) <name> side, fast PLL <name> group1 Y-range=(<number>-<number>) overlaps with fast PLL <name> group2 Y-range=(<number>-<number>)
ID:176083 Non-DPA-mode SERDES groups overlap -- in rows (<number>-<number>) <name> side, fast PLL <name> group1 Y-range=(<number>-<number>) overlaps with fast PLL <name> group2 Y-range=(<number>-<number>)
ID:176084 Non-DPA-mode and DPA-mode SERDES groups overlap and are driven by different PLLs -- in rows (<number>-<number>) <name> side, fast PLL <name> DPA-mode group1 Y-range=(<number>-<number>) overlaps with fast PLL <name> non-DPA-mode group2 Y-range=(<number>-<number>)
ID:176085 Non-DPA-mode and DPA-mode SERDES groups driven by the same fast PLL overlap -- in rows (<number>-<number>) <name> side, fast PLL <name> DPA-mode group1 Y-range=(<number>-<number>) overlaps with fast PLL <name> non-DPA-mode group2 Y-range=(<number>-<number>)
ID:176086 DPA-mode SERDES <name> of row <number> driven by fast PLL <name> is in an overlapping region
ID:176087 Non-DPA-mode SERDES <name> of row <number> driven by fast PLL <name> is in an overlapping region
ID:176088 DPA-mode SERDES groups driven by different PLLs don't have a buffer row separating them. The DPA channels driven by the fast PLL <name> have Y-range=(<number>-<number>). Those driven by the fast PLL <name> have Y-range=(<number>-<number>), both on the <name> side.
ID:176089 DPA-mode SERDES groups driven by different PLLs don't have a buffer row separating them. The DPA channels driven by the fast PLL <name> have Y-range=(<number>-<number>). Those driven by fast PLL <name> have Y-range=(<number>-<number>) -- both on the <name> side
ID:176090 LVDS channel placement rules are not satisfied for the device <name>
ID:176091 Can't place channel <name> in location <name> for the device <name> because the LVDS channel placement rules are not satisfied for this device
ID:176092 Can't place PLL <name> in PLL location <name> for the device <name>. The LVDS channel placement rules are not satisfied for this device.
ID:176093 Location assignments of LVDS DPA-mode <name> <name> do not obey the LVDS DPA rule. These DPA mode channels span rows <number> to <number> and have <number> SERDES separation between them. The maximum allowed SERDES separation between the DPA channels fed by a PLL is <number>.
ID:176094 Location assignment of LVDS DPA-mode <name> <name> is not within <number> from the fast driving PLL. These DPA-mode channels span rows <number> to <number>. However, they should lie between rows <number> to <number> (range of 25 SERDES from the PLL).
ID:176095 Fast PLL <name> drives more than the maximum number of DPA channels allowed to be driven by a PLL per bank, which is <number> (this is one more than the maximum distance allowed between DPA channels driven by a PLL per bank).
ID:176096 Both fast PLL <name> SCLKOUT ports must drive SERDES
ID:176097 Can't place differential I/O pin <name> with differential I/O standard <name> -- differential I/O pin <name> drives or is driven by a SERDES
ID:176098 Can't place differential I/O pin <name>
ID:176099 Synchronization register <name> for differential I/O pin <name> must be in same row and within <number> LABs of node
ID:176100 Non clock differential I/O pin <name> does not connect to any SERDES receiver or transmitter
ID:176101 Design has one or more non clock differential I/O pins that do not connect to SERDES receiver or transmitter. Changes to this connectivity may affect fitting results
ID:176102 Can't place negative differential pin <name> in location <name>
ID:176103 Can't place node <name> in location <name>
ID:176104 Can't merge PLL <name> and PLL <name>
ID:176105 Can't merge fast PLL <name> and fast PLL <name>
ID:176106 Fast PLL <name> and fast PLL <name> have different input signals for input port <name>
ID:176107 Input clock frequency for fast PLL "<name>" is not the same as the core clock frequency of fast PLL "<name>"
ID:176108 Input clock frequency for fast PLL <name> differs from input clock frequency of fast PLL <name>
ID:176109 Fast PLL <name> has <name> differential I/O standard, but LVDS PLL <name> has <name> differential I/O standard
ID:176110 PLLs <name> and <name> have different values for M counter or N counter or both
ID:176111 Fast PLL <name> has <number> Mbps differential I/O data rate, but LVDS PLL <name> has <number> Mbps differential I/O data rate
ID:176112 Fast PLL <name> and fast PLL <name> have incompatible location assignments
ID:176113 Fast PLL <name> and fast PLL <name> are being used in different modes
ID:176114 Can't merge fast PLL <name> and fast PLL <name> -- can't place merged PLL in current device
ID:176115 Counter <name> of fast PLL <name> has different configuration than counter <name> of fast PLL <name>
ID:176116 Fast PLL <name>, or one or more differential I/O nodes driven by fast PLL <name>, locked on <name> side, but <name> fast PLL location is on <name> side of device
ID:176117 Pin "<name>" has a pseudo-differential I/O standard but does not have its complement pin. Because the output enable of the buffer is in use, the Fitter will not create a negative pin without a complement output enable path.
ID:176118 Pin "<name>" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "<name>"
ID:176119 The values of the parameter "<name>" do not match for the PLL atoms
ID:176120 The values of the parameter "<name>" do not match for the PLL atoms <name> and PLL <name>
ID:176121 The value of the parameter "<name>" for the PLL atom <name> is <name>
ID:176122 Input clock frequency of PLL <name> differs from input clock frequency of PLL <name>
ID:176123 Input clock frequency for PLL "<name>" is not the same as the core clock frequency of PLL "<name>"
ID:176124 PLL <name> and PLL <name> have different input signals for input port <name>
ID:176125 The input ports of the PLL <name> and the PLL <name> are mismatched, preventing the PLLs to be merged
ID:176126 The location assignments of the PLL <name> and the PLL <name> are not compatible - hence these PLLs cannot be merged
ID:176127 The parameters of the PLL <name> and the PLL <name> do not have the same values - hence these PLLs cannot be merged
ID:176128 Assignment FORCE_MERGE_PLL took effect while trying to merge PLL <name> to PLL <name>
ID:176129 Assignment force_merge_pll_fanouts took effect to move all the fan-outs of the PLL clock <name> on to the PLL clock <name>
ID:176130 Both the PLL <name> and the PLL <name> are driving DLLs -- hence, these PLLs cannot be merged
ID:176131 Successfully merged LVDS PLL <name> and LVDS PLL <name>
ID:176132 Successfully merged PLL <name> and PLL <name>
ID:176133 Can't place differential I/O <name> pin <name> in location <name> -- differential I/O pin requires dedicated I/O SERDES, but location does not have differential I/O <name> SERDES available
ID:176134 Differential I/O node <name> assigned to pin <name>, but node must be assigned to pin <name> -- differential I/O node <name> is assigned to pin <name>
ID:176135 All differential I/O nodes driven by fast PLL <name> must be on same side of device
ID:176136 No differential I/O <type> nodes available in location <name> for node <name>
ID:176137 Can't place clock input pin <name> with I/O standard <name> and input frequency <number> in clock location <name> -- clock location cannot support input frequency greater than <number>
ID:176138 Can't place differential I/O pins and/or associated SERDES transmitters or receivers -- location assignments are illegal
ID:176139 Can't place differential I/O <name> pin <name> at a differential I/O <name> location <name> due to a polarity mismatch
ID:176140 Differential I/O <name> pin <name> is assigned to a <name> location <name>. However, you must assign the specified differential I/O pin to a differential <name> location
ID:176141 Non-transceiver I/O <name> pin <name> cannot be assigned to transceiver input pin at location <name>. Pin <name> is a dedicated transceiver <name> pin.
ID:176142 Project contains fast PLL driving <number> SERDES receivers, but target device can contain only <number> SERDES receivers per fast PLL
ID:176143 Project contains fast PLL driving <number> SERDES transmitters, but target device can contain only <number> SERDES transmitters per fast PLL
ID:176144 Project requires <number> SERDES receivers, but target device can contain only <number> SERDES receivers
ID:176145 Project requires <number> SERDES transmitters, but target device can contain only <number> SERDES transmitters
ID:176146 Project requires <number> fast PLLs, but target device can contain only <number> fast PLLs
ID:176147 Project requires <number> differential I/O-compatible pins, but target device can contain only <number> differential I/O-compatible pins
ID:176148 SERDES transmitter <name> drives <number> output pins, but must drive only one output pin
ID:176149 SERDES transmitter <name> must drive one output pin
ID:176150 Pin "<name>" with <name> I/O standard must be driven by the external clock output of an enhanced PLL
ID:176151 All outputs of SERDES receiver <name> should be synchronized to core clock
ID:176152 All data inputs of SERDES transmitter <name> must be synchronized to core clock
ID:176153 Fast PLL <name> drives DPA channels with <number> Mbps differential I/O data rate, but the target device <name> can support only <number> Mbps maximum differential I/O data rate for DPA channels
ID:176154 Fast PLL <name> drives non-DPA channels with <number> Mbps differential I/O data rate, but the target device <name> can support only <number> Mbps maximum differential I/O data rate for non-DPA channels
ID:176155 SERDES receiver <name> has a <number> Mbps differential I/O data rate, but the DPA must be enabled to achieve the specified data rate
ID:176156 Differential I/O pins <name> and <name> are driven by SERDES transmitter <name> with a <number> Mbps differential I/O data rate, but the specified differential I/O pins require the <name> assignment to indicate that an external receiver is using the DPA to support the specified rate
ID:176157 Fast PLL <name> has <number> Mbps differential I/O data rate, but a target device with a <name> speed grade can support only <number> Mbps minimum differential I/O data rate.
ID:176158 Fast PLL <name> has <number> Mbps differential I/O data rate, but target device with <name> speed grade can support only <number> Mbps maximum differential I/O data rate
ID:176159 Clock pin "<name>" driving <number> non-DPA RX PLLs cannot be compensated because device maximum possible is <number> PLL
ID:176160 Clock pin "<name>" drives non-DPA RX PLL <name>
ID:176161 Can't place input clock pin <name> driving fast PLL <name> in non-compensated I/O location <name> -- fast PLL drives at least one non-DPA-mode SERDES
ID:176162 Input clock pin of fast PLL <name>, which drives at least one non-DPA-mode SERDES, must be driven by a compensated input
ID:176163 Enable pin of fast PLL does not support differential I/O standards
ID:176164 Can't merge fast PLL <name> with fast PLL <name> -- merged fast PLL will use more than two clock signal feeding LVDS clock
ID:176165 Can't merge fast PLL <name> with fast PLL <name> -- merged fast PLL would use more than two differing data widths to drive dedicated SERDES transmitters or receivers
ID:176166 All dedicated SERDES transmitters or receivers driven by fast PLL <name> can have at most two differing data widths
ID:176167 Fast PLL <name> has input clock <name> with I/O standard <name>. This PLL drives differential I/O pins having I/O standard <name>. Clock and data I/O standards should be the same. This might happen if input clock drives two or more PLLs with different I/O standard on their differential I/O pins.
ID:176168 All differential I/O pins driven by fast PLL <name> must have same I/O standard
ID:176169 All differential I/O pins driven by fast PLL <name> must have same I/O standard
ID:176170 Can't place node "<name>" -- node has differential I/O pin pair inconsistencies
ID:176171 Input pin <name> drives <number> SERDES receivers, but must drive only one SERDES receiver
ID:176172 Can't place node "<name>" -- node is a differential I/O node
ID:176173 Can't place node "<name>" with differential I/O <name> in location (<number>,<number>,<number>) -- location does not support differential pin pair functionality
ID:176174 Input pin <name> must not have both <name> port and <name> port connected simultaneously
ID:176175 Input pin <name> has differential port connection to <name> which is not an input pin
ID:176176 Input pin <name> differential port connection must connect to complementary pin of input pin <name>
ID:176177 Input pin <name> <name> port connection must connect with only one complementary I/O pin
ID:176178 Input pin <name> must use differential I/O standard when using differential path connections -- automatically assigned <name> differential I/O standard to pin
ID:176179 Complement pins obtained for the bidirectional differential pin <name> via the input and output paths are different -- the configuration is invalid
ID:176180 GXB pin <name> should not have a pseudo-differential I/O standard
ID:176181 Complement bidirectional pins <name> and <name> with pseudo-differential I/O standard must use pseudo-differential output path
ID:176182 Bidirectional pin <name> with pseudo-differential I/O standard has the input buffer driving fan-outs. For such cases, the assignment "Allow Single-ended Buffer for Differential-XSTL Input" (XSTL_INPUT_ALLOW_SE_BUFFER) should be used instead of "Treat Bidirectional Pin as Output Pin" (TREAT_BIDIR_AS_OUTPUT).
ID:176183 Bidirectional pin <name> with a pseudo-differential I/O standard must use the output enable control signal on the output buffer
ID:176184 Bidirectional pins <name> and <name> with pseudo-differential I/O standard must either use a differential input path or have the output buffer's output enable (OE) set to VCC along with a proper assignment
ID:176185 Pin <name> must use pseudo-differential I/O standard. However, it is assigned <name> differential I/O standard
ID:176186 Pin <name> must use pseudo-differential I/O standard -- the Fitter will automatically assign <name> pseudo-differential I/O standard to pin
ID:176187 Transmitter or receiver pin <name> must use differential I/O standard -- Fitter will automatically assign <name> differential I/O standard to pin
ID:176188 Pin <name> driving clock input pin of fast PLL <name> does not have same I/O standard as other differential I/O pins driven by that PLL -- Fitter will automatically assign <name> differential I/O standard to pin
ID:176189 Corner fast PLL <name> drives SERDES <name> assigned to a different quadrant
ID:176190 Can't place more than <number> fast PLLs driving user-assigned LVDS channels in the same <name> quadrant
ID:176191 Fast PLL <name> drives LVDS channel <name> in quadrant <name>
ID:176192 Fast PLL <name> in location <name> cannot reach differential I/O pin <name> in location <name> using any differential I/O clock networks
ID:176193 Fast PLL <name> cannot reach differential I/O pin <name> in location <name> using any differential I/O clock networks
ID:176194 Differential I/O pins driven by fast PLL <name> have inconsistent location assignments
ID:176195 Can't place fast PLL <name> in fast PLL location <name> -- fast PLL requires <number> differential I/O <name> pins, but only <number> pin locations are available in fast PLL location <name>
ID:176196 Can't place fast PLL <name> in fast PLL location <name> -- not enough differential I/O pin locations available in fast PLL location <name>
ID:176197 Can't place fast PLL <name> in fast PLL location <name> -- no legal location for clock input pin <name> in target device
ID:176198 Can't place fast PLL <name> in fast PLL location <name> -- fast PLL, or one or more differential I/O pins driven by fast PLL, has location assignment incompatible with fast PLL
ID:176199 Can't place fast PLL <name> in fast PLL location <name> -- location does not support dynamic phase alignment
ID:176200 Can't place SERDES receiver or transmitter <name> with <number> Mbps data rate in location <name> -- location supports only <number> Mbps data rate
ID:176201 Can't place pin <name> with differential I/O standard -- no legal location available on target device
ID:176202 The differential I/O standard <name> cannot be used on the pin <name>, because the specified pin uses a tri-stated output buffer.
ID:176203 Differential I/O standard <name> cannot be used on the <name> pin <name>
ID:176204 Can't place pins due to device constraints
ID:176205 Can't place <number> pins with <name> I/O standard because Fitter has only <number> such free pins available for general purpose I/O placement
ID:176206 Constraint: <name>
ID:176207 Can't place pin <name> in I/O bank <name> due to the following reasons
ID:176208 Design has <number> pins, but Fitter can't place <number> pins
ID:176209 Can't place I/O pins -- can't place pins in any other I/O bank or other I/O banks have no pins available for general purpose I/O placement
ID:176210 Can't place pin <name> with I/O standard <name>, Termination setting <name>, and PCI I/O setting <name> due to device constraints
ID:176211 Number of I/O pins in group: <number> (<name> VREF, <name> VCCIO, <number> input, <number> output, <number> bidirectional)
ID:176212 I/O standards used: <name>
ID:176213 I/O bank number <name> <number or text> VREF pins and has <number or text> VCCIO pins. <number> total pin(s) used -- <number> pins available
ID:176214 Statistics of <name>
ID:176215 I/O bank details <before / after> I/O pin placement
ID:176218 Packed <number> registers into blocks of type <type>
ID:176219 No registers were packed into other blocks
ID:176220 Created <number> register duplicates
ID:176221 The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os.
ID:176222 Fitter will not automatically pack the registers into I/Os.
ID:176223 Can't pack register node <name> into non-LAB location
ID:176224 Constraint <name> contains no locations for registers
ID:176225 Can't pack node <name> to I/O pin
ID:176226 Can't pack register <name> and I/O node <name> -- one or both nodes have required options turned off
ID:176227 Can't pack node <name> and I/O node <name> -- no registers available for I/O cell
ID:176228 Can't pack node <name> and I/O node <name> -- I/O node is a dedicated I/O pin
ID:176230 Can't pack node "<name>" and I/O node "<name>" because the packing violates global signal capacity constraints of the region of the device occupied by the I/O node
ID:176231 Can't pack node "<name>" into an I/O node because the LCELL node has a location constraint to a region containing no I/O cells
ID:176232 Can't pack node "<name>" and I/O node "<name>" -- resulting I/O placement would violate pin assignment rules
ID:176233 Starting register packing
ID:176234 Starting register packing
ID:176235 Finished register packing
ID:176236 Started Fast Input/Output/OE register processing
ID:176237 Finished Fast Input/Output/OE register processing
ID:176238 Start inferring scan chains for DSP blocks
ID:176239 Inferring scan chains for DSP blocks is complete
ID:176240 Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density
ID:176241 Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks
ID:176242 Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
ID:176243 Finished moving registers into I/O cells, LUTs, and RAM blocks
ID:176244 Moving registers into LUTs to improve timing and density
ID:176245 Finished moving registers into LUTs: elapsed time is <time>
ID:176246 Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
ID:176247 Finished moving registers into I/O cells, DSP blocks, and RAM blocks
ID:176248 Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
ID:176249 Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
ID:176250 Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
ID:176251 Ignoring some wildcard destinations of fast I/O register assignments
ID:176252 Wildcard assignment "<name>=<value>" to "<wildcard>" matches multiple destination nodes -- some destinations are not valid targets for this assignment
ID:176253 Node "<name>" assigned to <text> due to <text>
ID:176254 Can't pack node <name> and I/O node <name> -- asynchronous clear signal violation
ID:176255 Can't pack node <name> and I/O node <name> -- synchronous clear signal violation
ID:176256 Can't pack node <name> and I/O node <name> -- clock signal violation
ID:176257 Can't pack node <name> and I/O node <name> -- clock enable signal violation
ID:176258 Can't pack node <name> and I/O node <name> -- register is in QFBK mode
ID:176260 Can't pack node <name> and I/O node <name> -- one node must be a logic cell and one must be an I/O cell
ID:176261 Can't pack node <name> and I/O cell <name> -- two distinct delay chain logic options on the combinational output port on I/O cell
ID:176262 Can't pack node <name> and I/O cell <name> -- connection from the combinational output port on the I/O cell to the logic cell is assigned the Decrease Input Delay to Internal Cells delay chain logic option
ID:176263 Illegal location assignment -- I/O cells in device do not have registers
ID:176264 Can't pack I/O cell <name> -- no fan-out from combinational output port
ID:176265 Can't pack register <name> -- no packable connection to a pin
ID:176266 Can't pack register <name> -- no packable connection to input pin
ID:176267 Can't pack node <name> -- no packable connection between output pin and register
ID:176268 Can't pack node "<name>" -- no packable connection between output pin (output enable) and register
ID:176269 Can't pack node "<name>" -- pin "<name>" is a DQ input and packing the register into the I/O cell reduces the DQ timing margin
ID:176270 Can't pack node "<name>" and I/O cell <name> -- packing the node into the I/O cell may cause incorrect processing
ID:176271 Can't pack node "<name>" and I/O cell <name> -- packing requires modification of inverter node
ID:176272 Can't pack node "<name>" and I/O cell <name>. The node and I/O cell are connected across a Design Partition boundary.
ID:176273 Performing register packing on registers with non-logic cell location assignments
ID:176274 Completed register packing on registers with non-logic cell location assignments
ID:176275 Packing node <name> and I/O cell <name> -- removed delay chain option between node and I/O cell
ID:176276 Can't pack Register node "<name>" into I/O pin "<name>". Can't place registered I/O pin in the same location as a differential I/O pin.
ID:176277 Can't pack register node "<name>" into I/O pin "<name>". The node "<name>" is used as a register for a MLAB cell.
ID:176278 Can't pack register node "<name>" into I/O pin "<name>". The node "<name>" cannot simultaneously use synchronous and asynchronous presets.
ID:176279 Can't pack register node "<name>" into I/O pin "<name>". The node "<name>" cannot simultaneously use clear and load signals.
ID:176283 Can't place <name> pin <name> in dedicated location (<number>, <number>, <number>)
ID:176284 Can't place remote update block <name> in dedicated location (<number>, <number>, <number>)
ID:176285 Can't place CRC block <name> in dedicated location (<number>, <number>, <number>)
ID:176286 Found <number> <type> blocks in design -- only one <type> block is allowed
ID:176287 Real-time CRC ERROR_CHECK_FREQUENCY_DIVISOR value (<number>) in design does not match value (<number>) in the Quartus Prime Settings File
ID:176288 Can't place <name> block because target device does not support block <name>
ID:176289 Can't use active serial memory interface block -- configuration scheme is not Active Serial
ID:176290 Can't place <number> pins with I/O standards supported only on horizontal I/O pins -- only <number> horizontal I/O pins available for general purpose I/O placement
ID:176291 Can't place <number> pins with I/O standards supported only on vertical I/O pins -- only <number> free vertical I/O pins pins available for general purpose I/O placement
ID:176292 Ignored Power-Up Level option on the following nodes -- nodes are set to power up low
ID:176293 Logic cell <name> will power up low
ID:176294 Input registers in I/O cell <name> will power up low
ID:176295 Output registers in I/O cell <name> will power up low
ID:176296 Output enable registers in I/O cell <name> will power up low
ID:176297 Ignored Power-Up Level option on the following nodes
ID:176298 Logic cell <name> will not match the power-up level <type> assignment
ID:176300 Illegal input port <name> found in update block in local update configuration mode
ID:176301 There are <number> JTAG blocks in the design, which exceeds the number of JTAG block locations available on the device (<number>)
ID:176302 Can't place JTAG input pin <name> in location (<number>, <number>, <number>)
ID:176303 Can't place JTAG block <name> in location (<number>, <number>, <number>)
ID:176304 JTAG block <name> does not support input port <name>
ID:176305 Source of port <name> in JTAG block <name> must be pin
ID:176306 Connection to <name> port of node <name> has a different global level than the original compilation
ID:176307 Can't place I/O pin <name> in non-bonded location <name>
ID:176309 Can't place pin <name> at assigned pin location <name> (<name>) because location is JTAG pin location
ID:176310 Can't place multiple pins assigned to pin location <name> (<name>)
ID:176311 Pin <name> is assigned to pin location <name> (<name>)
ID:176312 Can't place pin <name> at assigned pin location <name> (<name>) because that location is a dedicated PLL input pin location
ID:176313 Can't place pin "<name>" at assigned pin location <name> (<name>) because location is a dedicated GXB receiver input pin location but pin "<name>" does not feed the datain input port of a GXB receiver
ID:176314 Can't place pin "<name>" at assigned pin location <name> (<name>) because location must feed a GXB transmitter PLL clock input port or a GXB receiver cruclk input port
ID:176315 Can't place pin "<name>" at assigned pin location <name> (<name>) because location is a dedicated GXB transmitter output pin location but pin "<name>" is not fed by the dataout output port of a GXB transmitter
ID:176316 I/O assignment analysis allows pin "<name>" assigned to dedicated GXB receiver input pin location <name> (<name>) to not feed the datain input port of a GXB receiver. However, to successfully run the Fitter, pin "<name>" must feed the datain input port of a GXB receiver.
ID:176317 I/O assignment analysis allows pin "<name>" assigned to dedicated GXB Reference clock pin location <name> (<name>) to not feed the clock input port of a GXB transmitter PLL or the cruclk input port of a GXB receiver. However, to successfully run the Fitter, pin "<name>" must feed the clock input port of a GXB transmitter PLL or the cruclk input port of a GXB receiver.
ID:176318 I/O assignment analysis allows pin "<name>" assigned to dedicated GXB transmitter output pin location <name> (<name>) to not be fed by the dataout output port of a GXB transmitter. However, pin "<name>" must be fed by the dataout output port of a GXB transmitter for Fitter to run successfully.
ID:176319 Changed Global Signal option from <value> to <value> for signal <name>
ID:176320 Ignored <text> setting for node <name> -- setting is not supported by target device
ID:176321 Illegal Global Signal option assignment for Clock Control Block <name> -- destination nodes cannot have a Global Signal option of OFF
ID:176322 Clock Control Block <name> uses the clkselect port, but only one inclk port is used
ID:176323 Changed the clock type of Clock Control Block <name> from <type> to <type> to match the Global Signal option assignment of the source or destination node <name> for signal <name>
ID:176324 Changed the clock type of Clock Control Block <name> from <type> to <type> to match the Global Signal option assignment of the source or destination node <name> for signal <name>
ID:176325 Port name <name> with index <number> of Clock Control Block <name> has a Global Signal option assignment of <name> from signal <name> that does not match Global Signal option assignment <name>
ID:176326 Clock Control Block <name> has a Global Signal option assignment of <name> to the destination signal <name> that does not match the Global Signal option assignment of <name>
ID:176327 Ignored Global Signal option assignment from source signal <name> to destination signal <name> -- destination cannot use global signals
ID:176328 Ignored Global Signal option assignment for source signal <name> to some wild card destinations -- destination nodes cannot use global signals
ID:176329 Illegal connection from Clock Control Block <name> to destination node <name> -- destination node cannot be driven by global clock signals
ID:176330 Illegal connection from Clock Control Block <name> to some wild card destinations -- destination nodes cannot be driven by global signals
ID:176331 Ignored Global Signal option of <name> for Clock Control Block <name> with port name <name> and index <number> -- option must have value of <name>
ID:176332 Ignored Global Signal option of <name> for Clock Control Block <name> to the destination node <name> -- option must have a value of <name>
ID:176333 Limited to <number> messages for node "<name>"
ID:176334 I/O cell <name> is fed by two non-global clocks, but at least one clock must be a global clock or a regional clock
ID:176335 Node <name> is used by the I/O
ID:176336 Register <name> is driven by this clock
ID:176337 Cell <name> fed by <number> non-global control signals -- only <number> control signals may be non-global
ID:176338 Node "<name>" is used as the input clock of DDIO output registers but does not use global clock -- timing may not be met
ID:176339 Node "<name>" is used as the input clock of DDIO output registers but does not use global clock
ID:176340 Node "<name>" is a DDIO output register
ID:176341 The coreclk input of node <name> and <name> cannot both be non-global
ID:176344 Can't support CPRI Protocol in C5 speed grade devices
ID:176345 Worst-case clock duty cycle of a GXB receiver channel clkout and a GXB transmitter channel clkout in CPRI Protocol can be 60/40 percent
ID:176346 Design requires <number> clock signal(s) of type <type> but device can contain only <number> clock signals of type <type>
ID:176347 Design requires <number> clock signal(s) of type <type> but the project settings allow only <number> clock signals of type <type>
ID:176348 Design requires <number> clock signal(s) of type <type> in region (<number>, <number>), (<number>, <number>) but the selected device can contain only <number> clock signal(s) of type <type> in region
ID:176349 Node <name> uses <number> clock signal(s) of type <type>
ID:176350 Can't fit fan-out of node <name> into a single clock region
ID:176351 Can't fit <number> clock pins in the device -- only <number> clock pins are available
ID:176352 Promoted node <name> <string>
ID:176353 Automatically promoted node <name> <string>
ID:176354 Promoted <name> to use location or clock signal <string>
ID:176355 Automatically promoted <name> to use location or clock signal <string>
ID:176356 Following destination nodes may be non-global or may not use global or regional clocks
ID:176357 Destination node <name>
ID:176358 Non-global destination nodes limited to <number> nodes
ID:176359 Can't assign node "<name>" to any location
ID:176360 Can't assign node "<name>" to location <name>
ID:176361 Can't assign node "<name>" to use inclk[<number>] port at location <name> -- node uses inclk[<number>] port of Clock Control Block <name>
ID:176362 Can't assign node "<name>" to use inclk[<number>] port at location <name> -- node uses inclk[<number>] port of clock select Block <name>
ID:176363 Can't use clock type <name> at location <name> for clock control block or source node <name> with clock type <name> -- clock types do not match
ID:176364 Can't use clock region <string> from (<number>, <number>) to (<number>, <number>) for Clock Control Block or source node <name> with clock type <string>-- clock types do not match
ID:176365 Can't place node <name> at location <text> -- node uses Clock Control Block inclk port(s) <name> but the location can only use Clock Control Block inclk port(s) <name>
ID:176366 Node "<name>" uses inclk port <number> of Clock Control Block <name>
ID:176367 Can't assign fan-out of node "<name>" to the <text> region from (<number>, <number>) to (<number>, <number>)
ID:176368 Limited to <number> fan-out
ID:176369 Can't place node <name> -- node requires <number> <type> signals, which exceeds maximum of <number> signals
ID:176370 Assigned fan-out of node <name> to <type> region from (<number>, <number>) to (<number>, <number>)
ID:176372 Can't place node <name> at location <name> -- location of node conflicts with the following Clock Control Block(s)
ID:176373 Clock Control Block <name> can be placed at the following location(s)
ID:176374 Location <text> may be used for the Clock Control Block
ID:176375 Can't place Clock Control Block <name> in location <name> -- location conflicts with source nodes of inclk ports
ID:176376 Placed node <name> in location <name>
ID:176377 Clock Control Block can be placed at location <name>
ID:176378 Can't place node <name> at <text> because it potentially conflicts with the location constraints of Clock Control Block <name> and its inclk sources
ID:176379 Clock Control Block <name> has location constraint <text>
ID:176380 Can't place Clock Control Block <name> at location <text> due to possible conflicts with the location constraints of the inclk source(s)
ID:176381 Source of inclk[<number>] is node <name> with location constraints <text>
ID:176382 Design has <number> nodes that need to be assigned to a clock pin or PLL, but only <number> locations are available
ID:176383 Location <name> is legal for placement of nodes that need to be assigned to a clock pin or PLL
ID:176384 Node "<name>" cannot be placed at the following locations
ID:176385 Can't place Clock Control Block <name> at location <string> because it does not support the enable input port
ID:176386 Cannot place Clock Control Block <name> at location <string>, because it does not support the enaout output port
ID:176387 Can't place <name> at location <string> because it uses a Clock Control Block with dynamic clock select
ID:176388 Can't place <name> at location <string> because it uses a Clock Delay Control
ID:176389 Following <number> nodes require <number> Clock Control Block(s) of type <text>, but only <number> are available from the locations the nodes are assigned to
ID:176390 Node "<name>" placed in <text> needs <number> Clock Control Block(s)
ID:176391 Clock Control Block <text> can be used
ID:176393 Can't place <name> in <text> because the location is required for <name>
ID:176394 Can't fit <number> PLLs in the device -- only <number> PLLs are available
ID:176396 Node "<name>" needs to be assigned to one of the above locations
ID:176397 PLL <name> requires <number> external clock output pins using a single-ended I/O standard, but the maximum that are supported by any PLL is <number>
ID:176398 PLL <name> requires <number> external clock output pins using a differential I/O standard, but the maximum that are supported by any PLL is <number>
ID:176399 Following nodes use the same resource <text>
ID:176401 Can't place PLL <name> in location <name> -- input clocks of PLL driven by <number> clock signals -- exceeds maximum of <number> global signal(s)
ID:176403 Following nodes drive the PLL "<name>" placed at location <text> via the cascade connection, but only one can use this connection
ID:176404 Node "<name>" is currently placed at location <text> with a Global Signal type of <text>
ID:176405 Node drives Clock Control Block <name>
ID:176406 Following PLLs have a fixed counter order and cannot be changed; they may have forced some signals to use the same Clock Control Block
ID:176407 PLL <name> has fixed counter order
ID:176409 PLL clock output <name> cannot use counter <string> because it cannot drive the <string> input of LVDS receiver or transmitter <name>
ID:176410 Node <name> placed at location <string> cannot use the <string> region from (<number>, <number>) to (<number>, <number>) because it is not fully contained in the region or its sub-regions
ID:176411 Node <name> placed at location <string> cannot use the <string> region from (<number>, <number>) to (<number>, <number>) because its <text> interface is at (<number>, <number>)
ID:176413 Cannot place Clock Control Block <name> at location <string>, because it does not support the value of "<string>" for the ENA_REGISTER_MODE parameter
ID:176414 Can't place node <name> in <text> due to I/O or LAB clock region constraints
ID:176415 Location <text> does not support the clock type <text> that is used by "<name>"
ID:176416 Can't assign node "<name>" to location <text> because it is driven by node "<name>" assigned to location <text> that uses the <text> region from (<number>, <number>) to (<number>, <number>)
ID:176417 Cannot insert node <name> in region (<number>, <number>), (<number>, <number>) because it exceeds the total resources available in the region
ID:176418 More than <number> resources of type <type> are required
ID:176420 One or more violations of the register hold time due to clock skew have been identified
ID:176421 Minimum required interconnect delay between <name> and <name> is <number> ps, the Fitter inserted only <number> ps. The Fitter used <name> to establish connection.
ID:176422 Ignored Input Delay from Pin to Internal Cells logic option assignment on node <name> because node <name> and node <name> are fed by the same delay chain from input or bidirectional pin <name> but have different assignment values
ID:176423 Changed Input Delay from Pin to Internal Cells option assignment on pin <name> from <number> to <number> -- valid range is from <number> to <number>
ID:176424 Too many Input Delay from Pin to Internal Cells logic option assignments to input pin <name> and its fan-outs because pin uses input register -- honoring only one assignment (setting = <number>)
ID:176425 Ignored Input Delay from Pin to Internal Cells logic option assignment (setting = <number>) to input or bidirectional pin <name> because all of its fan-outs already have assignments of a different delay value (setting = <number>)
ID:176426 Ignored Input Delay from Pin to Internal Cells option assignment (setting = <number>) to input or bidirectional pin <name> -- all fan-out already have assignments of a different delay value or are fed by the pin through global or regional clocks
ID:176427 Ignored Input Delay from Pin to Internal Cells logic option assignment to input or bidirectional pin <name> because pin is a DQS I/O pin
ID:176428 Ignored Input Delay from Pin to Internal Cells logic option assignment to input or bidirectional pin <name> because pin fans out to SERDES receiver <name>
ID:176429 Ignored Input Delay from Pin to Internal Cells logic option assignment on input or bidirectional pin <name> because pin fans out to PLL <name>
ID:176430 Ignored Input Delay from Pin to Internal Cells logic option assignment to input or bidirectional pin <name> because pin assigned to VREF pad <name>
ID:176431 Too many Input Delay from Pin to Internal Cells logic option assignments to input pin <name> and its fan-outs -- honoring only <number> assignment(s) (ignored setting = <number>)
ID:176432 Ignored Input Delay from Pin to Internal Cells logic option assignment to input or bidirectional pin <name> because pin is assigned to global clock <name>
ID:176433 Ignored Decrease Input Delay to Internal Cells logic option assignment to input or bidirectional pin "<name>" because pin is assigned to global clock "<name>" and has no non-global destinations
ID:176434 Ignored Input Delay from Pin to Internal Cells logic option assignment (setting = <number>) from input or bidirectional pin <name> to destination logic cell <name> because it is a global destination
ID:176435 Ignored Input Delay from Pin to Internal Cells logic option assignment (setting = <number>) from input or bidirectional pin <name> to destination logic cell <name> because the routing path does not go through a delay chain
ID:176436 Can't set option <name> to <value> -- option is not used on pin <number>
ID:176437 Can't set option <name> to <number> -- option is not used in pin <name> -- changed to <number>
ID:176438 Can't set option <name> on pin <name> to <number> -- legal setting range is from <number> to <number>
ID:176439 Can't set option <type> on pin <name> to <number> -- legal setting range is from <number> to <number> -- changed to the default <number>
ID:176440 Auto delay chain can't change the delay chain setting on I/O pin <name> since it's a PLL compensated pin
ID:176441 The I/O pin <name> cannot meet the timing constraints due to conflicting requirements. The I/O pin is a PLL compensated I/O, but the setup/hold requirements are in conflict with the source PLL mode(source synchronous or ZDB).
ID:176446 There are <number> nodes that use <text> located at (<number>, <number>), but only one is allowed
ID:176447 Node <name> drives the following nodes
ID:176448 Node <name> uses the <text> input at index <number> and placed at <text>
ID:176449 Merged following Clock Control Blocks
ID:176450 Merged Clock Control Block <name> with <name>
ID:176451 Can't merge Clock Control Blocks <name> and <name> -- <name> uses more than one input clock
ID:176452 Can't merge Clock Control Blocks <name> and <name> -- different clock enable signals
ID:176453 Can't merge Clock Control Blocks <name> and <name> -- <name> feeds logic that is not <name>
ID:176454 Can't merge Clock Control Blocks <name> (clock type <name>) and <name> (clock type <name>) -- different clock types
ID:176455 Can't merge Clock Control Blocks <name> and <name> -- incompatible location assignments
ID:176456 Can't merge Clock Control Blocks <name> and <name> -- different values (<text> vs <text>) for the ena_register_mode parameter
ID:176457 Unable to merge Clock Control Blocks <name> and <name> because of the different values (<text> vs <text>) for the <text> parameter.
ID:176458 Fitter merged <number> physical RAM blocks that contain multiple logical RAM slices into a single location
ID:176459 Following physical RAM blocks contain multiple logical RAM slices
ID:176460 Physical RAM block <name> contains the following logical RAM slices
ID:176461 RAM slice: <name>
ID:176462 Carry chain starts with node "<name>"
ID:176463 Node "<name>"
ID:176464 Pin location <name>
ID:176465 Data width of memory block <name> is wider than the maximum data width of <number> allowed in device
ID:176466 Following DDIO <name> nodes are constrained by the Fitter to improve DDIO timing
ID:176467 Node "<name>" is constrained to location <name> to improve DDIO timing
ID:176468 Following DDIO <name> nodes could not be constrained by the Fitter to improve DDIO timing
ID:176469 DDIO capture registers for pin "<name>" could not be constrained to the chip periphery
ID:176470 DDIO node "<name>" could not be constrained to the chip periphery at <name> because <text>
ID:176471 Following DDIO <name> nodes could not be placed by the Fitter
ID:176472 DDIO Node "<name>" could not be constrained to a legal location
ID:176473 DDIO_OUTPUT_REGISTER_DISTANCE ACF setting is assigned an illegal value of <number>. Legal values are 1 and 2.
ID:176476 Memory block type <type> is not enabled because the option <name> is OFF or the option <name> is 0
ID:176477 Can't place all delay locked loop (DLLs) or DQS I/O pins
ID:176478 DQS I/O pin "<name>" feeds <number> DQ I/O pins -- exceeds the maximum allowed fan-out of <number> DQ I/O pins
ID:176479 Design requires <number> delay locked loop (DLLs) -- device can contain maximum of <number> DLLs
ID:176480 Design requires <number> DQS I/O pins -- device can contain maximum of <number> DQS I/O pins
ID:176481 Design requires <number> nDQS I/O pins -- device can contain a maximum of only <number> nDQS I/O pins
ID:176483 Delayctrlout port of DLL "<name>" feeds <number> DQS I/O pins -- maximum of <number> DQS I/O pins can be fed by DLL through delayctrlout port
ID:176484 Delayctrlout port of DLL "<name>" feeds <number> DQS I/O pins that feed <number> DQ I/O pins. A maximum of <number> DQ I/O pins can be associated with single DLL.
ID:176485 DQS I/O pins fed by delayctrlout port of DLL "<name>" require minimum of <number> DQSMUX resources to route the DQSBUS signals to DQ I/O pins -- maximum of <number> DQSMUX resources available to DQS I/O pins
ID:176486 Design requires <number> x4 DQS I/O pins -- selected device cannot contain more than <number> x4 DQS I/O pins
ID:176487 Design requires <number> x9 DQS I/O pins -- selected device cannot contain more than <number> x9 DQS I/O pins
ID:176488 Design requires <number> x18 DQS I/O pins -- selected device cannot contain more than <number> x18 DQS I/O pins
ID:176489 Design requires <number> x36 DQS I/O pins -- selected device cannot contain more than <number> x36 DQS I/O pins
ID:176490 Design requires <number> DQ I/O pins -- selected device can contain maximum of <number> DQ I/O pins
ID:176491 Design requires minimum of <number> DQSMUX resources to route the DQSBUS signals from DQS I/O pins to DQ I/O pins -- selected device contains only <number> DQSMUX resources
ID:176492 DQS I/O pin "<number>" feeds <number> DQ I/O pins -- maximum of <number> DQ I/O pins can be fed by a single DQS I/O pin
ID:176493 Can't place <name> I/O pin "<name>" in location <name> -- location is already occupied by <name> I/O <name> pin
ID:176494 Can't place <name> I/O "<name>" in location <name> -- location has constraint <name> due to <name>
ID:176495 Can't place <name> I/O pin "<name>" at location <name>
ID:176496 Can't place <name> I/O "<name>" in location <name> -- can't place associated DQS I/O pin "<name>" in a location that feeds this location
ID:176497 Can't place DQ I/O "<name>" in location <name> -- can't route DQSBUS signal from associated DQS I/O "<name>" pin to this location because the DQSMUX resource is already occupied by a DQS I/O pin that is not associated with this DQ I/O pin
ID:176498 Can't place DQS I/O pin "<name>" in location <name> -- can't place associated DQ I/Os or nDQS I/O in a location that can be fed from the DQS I/O pin location
ID:176499 Can't place DQS I/O pin "<name>" in location <name> -- DQS I/O pin requires DQSMUX resource location that is occupied by a different DQS I/O pin
ID:176500 Can't place nDQS I/O "<name>" in location <name> -- nDQS I/O pin requires DQSMUX resource location that is occupied by a DQS I/O pin not associated with this nDQS I/O pin
ID:176501 Can't place DQS I/O pin "<name>" in location <name> -- can't place one or more fan-out DQ I/O pins
ID:176502 Can't place DQS I/O pin <name>
ID:176503 Can't place DQS I/O pin "<name>" in location <name> -- location is already occupied by DQS I/O pin "<name>"
ID:176504 Can't place <name> "<name>" to location "<name>"
ID:176505 Can't place DQS I/O pin "<name>" in location <name> -- DQS I/O pin location can only fan-out to <number> DQ I/O pins but DQS I/O pin fans-out to <number> DQ I/O pins
ID:176506 Can't place DLL "<name>" in location <name>
ID:176507 Can't place DLL "<name>" in location <name> -- can't also place reference clock I/O "<name>"
ID:176508 Can't place DQS I/O pin "<name>" in location <name> -- can't also place nDQS I/O pin "<name>" that feeds DQS I/O pin
ID:176509 Can't place DLL "<name>" in location <name> -- DLL "<name>" is already assigned to that location
ID:176510 Can't place DLL "<name>" in location <name> -- DLL has location constraint <name> due to source <name>
ID:176511 Can't place DLL "<name>" in location <name> -- can't also place DLL source PLL "<name>" in location <name> because it has location constraint <name> due to source <name>
ID:176512 Can't place PLL "<name>" in location <name> -- PLL feeds the clk port of DLL "<name>" but location cannot feed the clk port of a DLL
ID:176513 Can't place <type> I/O pin "<name>" in location <name> -- location is not legal for a DQS I/O, nDQS I/O, DQ I/O, or DLL inclk I/O pin
ID:176514 Can't place <type> I/O pin "<name>" in location <name> -- location is not legal for a <type> I/O pin
ID:176515 Can't place <type> I/O pin "<name>" in location <name> -- placed DLL "<name>" fed by I/O pin in location <name>
ID:176516 Can't place <type> I/O "<name>" in location <name> -- location is not legal for a DLL inclk I/O pin
ID:176517 Placed DLL "<name>" in location <name> due to location constraints
ID:176518 DLL "<name>" with delay buffer mode <name> and delay chain length <number> is not legal
ID:176519 Placed PLL "<name>" in location <name> PLL feeds the clk port of DLL "<name>"
ID:176520 Placed PLL "<name>" in region "<name>" -- PLL feeds the clk port of DLL "<name>"
ID:176521 Can't place DLL "<name>" due to incompatible location assignments
ID:176522 I/O "<name>" of type <type> has location assignment <name> due to source <name>
ID:176523 PLL "<name>" has location assignment <name> due to source <name>
ID:176524 DLL "<name>" has location assignment <name> due to source <name>
ID:176525 DQS I/O pin "<name>" assigned I/O standard <name> -- nDQS I/O pin "<name>" fed by DQS I/O pin assigned I/O standard <name> -- both pins must be assigned same I/O standard
ID:176526 DQS I/O pin "<name>" assigned differential I/O standard <name> -- DQS I/O pin does not feed a nDQS I/O pin. A DQS I/O pin that does not feed a nDQS I/O pin cannot have a differential I/O standard assignment
ID:176527 DQ I/O pins fed by DQS I/O pin "<name>" assigned different I/O standards -- it is recommended that all DQ I/O pins fed by the same DQS I/O pin have the same I/O standard
ID:176528 I/O pin "<name>" of type <name> has I/O standard assignment of <name>
ID:176529 DQ I/O pins fed by DQS I/O pin "<name>" have different Output Enables -- all DQ I/O pins fed by the same DQS I/O pin should have the same Output Enable signal
ID:176530 I/O pin "<name>" of type <name> has Output Enable signal <name>
ID:176531 DQ I/O pins fed by DQS I/O pin "<name>" have different OUTCLKs -- all DQ I/O pins fed by the same DQS I/O pin should have the same OUTCLK signal
ID:176532 I/O pin "<name>" of type <name> has OUTCLK signal <name>
ID:176533 DLL "<name>" (in low jitter mode) requires up to <number> clock cycles to generate correct delay control settings on system power-up
ID:176534 DLL "<name>" (in fast lock mode) requires up to <number> clock cycles to generate correct delay control settings on system power-up
ID:176539 Input clock frequency <name> of DLL "<name>" should be in the frequency range of <name> to <name>
ID:176540 PLL <name> feeds the clk ports of DLLs <name> and <name> but a PLL cannot feed the clk port of more than 1 DLL
ID:176541 <name> I/O pin <name> feeds the clk ports of DLLs <name> and <name> but an I/O pin cannot feed the clk port of more than 1 DLL
ID:176542 Design contains <number> <name>
ID:176543 Delayctrlin input port of DQS I/O <name> is driven by more than one DLL or from both DLL and non-DLL signals
ID:176544 Delayctrlin[<number>] input port of DQS I/O <name> is driven by DLL <name>
ID:176545 Delayctrlin[<number>] input port of DQS I/O <name> is driven by node <name>
ID:176548 DDIO pin "<name>" is placed at location "<name>", but this dedicated clock I/O location cannot directly feed the data-in ports of the DDIO input registers, and consequently, this DDIO input circuit may not meet timing.
ID:176549 Two registers, "<name>" and "<name>", will not be used to create a differential port connection between the non-LVDS I/O pin "<name>" and its complement pin
ID:176550 The JTAG pin "<name>" is defined as virtual I/O pin
ID:176551 Destination of port <name> in JTAG block <name> must be a pin
ID:176553 Can't place <name> PLL "<name>" -- PLL location incompatible with PLL
ID:176554 Can't place <name> PLL "<name>" -- I/O pin <name> (port type <name> of the PLL) is assigned to a location which is not connected to port type <name> of any PLL on the device
ID:176555 Project requires <number> PLLs, but the target device can contain only <number> PLLs
ID:176556 Project requires <number> <name> PLLs, but the target device has only <number> <name> PLLs
ID:176557 Can't place <name> PLL "<name>" in target device due to device constraints
ID:176558 Can't place <name> PLL "<name>" in PLL location <name> due to device constraints
ID:176559 Can't place <name> PLL "<name>" in PLL location <name> because I/O cell "<name>" cannot be placed in I/O pin <name> (port type <name> of the PLL)
ID:176560 PLL input clock "<name>" feeds multiple PLLs but I/O pin "<name>" cannot use global or regional clock to feed multiple PLLs
ID:176561 Can't place <name> PLL "<name>" in PLL location <name> because location is already occupied by node "<name>"
ID:176562 Can't place <name> PLL "<name>" in PLL location <name> because the location does not accept <name> PLLs
ID:176563 Can't place <name> PLL "<name>" in PLL location <name> because PLL has a location assignment that is incompatible with the PLL location in the device
ID:176564 Can't place <name> PLL <name> in PLL location <name> because PLL is already assigned to <name>
ID:176565 Cannot place <name> PLL "<name>" in corner PLL location <name>, because PLL has a dual-regional clock assignment
ID:176566 Can't place <name> PLL "<name>" in PLL location <name>, because the PLL I/O pin <name> with port type <type> is already occupied by node "<name>"
ID:176567 Can't place I/O cell "<name>" in I/O pin <name> because it is already placed in I/O pin <type>
ID:176568 Can't place <name> PLL "<name>" in PLL location <name> because I/O cell <name> (port of type <type> of the PLL) has an incompatible location assignment with PLL I/O pin <name>
ID:176569 Can't place <name> PLL "<name>" in PLL location <name> because its input clock "<name>" has a frequency higher than PLL I/O pin <name> can support
ID:176570 Can't place <name> PLL "<name>" in PLL location <text> because its feedback input pin "<name>" is placed at PLL I/O pin <text>, which is not a positive differential input pin
ID:176571 Can't place <name> PLL "<name>" in PLL location <name> because its input clock "<name>" uses I/O standard <name> and has a frequency of <name> but PLL I/O pin <name> can only support a frequency up to <name>
ID:176572 Can't place the <name> PLL "<name>" in the PLL location <name> because the location operates on compensation mode but the PLL supports only "no compensation" mode
ID:176573 Cannot place <name> PLL "<name>" in PLL location <name>, because the input clock of the PLL "<name>" uses I/O standard <name> and has a frequency of <name>. However, the PLL I/O pin <name> only supports a frequency up to <name>.
ID:176574 Cannot implement <name> PLL "<name>", because the input clock of the PLL "<name>" uses I/O standard <name> and has a frequency of <name>. However, the device only supports a frequency up to <name>.
ID:176575 Cannot implement <name> PLL "<name>", because the input clock of the PLL "<name>" uses I/O standard <name> and has a frequency of <name>. However, the device only supports a frequency up to <name>.
ID:176576 Cannot place <name> PLL "<name>" in PLL location <name> -- location does not allow a fbin port
ID:176577 Can't place <type> PLL "<name>" in PLL location <name> -- PLL input clock port <name> requires too many routing resources of type <type>
ID:176578 Can't place <number> PLL "<name>" in PLL location <name> -- PLL requires <number> clock output ports but the PLL location only has <number> clock output ports
ID:176579 Can't place <name> PLL "<name>" in PLL location <name> -- no global clock location available for PLL input clock port <name>
ID:176580 Clock output port <name> of <type> PLL has illegal Global Signal option setting <type> -- must be set to Global Clock or Regional Clock
ID:176581 Changed the compensation clock parameter for PLL "<name>" to regional clock instead of global clock setting because PLL is placed in location that compensates for regional clock only -- clock outputs that do not use a regional clock may not be fully compensated
ID:176582 Changed the compensation clock parameter for PLL "<name>" to <type> instead of <type> -- clock outputs that do not use the same clock type may not be fully compensated
ID:176583 Output pin "<name>" (external output clock of PLL "<name>") uses I/O standard <name>, has current strength <name>, output load <number>pF, and output clock frequency of <name>, but target device can support only maximum output clock frequency of <name> for this combination of I/O standard, current strength, and load
ID:176584 Output pin "<name>" (external output clock of PLL "<name>") uses I/O standard <name>, has current strength <name>, output load <number>pF, and output clock frequency of <name>, but target device can support only maximum output clock frequency of <name> for this combination of I/O standard, current strength and load
ID:176585 <name> PLL "<name>" uses scandata input port - Fitter will preserve the order of its clock output ports
ID:176586 PLL "<name>" clock "<name>" uses <number> global clock and <number> regional clock settings
ID:176587 PLL "<name>" clock "<name>" uses <number> global clock or regional clock settings
ID:176588 Can't place <number> clocks signals of type <name> on <name> side of device -- device only supports <number> clock signals on the <name> side
ID:176589 Node "<name>" in location <name> uses <number> global clock, <number> regional clock, and <number> global or regional clock signals
ID:176590 PLL "<name>" uses <number> global clock, <number> regional clock, and <number> global or regional clock signals
ID:176591 Input clock of Fast PLL "<name>" cannot use global or regional clock because the Fast PLL drives a SERDES receiver that does not use dynamic phase alignment
ID:176592 Cannot place input clock "<name>" of <name> PLL "<name>" -- input clock must be placed in dedicated input clock I/O location and must not use global or regional clock -- PLL is in Zero Delay Buffer mode or External Feedback mode
ID:176593 Cannot place <name> PLL "<name>" in PLL location <name> -- compensated output clock pin "<name>" of the PLL must be placed in dedicated output clock I/O -- PLL is in zero-delay buffer mode
ID:176594 Input clock of <name> PLL "<name>" must be fed by an I/O node -- PLL is in zero delay buffer or external feedback mode
ID:176595 Entity "<name>" PLL "<name>" is user assigned to <name>
ID:176596 Corner PLL "<name>" input clock inclk[<number>] is not fully compensated. because it is fed by a center pin "<name>".
ID:176597 Corner PLL "<name>" input clock inclk[<number>] is not fully compensated because it is fed by a center pin "<name>"
ID:176598 PLL "<name>" input clock inclk[<number>] is not fully compensated because it is fed by a remote clock pin "<name>"
ID:176599 Transceiver PLL "<name>" input clock inclk[<number>] may have reduced jitter performance because it is fed by a non-dedicated clock pin "<name>"
ID:176600 Transceiver PLL "<name>" input clock inclk[<number>] may have reduced jitter performance while used for transceiver channels that configured at a data rate that is higher or equal to 2.97 Gbps because it is fed by a clock pin "<name>"
ID:176601 Can't achieve compensation delay of <number> for PLL "<name>" -- achieved compensation delay of <number>
ID:176602 Can't assign clock type <type> to node "<name>" in location <name>
ID:176603 Cannot place node <name> at <text> because it cannot drive the node <name> placed at <text>
ID:176604 Cannot place node <name> at <text> because it drives inclk port <number> of node <name> placed at <text> but must drive inclk port <text> instead
ID:176605 Clock select block <name> drives <number> clock enable block(s) but the current device only allows <number> clock enable block(s)
ID:176606 Clock select block <name> cannot drive clock enable block <name> with a clock type of <text> as the current device only allows a clock type of <text>
ID:176607 Clock select block <name> has <number> inclk inputs from <text>, but the current device only allows <number> inputs
ID:176608 CLKSELECT placement assigned the following <number> node(s) to these locations
ID:176609 Node <name> is assigned to location <text>
ID:176610 Changed the inputs of <number> CLKSELECT node(s) and inserted <number> logic node(s) to satisfy the current placement
ID:176611 Changed the inputs of node <name> and inserted <number> logic node(s) to change the logic of the clkselect inputs
ID:176612 Inserted node <name> to change the logic of the clkselect inputs of <name>
ID:176613 The following I/O buffers are being used illegally and must be connected to a pin.
ID:176614 The following I/O registers are being used illegally and must be connected to an output buffer.
ID:176615 The following I/O registers are being used illegally and must be connected to an input buffer.
ID:176616 The following I/O registers are being used illegally and must be connected to a DDIO input register.
ID:176617 The following I/O registers are used illegally and must drive an output buffer or DQS enable atom or be fed by an input buffer.
ID:176618 The following I/O registers are used illegally and must be driven by a DQS delay chain atom.
ID:176619 The following I/O registers are used illegally and must drive a DQS enable atom.
ID:176620 The following I/O registers are used illegally and must drive delay chains feeding an I/O output buffer or delay chain fed by an I/O input buffer.
ID:176621 Atom <name> "<name>"
ID:176622 <name> input of I/O clock divider atoms <name> and <name> must either be both connected to their own DQS config atoms or disconnected
ID:176623 The source driving the following ports must be the same
ID:176624 Source <name> drives port <name> on atom <name>
ID:176625 Atom <name> is not connected on port <name>
ID:176626 Atom "<name>" is connected on its <name> port but atom "<name>" is not connected. Both must be connected or both must be disconnected.
ID:176627 I/O Output Buffer "<name>" with programmable invert enabled has port "<name>" fed from "<name>" rather than the core
ID:176628 I/O atom "<name>" of type <name> must be assigned to the same I/O location as the other I/O atoms in its group
ID:176629 I/O register "<name>" has ports sclear and sload both connected by "<name>" and "<name>".
ID:176630 I/O register "<name>" must have the asdata port driven by VCC instead of "<name>" when the sload port is used.
ID:176631 The following I/O atoms have an invalid compatible inversion on the specified input ports
ID:176632 Atom "<name>" is expected to drive only one output buffer. The following atoms are also driven:
ID:176633 Port <name> on atom "<name>"
ID:176634 Can't place <name> I/O "<name>" to a non-memory interface specific I/O location <name>
ID:176635 Can't place I/O "<name>" to I/O location <name> because it does not support <name> mode memory interfaces
ID:176636 Can't place <name> I/O "<name>" to a non-<name> I/O location <name>
ID:176637 Can't place <name> I/O "<name>" to I/O location <name> because its memory interface I/O group cannot be placed
ID:176638 Can't place DQSn I/O "<name>" because this I/O location group has no DQSn I/O location
ID:176639 Can't place CQn I/O "<name>" because this I/O location group has no CQn I/O location
ID:176640 Can't place a high performance memory interface I/O group to left or right side I/Os
ID:176641 I/O "<name>" is connected as a <name> I/O in a x4 DQ_GROUP
ID:176642 IO_CLOCK_DIVIDER "<name>" is not associated with any memory interface I/O group
ID:176643 DQS_CONFIG block "<name>" is not associated with any memory interface I/O group
ID:176644 DQS_CONFIG "<name>" feeds more than six I/Os
ID:176645 Design has <name> memory interface groups of size <number>, but the selected device has only <name> locations that support <number> groups
ID:176646 Design has <number> DLLs, but the selected device has only <number> DLL locations
ID:176647 DLL atom "<name>" is using a clock period of <name>, which is outside the valid range for its configuration mode. When the delay buffer mode is "<name>" and the delay chain length is "<number>", the valid range is from <name> to <name>.
ID:176648 DLL atom "<name>" is using an unsupported configuration mode (delay buffer mode = "<name>", delay chain length = "<number>"). No clock period checks will be performed on the DLL atom.
ID:176649 Cannot place <name> I/O "<name>" to location <name>
ID:176650 Cannot place <name> I/O "<name>" in any legal location
ID:176651 Cannot place IO_CLOCK_DIVIDER "<name>" in any legal location
ID:176652 Cannot place DQS_CONFIG "<name>" in any legal location
ID:176653 Cannot place memory interface I/O group in pin group with DQS location <name>
ID:176654 Cannot place memory interface I/O group in any legal location
ID:176655 Cannot place DLL "<name>" in location <name>
ID:176656 Cannot place DLL_OFFSET_CTRL "<name>" in location <name> because its associated memory interface I/O groups cannot be placed
ID:176657 Cannot place PLL "<name>" to location <name>
ID:176658 Cannot place I/O "<name>" to location <name>
ID:176659 <name> I/O : "<name>"
ID:176660 I/Os have a memory interface specific sub-block, but have no memory interface grouping assignment specified
ID:176661 I/O "<name>" has a memory interface specific sub-block, but has no memory interface grouping assignment specified
ID:176662 <name> atom "<name>"
ID:176663 <name> assignment from "<name>" to "<name>"
ID:176664 <name> assignment from "<name>" to "<name>" with value <number>
ID:176665 I/O "<name>" is connected as a DQSn I/O
ID:176666 I/O "<name>" is connected as a CQn I/O
ID:176667 DQ_GROUP or MEMORY_INTERFACE_DATA_PIN_GROUP assignments have invalid values
ID:176668 The following external memory interface-related assignments are either incorrect or inconsistent
ID:176669 The following external memory interface-related assignments on "<name>" are either incorrect or inconsistent
ID:176670 Pin "<name>" requires a pseudo-differential I/O assignment.
ID:176671 The LCELL_COMB "<name>" atom has both "<name>" and "<name>" attributes assigned to it
ID:176672 Error Detection CRC is not supported at a core voltage of <name> (CRC power type: <name>)
ID:176673 Following <number> pin(s) must use differential I/O standard -- the Fitter will automatically assign <name> differential I/O standard to pin(s)
ID:176674 Following <number> pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
ID:176675 The following <number> pins driving clock input pins of a fast PLL do not have same I/O standard as other differential I/O pins driven by that PLL -- the Fitter will automatically assign <name> differential I/O standard to pin
ID:176676 Either the positive pin "<name>" or its complement pin "<name>", or both, might have constraints and therefore fails to fit in the device "<name>"
ID:176677 DQS config atom "<name>" associated with I/O pin "<name>" is driving the following atoms related to another I/O pin:
ID:176678 Input pins that are compensated by the source-synchronous PLL "<name>" are spread across multiple edges
ID:176679 Input pin "<name>" is on the <text> edge
ID:176680 MLAB cell <name> is driven by a combinational source on an input port
ID:176681 MLAB cell <name> and register cell <name> are connected through port <name> but these cells are required to be in the same partition.
ID:176682 Unable to place CK/CKn pair <name> and <name> on a differential pin pair because <name> has been assigned to a non-differential pin
ID:176683 Placing a CK or a CKn pin pair on <name> and <name> at the same row and column as the DQ pins may result in failure to constrain the DDIO Input nodes to improve DDIO timing
ID:176684 Unable to place CK/CKn pair <name> and <name> on a differential pin pair because they have been assigned to incompatible pins not belonging in the same pair
ID:176685 Unable to place CK/CKn pair <name> and <name> on a differential pin pair because they have been assigned to different I/O banks or edges
ID:176686 Unable to place CK/CKn pair <name> and <name> on a differential pin pair because there are no available differential pin pairs left
ID:176687 CK/CKn pin <name> has been placed on a PLL CLKOUT pin. The pin should be placed on Differential IO (DIFFIO) pins only.
ID:176688 Following atoms that are fed by the same clock source must have the same clock polarity
ID:176689 <name> clock <name>
ID:176690 Atoms that are placed in <name> must have the same clock source
ID:176691 <name> clock source is <name>
ID:176692 Pin <name> driving clock input pin of fast PLL <name> cannot have I/O standard <name>
ID:176693 HALF_RATE_INPUT atoms and DDIO_OUT atoms, which belong to the same DQS/DQ group, must all be driven by IO_CLOCK_DIVIDERs or all driven by the core
ID:176694 <name> clock source is <name>
ID:176695 HALF_RATE_INPUT atom <name> must have non-inverted clocks if clocked by an IO_CLOCK_DIVIDER
ID:176696 LVDS receiver data rate checking is disabled -. no timing info is available
ID:176697 Minimum frequency for high-speed clock input-related checks are disabled -- no timing info is available
ID:176698 LVDS transmitter data rate checking is disabled -- no timing info is available
ID:176699 PLL High Speed VCO maximum setting is not set -- no timing info is available
ID:176700 DLL maximum and minimum frequency-related checks are disabled -- no timing info is available.
ID:176701 Bidirectional pins <name> and <name> with pseudo-differential I/O standard have conflicting assignments, "Allow Single-ended Buffer for Differential-XSTL Input" (XSTL_INPUT_ALLOW_SE_BUFFER) and "Treat Bidirectional Pin as Output Pin" (TREAT_BIDIR_AS_OUTPUT)
ID:176702 Bidirectional pins <name> and <name> with pseudo-differential I/O standard have a differential input buffer, which is conflicting with the "Allow Single-ended Buffer for Differential-XSTL Input" (XSTL_INPUT_ALLOW_SE_BUFFER) assignment
ID:176703 Output enable ports of the bidirectional pins <name> and <name> with pseudo_differential I/O standard do not have the same inversion
ID:176704 CLKCTRL <name> has less registers on the enable (ena) path for some destinations, and consequently, it may have a slightly different behavior than expected
ID:176707 Output enable port of I/O buffer <name> must be present
ID:176708 Can't place I/O pin <name> with I/O standard <name> -- the I/O pin <name> drives or is driven by a SERDES
ID:176709 M144K does not support dual-port mode and different clocks on the inputs of each port for Stratix IV engineering sample devices. See the Stratix IV Errata Sheet for more information.
ID:176711 No remapping logic cells found for PLL <name> with non-phase dynamic reconfiguration enabled
ID:176712 <name> setting has changed from <number> to <number> on <name>.
ID:176713 The following delay chain settings have been changed for package skew compensation.
ID:176714 Pin <name> is assigned to location <name> and pin <name> is assigned to location <name>. These two pins form a differential pair. However, these two locations do not belong to the same differential pair.
ID:176716 inclk port of Clock Control Block "<name >" must be driven by <number > GPLL but is driven by <number > GPLLs.
ID:176717 Clock Control Block is driven by GPLL "<name >"
ID:176718 Pin <name> uses pseudo-differential output node <name>. However, these pins also have an I/O standard <name> that cannot be supported by the pseudo-differential output node.
ID:176719 I/O register node <name> is clocked by clock divider <name>. The I/O register node requires clock divider to be placed at location <name>, but the clock divider is placed at location <name>.
ID:176720 Fail to place DLL <name>.
ID:176721 UNIPHY_TEMP_VER_CODE is missing from the .qsf
ID:176722 You attempted to compile a project with an IP core generated for another family
ID:176723 DQS_DELAY_CHAIN atom <name> has DELAYCTRLIN bus with <number> out of <number> bits connected.
ID:176724 Illegal I/O location assignment for pin "<name>" (<name>) assigned to location <name> (<name>) (<name>)
ID:177000 There were not enough <ctype> clock drivers available
ID:177001 There was not enough core-to-clock-driver routing for <src> to route to <dst>.
ID:177002 If <dst> is placed in the following regions, <src> cannot be routed
ID:177003 Fitter encountered congestion in the clock network while routing from <src> to <dst>
ID:177004 Fitter encountered congestion while routing the <type (including space if not blank)>PLL feedback clock for <name>
ID:177005 Illegal Global Signal option assignment for Clock Control Block source <src> -- destination input <port> of node <dest> cannot have a Global Signal option of OFF
ID:177006 Route from node <src> to destination input <destport> of node <dest> requires a Clock Control Block
ID:177007 PLL(s) placed in location <name> do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks
ID:177008 PLL <name>
ID:177009 The PLL(s) placed in location <name> have a compensation path specified that differs from the output clock network type driven by the PLL - the PLL will compensate for the output clocks
ID:177010 Can't feed more than one HSSI reference clock to the PLL refclk select block <name>
ID:177012 Route from <name> to <name> is congested
ID:177013 Cannot route from <name> to <name> because the destination is in the wrong region
ID:177014 Invalid port found on the path from <name> to <name>
ID:177015 No paths exist from <name> to <name>
ID:177016 The <name> can only be merged with other logic from partition <partition>
ID:177017 Cannot route signal <name> using a clock driver because doing so would violate reconfigurable partition boundaries
ID:177018 One or more areas overlapped by partial reconfiguration region(s) use more global signals than are allowed for those areas
ID:177019 The area from coordinate (<number>,<number>) to coordinate (<number>,<number>) uses <number> global signals, but only <number> global signals are allowed
ID:177020 The PLL reference clock was not placed in a dedicated input pin that can reach <dest>
ID:177021 The external clock driver <name> cannot have an ENA_REGISTER_MODE setting of <value>. The only valid settings for external clock drivers are 'always enabled' or 'falling edge'
ID:177026 PLL drives <gclk>
ID:177027 PLL can drive only <max number of extclks> external clock signals, but this PLL drives <number driving>: <name>
ID:177028 PLL drives <number> external clock <signal(s)> on <IO type> <IO name>
ID:177029 The signal could not be placed in any of the below locations because the PLL feedback clock network was already used by <competing signal>, placed in location <location>
ID:177030 Also merged at this location: <other signal>
ID:177031 Column I/O clock network in the region bounded by (<top left X>,<top left Y>) and (<bottom right X>,<bottom right Y>) is <overused or congested>
ID:177032 Section clock (SCLK) network in spine clock region bounded by (<top left X>,<top left Y>) and (<bottom right X>,<bottom right Y>) is <overused or congested>
ID:177033 PLL can drive only <max number of gclks> global clocks, but this PLL drives <number driving> global clocks: <name>
ID:177034 Row clock network in the region bounded by (<top left X>,<top left Y>) and (<bottom right X>,<bottom right Y>) is <overused or congested>
ID:177035 The <direction> pin <name> assigned to HSSI <name> has no <fanin_or_fanout>.
ID:177036 PLL output counters driving <cell> are not recommended for use in the memory IP PHY clock tree and may cause decreased performance
ID:178000 Design requires <number> <name> -- too many to fit in the <number> locations available in the selected device
ID:178001 Could not find x1 clock line from <name> to <name>
ID:178002 Could not find reference clock network from <name> to <name>
ID:178003 Could not find duplex location to place duplex channel consisting of <name> and <name>
ID:178004 Could not find location for <name> that enable routing of bonding clock lines
ID:178005 Could not find location for <name> that enable routing of control-plane bonding signals
ID:178006 Could not find locations for <name> and <name> that enable routing of control-plane bonding signals
ID:178007 Could not find location for <name> that satisfies the <name> requirement of <name>
ID:178008 Illegal connection from source <name> to the reference clock input of <name> - source is not a HSSI reference clock pin or a ff-PLL counter clock output
ID:178009 Connection from <name> to <name> is not supported
ID:178010 Could not find location for <name> that supports configuration via PCIe
ID:178011 <name> was placed in location <name>
ID:178012 Core clock source from <name> node <name> does not have the same 0ppm source with respect to the PCS internal clock because <text>.
ID:178013 Node is not compatible with other nodes placed at the same location either because there are too few available <text> locations, or the nodes belong to different transceiver reconfiguration groups, or both.
ID:178014 Partition assignments may be preventing transceiver placement and optimizations across partitions that are not supported in this version of the Intel Quartus Prime software.For more information, refer to the Release Notes.
ID:178015 Cannot find a valid compensation counter setting for channels placed between <name> (placed at <text>) and <name> (placed at <text>)
ID:178016 The LC PLL "<name>" at the location <<number>, <number>>, which uses 14G VCO, cannot function well in ES parts. For more information, refer to the Release Notes.
ID:178017 Routing path from source to the destination requires non-functional IQCLK network. The source location contains: <text>. The destination location contains: <text>. Change the assignments for the source and sink instances may solve the issue.
ID:178018 Channels in bonded channel groups must be placed in contiguous locations. If CMU PLLs are used, gaps must be left for the transmit PLL channel.
ID:178019 <text>
ID:178020 Although the PCIE HIP block is enabled, some of the channels are not enabled.
ID:179000 Design requires <number> user-specified I/O pins -- too many to fit in the <number> user I/O pin locations available in the selected device
ID:179001 Current design requires <number> user-specified I/O pins -- <number> normal user-specified I/O pins and <number> programming pins that have been constrained to use dual-purpose I/O pin locations
ID:179002 Targeted device has <number> I/O pin locations available for user I/O -- <number> general-purpose I/O pins and <number> dual-purpose I/O pins
ID:179003 Design requires <number> HSSI I/O pin resources -- too many to fit in the <number> HSSI I/O pin locations available in the selected device
ID:179004 Design requires <number> HSSI reference clock I/O pin resources -- too many to fit in the <number> HSSI reference clock I/O pin locations available in the selected device
ID:179005 Design requires <number> dedicated programming I/O pin resources -- too many to fit in the <number> dedicated programming I/O pin locations available in the selected device
ID:179006 Design requires <number> JTAG I/O pin resources -- too many to fit in the <number> JTAG I/O pin locations available in the selected device
ID:179007 Not enough I/O pin locations available with sub-components of type "<sub_component_type>"
ID:179008 Could not find enough available I/O pin locations that can be configured to use a <name> voltage of <name>
ID:179009 Could not find enough available I/O pin locations that supports the <iostd> standard
ID:179010 Source I/O is not placed onto a dedicated REFCLK input pin
ID:179011 Source REFCLK I/O cannot be routed using dedicated clock routing
ID:179012 Refclk input <name> is placed onto <location>
ID:179013 The <name> is placed onto <location>
ID:179014 Cannot pack DDR register <name> and I/O node <name> -- register fans out to <fanout> destinations.
ID:180000 <name> is attempting to compensate for multiple <name>(s), but it can compensate only for one <name>
ID:180001 Cannot place <name> because too many LVDS SERDES channels are already placed into one <name>
ID:180002 Cannot place <name> because the <name> is already driven by <number> clock and clock enable pairs
ID:180003 Cannot place <name> because the DPA clock tree does not support overlapping DPA groups
ID:180004 Cannot place <name> in the following locations because they cannot route to <destination name>.
ID:180005 The <cell description> name: <long name>
ID:181000 DQS bus feeds <number> DQ I/O pins -- the maximum allowed fanout of <number> DQ I/O pins has been exceeded
ID:181001 DQS I/O pin "<name>" feeds <number> DQ I/O pins -- the maximum allowed fanout of <number> DQ I/O pins has been exceeded
ID:181002 The DQS Group fed by the DQS I/O pin "<name>", contains too many I/O pins for the specified mode (<mode_name>)
ID:181003 The specified <name> DQS group uses: (<value>/<value>) total I/Os, (<value>/<value>) DQ I/Os, (<value>/<value>) differential input DQ I/Os, and (<value>/<value>) differential output DQ I/Os
ID:181004 DQS I/O pin "<name>" assigned differential I/O standard <name> -- DQS I/O pin does not feed a nDQS I/O pin. A DQS I/O pin that does not feed a nDQS I/O pin cannot have a differential I/O standard assignment
ID:181005 DQS I/O pin "<name>" assigned I/O standard <name> -- nDQS I/O pin "<name>" fed by DQS I/O pin assigned I/O standard <name> -- both pins must be assigned same I/O standard
ID:181006 DQS I/O pin "<name>" connects to nDQS I/O pin "<name>", but uses the non-differential I/O standard <name>-- both pins must be assigned a differential I/O standard
ID:181007 Incompatible I/O standards detected for pins in the DQS group fed by DQS I/O pin "<name>" -- standards must have the same VCCIO and compatible VREF voltage requirements
ID:181008 DQ I/O pins fed by DQS I/O pin "<name>" have been assigned differential I/O standards -- DQ I/O pins may only use single-ended I/O standards.
ID:181009 DQ I/O pins fed by DQS I/O pin "<name>" assigned different I/O standards -- it is recommended that all DQ I/O pins fed by the same DQS I/O pin have the same I/O standard
ID:181010 I/O pin "<name>" of type <name> has I/O standard assignment of <name>
ID:181011 Incompatible on-chip termination settings detected for pins in the DQS group fed by DQS I/O pin "<name>". All pins in group must use the same OCT control block.
ID:181012 I/O pin "<name>" of type <name> is using on-chip termination control block "<name>"
ID:181013 Design requires <number> delay locked loop (DLLs) -- device can contain maximum of <number> DLLs
ID:181014 Design requires <number> DQS I/O pins -- device can contain maximum of <number> DQS I/O pins
ID:181015 Design requires <number> nDQS I/O pins -- device can contain a maximum of only <number> nDQS I/O pins
ID:181016 Design requires <number> nDQS I/O pins -- device does not support nDQS I/O pins
ID:181017 Design requires <number> <name> DQS I/O pins -- selected device cannot contain more than <number> <name> DQS I/O pins
ID:181018 Design requires <number> DQ I/O pins -- selected device can contain maximum of <number> DQ I/O pins
ID:181019 Design requires minimum of <number> DQSMUX resources to route the DQSBUS signals from DQS I/O pins to DQ I/O pins -- selected device contains only <number> DQSMUX resources
ID:181020 Design contains <number> <name>
ID:181021 Can't place DLL "<name>" in location <name> -- this DLL location cannot connect to the DQS group fed by DQS I/O pin <name>
ID:181022 Can't place <name> due to conflicting region constraints made to <name>.
ID:181023 Could not find locations to place DLL, Leveling Delay Chain, and DQS I/O Group such that connectivity between these blocks can be satisfied.
ID:181024 <cell> was placed in location <location>
ID:181025 <cell> could not be placed in any location.
ID:181026 Insufficient <dqs_group_desc> DQS I/O Group locations available to place <dqs_group>
ID:181027 Cannot route DQS bus in <dqs_bus_mode> mode from <dqs_group> to <pin>
ID:181028 Cannot place DQS <dqs_pin> in a location that can drive a <dqsbus_mode> <dqsbus_type> bus
ID:181029 <cell> was placed in location <location>
ID:181030 DDR circuitry in DQ I/O pin "<number>" is driven by too many DQS Delay Chain primitives
ID:181031 Illegal DQS leveling mux configuration detected for the DQS I/O Group fed by DQS I/O "<dqs_pin>" -- Group contains uncategorized <clock_phase_select> primitives.
ID:181032 More than one <name> primitive of type <clock_phase_select_type> is associated with the DQS I/O group fed by DQS I/O <dqs_pin>
ID:181033 <name> primitive "<name2>" has type "<clock_phase_select_type>"
ID:181034 <name> primitive "<name2>" was not categorized
ID:181035 External memory interface-related assignments are either incorrect or inconsistent
ID:181036 Atom "<name>" is not part of an I/O
ID:181037 I/O pin "<name>" is associated with more than one DQS I/O Group due to the following assignments:
ID:181038 DQ_GROUP assignment has an invalid value
ID:181039 <name> assignment from "<name>" to "<name>"
ID:181040 <name> assignment from "<name>" to "<name>" with value <number>
ID:181041 <name> assignment from "<name>" to "<name>" with value <number>
ID:181042 Detected illegal fanouts for <dqs_pin> primitive "<dqs_pin>" -- Group contains uncategorized <clock_phase_select> primitives.
ID:181043 Output port <port_name> of <atom_type> atom "<atom_name>" has one or more illegal fan-outs.
ID:181044 The <atom_type> Atom "<atom_name>" is an illegal destination
ID:181045 DQS I/O "<name>" is configured in x4 mode. Use of DQS I/Os in x4 mode has been disabled with the selected Stratix V ES device.
ID:181046 The DQS Group fed by <name> contains <number> I/Os
ID:181047 <io_pad_name> is in the DQS Group fed by <dqs_pad_name>
ID:181048 Cannot add <io_pad_name> to DQS Group fed by <dqs_pad_name>
ID:181049 The DQS Group containing "<name>", contains too many I/O pins for the specified mode (<mode_name>)
ID:181050 Could not merge leveling delay chains into the same location in an I/O bank -- leveling delay chains are driven by different DLLs.
ID:181051 DQS Group fed by DQS I/O pin "<cell>" might not function correctly on the selected Stratix V ES Device
ID:181052 <cell> was placed into <location>
ID:181053 PLL output counters driving <cell> are not recommended for use in the memory IP PHY clock tree and may cause decreased performance.
ID:181054 PHY clock tree is driven by PLL output <output_port> (counter: <pll_counter_index>, location: <location>)
ID:181055 PLL output counters 0-3 or 14-17 is not used for driving the PHY clock tree in your Stratix V device.
ID:181056 PLL counters that drive the PHY clock tree can be constrained using the set_location_assignment <PLL counter location> -to <PLL output signal> assignment.
ID:182000 Design requires minimum of <number> OCT calibration blocks; however, selected device contains only <number> OCT calibration block resources
ID:184016 There were not enough <gpio_desc> pin locations available
ID:184017 Pad is not the negative pad of a differential pin pair
ID:184018 The Quartus Prime Fitter detected an I/O configuration that is not currently supported.
ID:184019 The <name> node "<name>" has an illegal configuration.
ID:184020 Starting Fitter periphery placement operations
ID:184021 Fitter periphery placement operations ending: elapsed time is <time>
ID:184022 obuf primitive "<name>" has its dynamicterminationcontrol signal connected. Dynamic on-chip termination control is only supported for I/Os that are part of memory interface IP in the current version of the Quartus Prime software.
ID:184023 Fitter detected an unsupported memory interface hardware configuration
ID:184024 <name> node "<name>" has an illegal configuration
ID:184035 Design uses <number> DSP blocks, but only <number> DSP blocks are available in the device
ID:184036 Cannot place the following <number> DSP cells -- a legal placement which satisfies all the DSP requirements could not be found
ID:184037 Node "<name>"
ID:184038 Illegal DSP atom <name> with unconnected inputs
ID:184040 The <cell> was placed in location <location>
ID:184042 Found <number> Transceiver Reconfiguration Controllers
ID:184043 Fitter was unable to find Transceiver Reconfiguration Controllers associated with the following <number> transceiver PHY IP component blocks
ID:184044 Avalon Memory Map block <name>
ID:184045 Fitter found two transceiver PHY IP component blocks associated with the Transceiver Reconfiguration Controller interface id: <number>
ID:184046 Avalon Memory Map block <name> (associated with channel block <name>) has Transceiver Reconfiguration Controller interface id: <number>
ID:184047 Fitter was unable to process memory blocks within the transceiver reconfiguration controller (ALT_XCVR_RECONFIG) connected to transceiver PHY IP containing component Avalon Memory Map block <number>.
ID:184048 Fitter detected an unsupported memory interface hardware configuration -- IO_CONFIG primitive "<name>" has MULTIRANKSELECTWRITE port connected, but related I/O "<name>" is not part of a DQ_GROUP
ID:184049 Internal translation memory content map of the specified transceiver reconfiguration controller (ALT_XCVR_RECONFIG) has a word size of <number>. The correct word size is <number>
ID:184050 Input port <name> of the atom "<name>" is not connected
ID:184051 Input port <name> of the atom "<name>" is driven by the atom "<name>"
ID:184052 Internal translation memory content map of the specified transceiver reconfiguration controller (ALT_XCVR_RECONFIG) has <number> words. The number of words must be at least <number>
ID:184053 Fitter has detected that the transceiver reconfiguration controller (ALT_XCVR_RECONFIG) associated with the block <name> is out-of-date.
ID:184055 Already placed at this location: <cell>
ID:184056 Fitter has modified the internal translation memory content in a post-fit RAM in the transceiver reconfiguration controller (ALT_XCVR_RECONFIG) associated with block <name>
ID:184057 Fitter cannot read the .mif <name>
ID:184058 Fitter cannot write the .mif <name>
ID:184059 When Hard Reset Controller is enabled, input port <name> of PCI Express Hard IP node "<name>" cannot be driven by GND or VCC.
ID:184060 DSP "<name>" in 27x27 mode has mismatching Coefficient Select clocks
ID:188000 Following signals have routing constraints that seem to cause deterministic congestion. Routing constraints for some of these signals will be removed.
ID:188001 Signal "<name>" with routing constraints on line <number> of the routing constraints file
ID:188002 Signal "<name>" with auto-generated routing constraints
ID:188003 Signal "<name>" without routing constraints
ID:188004 Control signal routing from a previous compilation or Routing Constraints File could not be preserved at <num> block locations
ID:188005 Design requires adding a large amount of routing delay for some signals to meet hold time requirements, and there is an excessive demand for the available routing resources. The Fitter is reducing the routing delays of some signals to help the routing algorithm converge, but doing so may cause hold time failures. For more information, refer to the "Estimated Delay Added for Hold Timing" section in the Fitter report.
ID:188009 Rapid Recompile is attempting to use the previous placement information to reduce compilation time.
ID:188010 Rapid Recompile failed to locate previous placement information.
ID:188011 Rapid Recompile failed to use the previous placement information to reduce compilation time.
ID:188012 Rapid Recompile detected poor timing preservation. Placement will restart, and previous placement information will be ignored.
ID:188013 Rapid Recompile detected poor timing preservation. Routing will restart, and previous routing information will be ignored.
ID:188014 Rapid Recompile failed to locate previous routing information.
ID:188015 Rapid Recompile is attempting to use the previous routing information to reduce compilation time
ID:188016 Rapid Recompile has failed to use the previous routing information to reduce compilation time
ID:188018 Placement has finished and a timing estimate of the critical path is provided below. This timing may differ from the final timing sign-off values.
ID:188019 Router found <number> routing resources listed in an exclusion list section of a routing constraints file. These resources will not be used to route any signals.
ID:188023 The Fitter encountered congestion in the periphery. The likelihood of routing successfully on the next fit attempt is very low.
ID:188024 <message>
ID:188026 The Fitter failed to successfully route the design. View the Global Router Wire Utilization Map in the reports GUI and/or Routing Utilization in the Chip Planner to diagnose routing congestion. Based on the congestion information, modify your RTL or compiler settings to improve routability. Consult Intel Quartus Prime help about this message ID for more detailed advice.
ID:188028 The highest router effort tried by the fitter during this compile was: <name>
ID:188029 Fitter has determined that you must use the AND/OR programming method for Partial Reconfiguration.
ID:188030 Fitter recommends that you use the SCRUB programming method for the smallest partial bitstream size.
ID:188031 Ignored hold transfers: Source clock = <clk1>, Destination clock = <clk2>, Estimated delay added for hold = <delay> ns (<pctg> of available delay)
ID:189000 Can't open dockable window -- can't load library "<name>". <text>.
ID:189001 Only one node name is selected in the Node Finder
ID:189002 Access to file <filename> was denied.
ID:189003 File already exists. Do you want to overwrite the existing file?
ID:190000 IP Variation Editor (<text>) failed to launch
ID:190001 File extension (<name>) is not supported for the variation file of the IP megafunction
ID:190002 File '<file name>' already exists. Do you want to overwrite the existing file?
ID:190003 Variation file (<file name>) of the IP megafunction cannot be created
ID:192000 IP Generator (<launch command line>) failed to launch
ID:192001 File extension (<file extension>) is not supported for the variation file of the IP megafunction
ID:192002 File '<file name>' already exists. Do you want to overwrite the existing file?
ID:192003 Variation file (<file name>) of the IP megafunction cannot be created
ID:199000 Run Analysis and Synthesis with top-level entity name "<name>" or run I/O Assignment Analysis before running the EDA Netlist Writer
ID:199001 Run Analysis and Synthesis with top-level entity name "<name>" before running EDA Netlist Writer
ID:199002 Run the Timing Analyzer before running the EDA Netlist Writer
ID:199004 Run Fitter before running EDA Netlist Writer with --rcf option
ID:199005 Project name is required
ID:199006 Project name "<name>" contains illegal characters
ID:199007 Top-level entity name "<name>" contains illegal characters
ID:199008 Specify --tool option to use options
ID:199009 Use --gen_testbench when generating test bench files
ID:199010 Use --vector_source option and --testbench_file option when using --check_outputs option
ID:199011 Verilog Test Bench File or VHDL Test Bench File must be specified with --testbench_file option when using --vector_source option
ID:199012 File name "<name>" used with --testbench_file option is illegal -- file name must have .vt or .vht file extension
ID:199013 HDL output file name "<name>" used with --testbench_file option contains a non-existent directory path
ID:199014 Vector source file <name> specified with --testbench_vector_input_file option does not exist
ID:199015 Run Analysis and Synthesis using device family <name> as value for --family option before running EDA Netlist Writer
ID:199016 Run Analysis and Synthesis using device part <name> as value for --part option before running EDA Netlist Writer
ID:199017 Device part <name> is illegal
ID:199018 EDA tool name <name> cannot be used with top-level option. Refer to --help for legal EDA tool names.
ID:199019 Can't specify more than one top-level option. Refer to --help for list of top-level options.
ID:199020 Specify exactly one top-level option. Refer to --help for list of top-level options.
ID:199021 Value "<text>" for --format option is illegal. Refer to --help for legal values.
ID:199022 Can't use value "<name>" for --format option when using other options. Refer to --help for legal values and option combinations.
ID:199023 Value "<text>" for --format option is illegal. Using default --format option value for the specified tool. Refer to --help for legal values.
ID:199024 Tool name <name> for --tool option is illegal. Refer to --help for legal tool names.
ID:199025 Specify --format option when using --tool option. Refer to --help for legal values.
ID:199026 Run Fitter before running EDA Netlist Writer with options requiring post-fit netlist
ID:199028 Can't generate post-fit output files for specified command-line options. Run Analysis and Synthesis or specify different options. Refer to --help for legal options.
ID:199029 Timescale value "<name>" for --timescale option is illegal. Refer to --help for legal timescale values.
ID:199030 Report window sections are not supported for tool <name> of tool type <name>
ID:199031 Glitch filtering is not supported for <name> family
ID:199032 Glitch filtering is not supported for simulation tool <name>
ID:199033 VCD type <text> for --vcd_type option is illegal. No VCD script will be generated. Refer to --help for legal values.
ID:199034 VCD script generation is not supported for simulation tool "<name>"
ID:199035 Missing VCD testbench design instance path -- No VCD script will be generated
ID:199036 Run Fitter successfully before running EDA Netlist Writer
ID:199039 Formal verification not supported for specified design entry/synthesis tool
ID:199040 Device family does not support Synplify Premier as an EDA physical synthesis tool
ID:199041 Can't generate output netlist and other output files -- license for generating netlists for formal verification is not available
ID:199042 Can't generate IBIS Output File for board analysis
ID:199043 Can't generate HSPICE Output File for board analysis
ID:199044 Failed to generate Tcl Script File (.tcl) for EDA <type> tool
ID:199045 Can't generate formal verification files -- top-level design entity is a black-box
ID:199046 Generated files "<name>_board.data" and "<name>_board.mod"
ID:199047 Generated files "<mod file name>" and "<data file name>"
ID:199050 Generated IBIS Output File <name> for board level analysis
ID:199051 Generated HSPICE Output File <name> for board level analysis
ID:199052 Value "<text>" for --tool option is incompatible with --format option. Ignoring the --tool option value for the specified format. Refer to --help for legal values.
ID:199053 Generated <number> HSPICE Output files for board level analysis
ID:199054 Missing option --netlist=<vqm_file>
ID:199055 Can't generate files for Synopsys PrimeTime timing analysis tool because VHDL format is not supported if the Timing Analyzer is selected as the timing analysis tool in the current device family
ID:199058 Fail to evaluate Tcl command <name>
ID:199059 Can't generate files for ViewDraw EDA tool -- device family not supported in ViewDraw Flow
ID:199060 Can't find Timing Analyzer generated files.
ID:199061 Can't generate Greybox netlist file because the Greybox netlist file name "<name>" has a file extension .vqm, which is not a valid file extension for a Greybox netlist file name
ID:199062 Run Partition Merge with top-level entity name "<name>" before running EDA Netlist Writer
ID:199063 Run the Fitter, followed by the Timing Analyzer, before running the EDA Netlist Writer
ID:199064 Device family does not support board-level Boundary-Scan Description Language file generation
ID:199065 Generated Boundary-Scan Description Language output file <name> for board-level analysis
ID:199066 Run Fitter with top-level entity name <name> before running the EDA Netlist Writer
ID:199067 Quartus Prime software currently does not support the generation of timing analysis netlists for <name> device family
ID:199068 Can't use value "<name>" for the --bsdl_type option when using other options. Refer to --help for legal values and option combinations.
ID:199069 Can't use value "<name>" for --gen_script option. Refer to --help for legal --gen_script values.
ID:199070 Default netlist file "<file_name>" not found. Can't generate gate-level simulation command script.
ID:199071 Default Standard Delay Format Output File "<file_name>" not found; therefore, the gate-level timing simulation command script cannot be generated.
ID:200000 Double data rate (DDR) timing delays reported by <flow> are preliminary. Run the Timing Analyzer for analyzing delays on paths through the DDR.
ID:200001 Standard Delay Output File (.sdo) contains estimated delays -- run Fitter first to annotate SDF Output File with exact delays
ID:200002 Can't open file <name> for writing
ID:201000 Generated Verilog Test Bench File <name> for simulation
ID:201001 Generation of Verilog Test Bench File <name> for simulation was NOT successful
ID:201002 Generated VHDL Test Bench File <name> for simulation
ID:201003 Generation of VHDL Test Bench File <name> for simulation was NOT successful
ID:201004 Can't generate test bench files -- successfully run Analysis and Elaboration on the project before generating test bench files
ID:201005 Ignoring output pin "<name>" in vector source file when writing test bench files
ID:201006 Can't recognize node "<name>" in vector source file -- ignoring node when writing test bench files
ID:201007 Can't find port "<name>" in design
ID:201008 Bus port "<name>" specified in vector source file has ports with indices that do not fall in the range of port <name>[<number>:<number>] in top level design of Quartus Prime project
ID:201009 Bus port "<name>" specified in vector source file has width of <number>, which does not match width <number> of top level port of same name
ID:201010 Can't open file <name> for writing
ID:202000 An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool.
ID:202001 Verilog output file generation for formal verification is disabled because the project contains source files generated by Synplify with certain feature restrictions
ID:202002 Cannot generate netlist output files because the license for encrypted file "<name>" is not available
ID:202003 Cannot generate netlist output files because the encrypted file "<name>" is no longer encrypted
ID:202004 Cannot generate greybox netlist output files because licenses for generating greybox netlist are not available
ID:202005 Generating greybox netlist output files with changed lutmask
ID:202006 Generating greybox netlist output files with original lutmask
ID:202007 Generating greybox netlist is not supported for post-fit netlist
ID:202008 Cannot generate netlist output files because the encrypted file "<name>" was not encrypted during Analysis and Synthesis
ID:202009 Cannot generate netlist output files because the encrypted file "<name>" is not the same file that was used during Analysis and Synthesis
ID:203001 Unable to write Verilog Quartus Mapping File because there is no netlist available
ID:203002 Generated Verilog Quartus Mapping File using post-fit netlist
ID:203003 Generated Verilog Quartus Mapping File using post-synthesis netlist
ID:203004 No file name or illegal path specified for Verilog Quartus Mapping File -- can't save intermediate synthesis results
ID:203005 Can't generate netlist output files because the license for encrypted file "<name>" is not available
ID:203006 Can't generate netlist output files because the encrypted file "<name>" is no longer encrypted
ID:203007 Can't generate greybox netlist output files because licenses for generating greybox netlist are not available
ID:203008 Generating greybox netlist output files with changed lutmask
ID:203009 Generating greybox netlist output files with original lutmask
ID:203010 Generating clearbox netlist output files with original lutmask
ID:203011 Generating greybox netlist is not supported for this family
ID:203012 Generating greybox netlist is not supported for post-fit netlist
ID:203013 Can't generate netlist output files because the encrypted file "<name>" was not encrypted for Analysis & Synthesis
ID:203014 Can't generate netlist output files because the encrypted file "<name>" is not the same file which was used for Analysis & Synthesis
ID:203015 Can't generate greybox netlist file because the greybox netlist file name "<name>" has a file extension ".vqm" which is not a valid file extension for a greybox netlist file name
ID:203016 Verilog Quartus Mapping File generation is disabled because the project contains source files generated by Synplify with certain feature restrictions
ID:204000 Port <name1> is changed into <name2> because it has negative index
ID:204001 Port "<name1>" is changed into "<name2>" because it's a member of 2-D array port "<name3>"
ID:204002 Changed type of port "<name>" from INTEGER to STD_LOGIC
ID:204003 Can't generate output netlist file -- port "<name>" of the top-level design entity is an unsupported two-dimensional array port
ID:204004 Can't generate output netlist file -- port "<name>" of the top-level design entity is an unsupported type
ID:204005 Can't generate output netlist file <name> -- output netlist files are read-only
ID:204006 Can't open file <filename> for reading
ID:204008 Glitch filtering information will not be written out to the simulation netlist because device family <family> does not support glitch filtering
ID:204009 Can't generate netlist output files because the license for encrypted file "<name>" is not available
ID:204012 Can't generate netlist output files because the file "<name>" is an OpenCore Plus time-limited file. Remove the unlicensed cores or obtain a license for those OpenCore Plus time-limited IP cores used in the design. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
ID:204013 Can't generate netlist output files because the encrypted file "<name>" is missing
ID:204014 Can't generate netlist output files because the encrypted file "<name>" is not the same file which was used for Analysis & Synthesis
ID:204015 Can't generate netlist output files because the encrypted file "<name>" is no longer encrypted
ID:204016 Can't generate netlist output files -- compile project successfully before generating output netlists
ID:204017 Run timing analysis before generating netlist/output files for the selected EDA tool(s)
ID:204018 Generated files "<name>" and "<name>" in directory "<name>" for EDA <name> tool
ID:204019 Generated file <name> in folder "<name>" for EDA <name> tool
ID:204020 Writing VCD Dump Commands for all nodes to <name>
ID:204021 Can't open file <name> for writing
ID:204022 Can't map all signals in the design to the EDA simulation netlist
ID:204023 Can't find a corresponding signal for <name> in the EDA netlist
ID:204024 Created port "<port_name>" on instance "<instance_name>" of hierarchy entity "<entity_name>" in the EDA formal verification netlist to connect extra signals crossing the hierarchy boundary
ID:204025 Connected signal "<signal_name>" to bit <bit> of port "<port_name>"
ID:204026 Generated files "<name>", "<name>" and "<name>" in directory "<name>" for EDA <name> tool
ID:204027 Generated simulation netlist will be non-hierarchical because the design has Signal Tap partitions, termination control logic and/or a design partition that contains bidirectional ports
ID:206000 Cannot save file <name>
ID:206002 No insertion point specified for file
ID:206003 Unrecognized file format
ID:206004 Top Boot Data is not supported in current version of the Quartus Prime software
ID:206005 Cannot add multiple HEX files to <Main Block Data or Bottom Boot Data> item
ID:206006 Conversion Setup File <name> is in an older Conversion Setup File format
ID:206007 Saved Conversion Setup File <name>
ID:206008 No file name specified for Conversion Setup File
ID:206009 Cannot find file <name>
ID:206010 Cannot load Programmer Object File in POF Data item -- POF contains unknown device <name>
ID:206011 Cannot add Programmer Object File to POF Data item-- only Programmer Object Files for serial configuration devices can be converted into Raw Programming Data Files
ID:206012 Missing key programming file output file name
ID:206013 The keys you entered do not match
ID:206014 Use the keypad to enter the encryption key
ID:206015 Generated <file name> successfully
ID:206016 Failed to generate <file name>
ID:206017 <text - key name> in Key <text - file id> file is ignored because it contains an invalid character.
ID:206018 <text - key name> in Key <text - file id> file is longer than <number> characters. Only the first <number> characters will be used.
ID:206019 <text - key name> in Key <text - file id> file will be ignored because it does not have enough characters.
ID:206020 Key is <number> bits (<number> hexadecimal characters). You have reached this limit.
ID:206021 '<text - character entered>' is not a valid <text - type of characters> character. Please enter a valid <text - type of characters> character.
ID:206022 POF Data item missing input file
ID:206023 Device name <name> already exists
ID:206024 HEX Data item missing input file
ID:206025 No input file specified
ID:206026 <name> does not support remote update and local update
ID:206027 Device <name> supports using either bitstream encryption or bitstream compression. The Quartus Prime software is disabling bitstream compression and using bitstream encryption.
ID:206028 Unable to load all the programming files specified in <name>. See the System tab of the Messages window for more details.
ID:206029 You must reserve at least 2% of memory density for NAND flash reserved block
ID:206030 <name> address <number> is not a valid block address.
ID:206031 Option bit address range cannot overlap with NAND flash reserved block address range.
ID:207000 Selected device <name> does not support ISP CLAMP feature
ID:207001 I/O Pin State File <name> is incompatible with selected device
ID:207002 Cannot save I/O Pin State File <name>
ID:208300 Cannot run Programmer Debugger (quartus_pgmd) -- No valid option is specified.
ID:208301 <name> programming hardware cable is not valid, detected, or specified.
ID:208302 More than one programming cable option specified for the <name>
ID:208303 More than one option specified for option <name>
ID:208304 Cannot run Programmer Debugger (quartus_pgmd) -- option "<name>" is illegal or missing.
ID:208305 Programming cable for MONSTER and DUT cannot be the same.
ID:208400 Can't save or open file <name>
ID:208500 Specify programming hardware setup
ID:208501 Unable to scan device chain. <Hardware not connected, Can't scan JTAG chain, Port in use, or Check the hardware setup.>
ID:208502 Unable to scan device chain. <Hardware not connected, cannot scan JTAG chain, port in use, or check the hardware setup.> Please use JTAG Chain Debugger to troubleshoot the JTAG chain.
ID:208503 Cannot add Flash Memory Programmer Object File at the top level
ID:208504 Cannot add JTAG Indirect Configuration File at the top level
ID:208505 JTAG support disabled in file <name>
ID:208506 Cannot add target device <name> to device chain when in current programming mode
ID:208507 Programming file <name> selected for replacement contains device <name>, which is incompatible with target device <name> in device chain.
ID:208508 Cannot program device <text> in JTAG mode. The device will be bypassed in JTAG chain
ID:208509 Cannot open file <name>. See System tab (Messages window) for details.
ID:208510 Unknown hardware detected
ID:208511 Device chain in use
ID:208512 Application <info> is using the target device
ID:208513 Can't find JTAG Server
ID:208514 Device not responding
ID:208515 JTAG Server not running
ID:208516 JTAG Server out of memory
ID:208517 Selected port is busy
ID:208518 JTAG Server can't access selected programming hardware
ID:208519 Can't access JTAG chain. Make sure the board is powered on and programming hardware is connected properly, and check the integrity of the board.
ID:208520 Unexpected error in JTAG server -- error code <number>
ID:208521 Injects <number> error(s) into device(s)
ID:208522 Starting the multiple fault injections process. Enter q to stop injecting fault.
ID:208523 Fault Injection IP logic checking
ID:208524 Error Message Register (EMR) checking
ID:208525 External scrubbing
ID:208526 Device <number> : Partial Reconfiguration testing frame (<number>/<number>) - <name>, with data size of <number> words
ID:208527 PR operation failed - PR_READY is <number>, PR_DONE is <number>, PR_ERROR is <number> and CRC_ERROR is <number>
ID:208528 Fault Injection IP not loaded on device <number>
ID:208529 Can't fault inject device. Expected virtual IR length of at least <number> bits for device <number>, but found virtual IR length of <number>.
ID:208530 SRAM Object File <name> does not contain valid path name
ID:208531 Partial Reconfiguration Programmer Object File <name> already exists. Do you want to overwrite file?
ID:208532 Invalid password. Remaining trial: <number> time(s)
ID:208533 Operation failed. Expected JTAG ID code 0x<number> for device <number>, but found JTAG ID code 0x<number>.
ID:208534 Activate Partial Reconfiguration testing frame speed-up feature.
ID:208535 Partial Reconfiguration testing frame failed.
ID:208536 Execute PRPOF <name>.
ID:208537 Failed to execute PRPOF <name>.
ID:208538 Fault injection IP on device <number> is not granted.
ID:208539 Clearing EMR array
ID:208540 Reading EMR array
ID:208541 Fault injection IP on device <number> is outdated.
ID:208542 The number of injected errors exceeds <number>. Fault injection IP on device <number> can store up to <number> error messages. To clear stored error messages, conduct Read EMR
ID:208543 No frame error detected in device <number>.
ID:208544 <number> frame error(s) detected in device <number>.
ID:208545 Error #<number> <name>: <name> in frame <name> at bit <name>. <name>
ID:208546 Device <number> does not have EMR array support
ID:208547 Injects <number> error(s) into device(s). Enter q to stop injecting fault.
ID:208548 Starting the multiple fault injections process. Click the Stop button to stop injecting fault.
ID:208549 Failed to start up engine after programming.
ID:208550 No device is programmed with signature.
ID:208551 Program signature into device <number>.
ID:208552 Signature of device <number> mismatch.
ID:208553 Failed to read EMR cache of device <number>.
ID:208554 Device <number> fails to start fault injection after <number> attempts to get fault error with desired sensitive.
ID:208801 More than one programming cable option specified
ID:208802 More than one device index option specified
ID:208803 Can't run Fault Injection Debugger (quartus_fid) -- No valid option is specified
ID:208804 Can't run Fault Injection Debugger (quartus_fid) -- option "<name>" is illegal or missing
ID:208805 Programming hardware cable not detected
ID:208806 Programming cable does not support <name> programming mode
ID:208807 More than one programming cable found in available hardware list -- use --list option to display available hardware list and specify correct programming cable
ID:208808 Using programming cable "<name> [<name>]"
ID:208809 Using programming cable "<name> on <name> [<name>]"
ID:208810 Can't scan JTAG chain. Error code <name>.
ID:208811 <name> file <name> does not contain valid path name
ID:208812 Argument option <name> is illegal. Refer to --help for legal argument option combinations.
ID:208813 Device index <name> must be less than device index of physical JTAG chain. Check board or choose legal device index.
ID:208814 Device <name> does not support fault injection.
ID:208900 Fail to read SMH file.
ID:209000 Can't verify device
ID:209001 JTAG ID code specified in JEDEC STAPL Format File does not match any valid JTAG ID codes for device. Verify that the target device's location on the circuit board matches the device's location in the device chain.
ID:209002 Blank-Check failed on device
ID:209003 Can't recognize exit code <number> for Jam STAPL Byte Code 2.0 File <name>
ID:209004 Programming error: <text>
ID:209005 Programming status: <text>
ID:209006 <text>
ID:209007 Configuration succeeded -- <number> device(s) configured
ID:209008 Configuration failed
ID:209009 Unable to reset device before configuration
ID:209010 Device did not accept configuration data (after <number> bits sent)
ID:209011 Successfully performed operation(s)
ID:209012 Operation failed
ID:209013 CONF_DONE pin failed to go high
ID:209014 CONF_DONE pin failed to go high in device <number>. Make sure all communication cables are securely connected, select a different device, check the power on the target system, or make sure all nCE pins are connected to GND. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
ID:209015 Can't configure device. Expected JTAG ID code 0x<number> for device <number>, but found JTAG ID code 0x<number>. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf).
ID:209016 Configuring device index <number>
ID:209017 Device <number> contains JTAG ID code 0x<number>
ID:209018 Device <number> silicon ID is <text>
ID:209019 Blank-checking device(s)
ID:209020 Blank-checking device <number>
ID:209021 Performing <type>verification on device(s)
ID:209022 Performing <type>verification on device <number>
ID:209023 Programming device(s)
ID:209024 Programming device <number>
ID:209025 Can't recognize silicon ID for device <number>. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly.
ID:209026 Blank-Check failed on device <number>
ID:209027 Verification failed for device number <number>
ID:209028 Operation canceled
ID:209029 Can't invoke Programmer to configure device
ID:209030 Can't access programming hardware <name>
ID:209031 Device chain in Chain Description File does not match physical device chain -- expected <number> device(s) but found <number> device(s).
ID:209032 JTAG Server out of memory
ID:209033 JTAG Server not running
ID:209034 Can't find JTAG Server
ID:209035 Device chain in use
ID:209036 Unknown hardware detected
ID:209037 JTAG Server can't access selected programming hardware
ID:209038 Examining devices
ID:209039 Examining device <number>
ID:209040 Can't access JTAG chain
ID:209041 Selected port is busy
ID:209042 Application <info> is using the target device
ID:209043 Erasing device <number>
ID:209044 Erasing <name> configuration device(s)
ID:209045 Orientation of device in socket is backwards
ID:209046 Current adapter cannot be used with device <name>
ID:209047 Adapter not recognized
ID:209048 <blank-check or verify> failure on device number <number>
ID:209049 Pin continuity failure on pin <name>
ID:209050 Socket must contain device
ID:209051 Multiple devices in adapter
ID:209052 Device not responding
ID:209053 Unexpected error in JTAG server -- error code <number>
ID:209054 Can't program <name> device with <name> Programmer Object File in current version of the Quartus Prime software
ID:209055 Multiple files specified in Programmer
ID:209056 Device number <number> failed to configure in passive serial chain
ID:209057 Can't examine more than one device in Chain Description File
ID:209058 Device has pin continuity failure
ID:209059 Cannot communicate with a device that contains an IP that supports the Intel FPGA IP Evaluation Mode feature. Device will stop functioning when it reaches its non-tethered mode timeout limit. Make sure the communications cable is properly attached and the device has power.
ID:209060 Started Programmer operation at <time>
ID:209061 Ended Programmer operation at <time>
ID:209062 Flash Loader IP not loaded on device <number>
ID:209063 The Intel FPGA IP Evaluation Mode IP in device <number> is not responding.
ID:209064 Failed to get access to the flash interface
ID:209065 The <name> device at position <number> with instruction register length = <number> in the JTAG chain couldn't be automatically defined
ID:209066 The instruction register length for the <name> device at position <number> in the JTAG chain is unknown
ID:209067 The attached CFI Flash device, CFI_<size>Mb, is larger than the size selected in the PFL IP, CFI_<size>Mb.
ID:209068 The attached Programmer Object File, CFI_<size>Mb, is larger than the CFI Flash device, CFI_<size>Mb
ID:209069 The attached Programmer Object File, CFI_<size>Mb, is larger than the size selected in the PFL IP, CFI_<size>Mb
ID:209070 The attached CFI Flash device, CFI_<size>Mb, is larger than the size selected in the PFL IP, CFI_<size>Mb -- <number>. The higher-order address lines are assumed to be driven low during PFL IP operation.
ID:209071 Programming the <name> device at position <number> for exclusive-secure bitstream configuration
ID:209072 SFL IP version loaded in the device chain is not consistent.
ID:209073 The firmware of the connected EthernetBlaster download cable does not support configuration of the <name> device at position <number>. Upgrade the EthernetBlaster firmware to the latest available version to configure this device.
ID:209074 The attached JTAG Indirect Configuration File (.jic) or Programming Object File (.pof), <size>Mb, is larger than the Serial Flash device, <size>Mb at device <number> -- Only the first <size>Mb JTAG Indirect Configuration File or Programming Object File data will be programmed to the device
ID:209075 Serial Flash Loader Active Serial Memory Interface on device <number> is not granted .
ID:209076 Operation on ASP configuration devices fails because the JTAG chain contains unknown device.
ID:209077 Can't erase or program protected sectors in the EPCS/EPCQ device
ID:209078 The Programmer Object File assigned to device <number> (CFI_<size>Mb) is for a smaller capacity device (CFI_<size>Mb).
ID:209079 Programmer Object File (<size>Mb) is larger than the Quad SPI Flash device QSPI_<size>Mb
ID:209080 Can't perform operation on EPCS<size> with current SFL IP version for device <size>
ID:210000 No programming file specified for JEDEC STAPL Format File, Jam STAPL Byte Code 2.0 File, Serial Vector Format File, or In System Configuration File
ID:210001 Can't open programming file <name> -- not valid <type> file
ID:210002 JEDEC STAPL Format File or Jam STAPL Byte Code 2.0 File must have cyclic redundancy check code
ID:210003 JEDEC STAPL Format File, Jam STAPL Byte Code 2.0 File, SRAM Object File, or Programmer Object File contains cyclic redundancy check code <number> that does not match expected CRC code <number>. Do you want to ignore CRC code and add file to JTAG chain?
ID:210005 Device index <number> is not associated with a specified programming file
ID:210006 Can't save or open file <name>
ID:210007 Can't locate programming file <name> in <name> <name>
ID:210008 Line <number> of Chain Description File <name> contains syntax error
ID:210009 Device <name> is not supported
ID:210010 Can't use programming file <name> because it contains an unsupported file extension
ID:210011 Configuration device <name> does not support multiple pages
ID:210012 Examining CFI POF image version 1 or 2 with non-sequential pages is not supported.
ID:210013 Raw Binary Files and Tabular Text Files do not support multiple pages
ID:210014 Configuration device <name> cannot configure device <name>
ID:210015 Can't create Serial Vector Format File for device <name>
ID:210016 TCK frequency of <text> is invalid. Maximum TCK frequency for current JTAG chain is <text>.
ID:210017 Devices in JTAG chain require different fixed TCK frequencies.
ID:210018 Configuration device <name> cannot configure device <name>
ID:210019 Illegal output file name
ID:210020 SOF Data item missing input file
ID:210021 Size of file(s) in <Main Block Data or Bottom Boot Data> exceeds memory capacity
ID:210022 SOF Data items must have unique page numbers
ID:210023 Configuration device <name> cannot be used with selected programming mode
ID:210024 <Hexadecimal (Intel-format) Output File, Programmer Object File, Raw Binary File, or Tabular Text File> programming file type does not support selected programming mode
ID:210025 Device <name> does not support selected mode
ID:210026 File <name> is corrupted
ID:210027 Can't use configuration device <name> with selected programming mode
ID:210028 Can't add file <name> to SOF Data
ID:210029 Bottom Boot Data item and Main Block Data item can each contain only one Hexadecimal (Intel-Format) File
ID:210030 Hexadecimal (Intel-Format) File data overlaps SRAM Object File data
ID:210031 Checksum on line <number> does not match expected checksum
ID:210032 Data in HEX File overlaps between data blocks at address <address> and address <address>
ID:210033 Memory Map File <name> contains memory usage information for file <name>
ID:210034 Error in file <name> at line <name> and column <name> -- <text>
ID:210035 Error occurred while initializing or parsing file : <name>
ID:210036 Device or configuration device <name> is not IEEE-1532 compliant
ID:210037 Can't create Hexadecimal (Intel-Format) Output File for <name> -- invalid Programmer Object File
ID:210038 Adapter not recognized
ID:210039 File <name> contains one or more time-limited IPs that support the Intel FPGA IP Evaluation Mode feature that will not work after the hardware evaluation time expires. Refer to the Messages window for evaluation time details.
ID:210040 SRAM Object File <name> contains time-limited IP that supports Intel FPGA IP Evaluation Mode feature -- Vendor: 0x<name>, Product: 0x<name>
ID:210041 Can't generate file -- file <name> contains time-limited cores
ID:210042 Can't convert time-limited SOF into POF, HEX File, TTF, or RBF
ID:210043 Can't generate <name> file for more than one programming file
ID:210044 Configuration device <name> does not support remote or local update
ID:210045 SRAM Object File does not have <name> turned on
ID:210046 Assign a Programmer Object File to the POF Data item
ID:210047 Programmer Object File does not have <name> update turned on
ID:210048 Configuration device <name> does not support remote or local update
ID:210049 Programmer Object File is corrupted
ID:210050 Can't support remote update difference file with file extension <name>
ID:210051 Writing file <name>
ID:210052 File cannot contain SRAM Object Files with both remote update and local update enabled
ID:210053 Size of device data exceeds memory capacity of configuration device
ID:210054 Clock frequency or clock divisor has illegal value
ID:210055 Device name <name> already exists
ID:210056 Device <name> does not support <name> file type
ID:210057 Page settings for Programmer Object File for Local Update are illegal
ID:210058 Programmer Object File cannot contain Hexadecimal (Intel Format) File in Main Block Data item and SRAM Object File with either remote update enabled or local update enabled in SOF Data item
ID:210059 Configuration device <name> does not support remote or local update
ID:210060 CLKUSR option turned off for programming
ID:210061 Illegal value or string encountered while parsing Conversion Setup File
ID:210062 Design compiled for <name> device, but quartus.ini file specifies use of <name> bitstream
ID:210063 quartus.ini file specifies use of <text> instead of <text> for current JTAG chain
ID:210064 The requested address range for page <page1> (<range1>) overlaps with the address range for page <page2> (<range2>)
ID:210065 Can't create Raw Programming Data File -- Programmer Object File does not contain serial configuration device
ID:210066 JEDEC STAPL Format Files, Jam STAPL Byte Code 2.0 Files, Serial Vector Format Files, and In System Configuration Files do not support <name> device
ID:210067 Page start address <number> and size <number> do not match original page start address <number> and size <number>
ID:210068 Page start address <number> is not a valid block address for the <name> flash device
ID:210069 Programmer Object File for Local Update must use both page 0 and page 1
ID:210070 Start and/or end address exceeds memory size
ID:210071 Can't add user-defined device to JTAG server -- internal error code <number> occurred
ID:210073 I/O Pin State File <name> missing version number
ID:210074 Can't initialize or parse I/O Pin State File <name> -- At least one bsr_cell element in I/O Pin State File <name> is missing pin name
ID:210075 At least one bsr_cell element in I/O Pin State File <name> is missing a value
ID:210076 Can't recognize file <name> as a valid I/O Pin State File
ID:210077 I/O Pin State File <name> contains one or more unknown pin names
ID:210078 I/O Pin State File <name> contains unknown error
ID:210079 Serial Vector Format Files do not support Sample and Sustain clamp option
ID:210080 Serial Flash Loader device is missing
ID:210081 Device <name> does not support Serial Flash Loader scheme
ID:210082 Device in I/O Pin State File <name> does not match device <name> in Programmer window
ID:210083 This version of the Quartus Prime software does not support ISC file generation for device <name>
ID:210085 Syntax error is found on line number <number> in JCF or FCF file
ID:210086 Device number <number> is missing in the JCF or FCF file
ID:210087 <name> is not a valid configuration file
ID:210088 Device <name1> specified in JCF file is already defined in the Quartus Prime database. However, the <name2> specified in the JCF file is different from the <name3> specified in the Quartus Prime database.
ID:210089 Can't attach File <name>
ID:210090 Page start address <number> do not match original page start address <number>
ID:210091 Compressed data size is greater than the uncompressed data size. Turn off the compression for enhanced configuration device.
ID:210092 Option address specified (<range1>) overlaps with the <datatype> data in page <page> (<range2>) of the flash device
ID:210093 Illegal option address value specified.
ID:210094 The HEX file <name1> located in the Main Block is not aligned on a 16-bit boundary
ID:210095 Encountered unknown file construct (<text>) in file <name>
ID:210096 The quartus.ini file specifies the use of <number> pad byte(s) instead of <number> pad byte(s) for the current bitstream conversion
ID:210097 The quartus.ini file specifies a program length count adjustment of <number> bit(s). The program length count for the current bitstream conversion is 0x<number> instead of 0x<number>
ID:210098 Active Serial/Parallel mode CONF_DONE pin error check is disabled
ID:210099 The quartus.ini file specifies the CRAM CRC value of 0x<number>, overriding the true CRAM CRC value of 0x<number>
ID:210100 The quartus.ini file specifies a Device ID value of 0x<number>, overriding the true Device ID value of 0x<number>
ID:210101 The quartus.ini file enables Control Block Emulator file generation
ID:210102 Generating CB Emulator files: <text> and <text>
ID:210103 File <text> is not a valid Hexadecimal (Intel-Format) File
ID:210104 Size of configuration device exceeds addressing capacity of controller
ID:210105 Configuration device <name> cannot configure device <name>. POF file will not be generated.
ID:210106 Target device <name> does not support multiple pages
ID:210107 Programming file <name> was produced by a version of the Quartus Prime software that has a known issue for <name> devices.
ID:210108 Multiple SFL devices are not supported in Jam or JBC files.
ID:210109 Advanced SEU Detection data size is <number> bytes
ID:210110 Device has <number>% critical bits
ID:210111 The SRAM Object File (.sof) you selected does not contain Advanced SEU Detection data.
ID:210112 PFL multiple flash programming is not supported in Jam, JBC or SVF files.
ID:210113 Inserting error at bit <number> in frame <number>.
ID:210114 Inserting error at bit <number> in frame <number>. This bit is in a redundancy frame and will not be detected by the CRC error detection block.
ID:210115 Active Serial Programming mode does not support secondary device
ID:210116 Current version of the Serial FlashLoader does not support EPCS<number> configuration device
ID:210117 Created JAM or JBC file for the specified chain: <name>
ID:210118 Created EKP file <name>
ID:210119 EKP file <name> sets the tamper protection bit
ID:210120 <text> information is incomplete. The ISP clamp functionality will be disabled.
ID:210121 NAND flash reserved block address specified (<range1>) overlaps with the <datatype> data in page <page> (<range2>) of the flash device
ID:210122 JAM and JBC file creation is not supported for NAND flash
ID:210123 SOF <name> for device <name> is not compiled for CvP.
ID:210124 <name> configuration mode does not support cascaded device chain
ID:210125 Configuration device <name> has been discontinued.
ID:210126 Can't locate programming file <name>
ID:211000 Specify programming hardware setup
ID:211001 Unable to scan device chain. <Hardware not connected, Can't scan JTAG chain, Port in use, or Check the hardware setup.>
ID:211002 Cannot find Quartus User-Defined Device or BSDL File <name>
ID:211003 JTAG chain connection is good. Detected <number> device(s)
ID:211004 JTAG chain connection is good and consistent. Detected <number> device(s)
ID:211005 Uncertain JTAG chain. Detected <number> device(s)
ID:211006 Detected <number> device(s)
ID:211007 Performed <number> iteration(s) of the IDCODE test
ID:211008 No device detected. Detected <name> at TDI pin.<name>
ID:211009 Device <number>: <name>
ID:211010 JTAG chain problem detected
ID:211011 JTAG chain connection is inconsistent
ID:211012 TDI connection to the first detected device <name> might be shorted to GND
ID:211013 The TDI connection to the first detected device <device name> might be shorted to VCC or is an open circuit
ID:211014 The TCK and TMS connections to the device before the first detected device <device name> might have a problem
ID:211015 Incorrect clock and TDI value
ID:211016 Incorrect clock value
ID:211017 Incorrect TDI value
ID:211018 Can't initialize chain - Error locking chain or hardware is not set
ID:211019 Fails to scan the chain
ID:211020 No state transition happens
ID:211021 Current hardware doesn't support TCK frequency setting
ID:211022 TCK frequency setting of <number> Hz set is invalid. TCK frequency allowed is in the range of 1.0kHz to 1.0MHz or 8MHz
ID:211023 Fail to set the TCK frequency
ID:212000 Cannot open file <name>. See System tab (Messages window) for details.
ID:212001 Cannot add target device <name> to device chain when in current programming mode
ID:212002 Device <name> selected for replacement is incompatible with target device <name> associated with programming file. Proceeding will cause programming file to disappear from Chain Description File. Do you want to replace target device with new device?
ID:212003 Programming file <name> selected for replacement contains device <name>, which is incompatible with target device <name> in device chain. Proceeding will cause new device associated with selected programming file to replace target device. Do you want to replace programming file?
ID:212004 Programming file of type <type> is not supported
ID:212005 Specify programming hardware setup
ID:212006 Some devices in current device list cannot be added to selected programming mode <name>. Do you want to clear all devices in current device list and switch to selected mode?
ID:212007 Device configuration is in progress. You must stop configuration before closing Programmer window.
ID:212008 Cannot start device configuration because no programming options have been selected for device chain
ID:212009 Cannot save file <name>
ID:212010 Finished creating JEDEC STAPL Format File(s), Jam STAPL Byte Code 2.0 File(s), Serial Vector Format File(s), or In System Configuration File(s)
ID:212011 JEDEC STAPL Format File, Jam STAPL Byte Code 2.0 File, Serial Vector Format File, or In System Configuration File <name> already exists. Do you want to overwrite file?
ID:212012 JEDEC STAPL Format File, Jam STAPL Byte Code 2.0 File, Serial Vector Format File, or In System Configuration File <name> is read-only. Select another file name.
ID:212013 JEDEC STAPL Format File, Jam STAPL Byte Code 2.0 File, Serial Vector Format File, or In System Configuration File <name> does not contain valid path name
ID:212014 Cannot program device <text> in JTAG mode--device will be bypassed in JTAG chain
ID:212015 Cannot update JTAG Server with specified hardware: <type>
ID:212016 The hardware you selected could not be removed by the JTAG server
ID:212017 Unable to scan device chain. <Hardware not connected, Can't scan JTAG chain, Port in use, or Check the hardware setup.>
ID:212018 Cannot save Chain Description File <name> because programming file <name> has not been saved
ID:212019 Too many devices for In-Socket Programming mode or Active Serial Programming mode
ID:212020 Attempted to access JTAG server -- internal error code <number> occurred
ID:212021 Attempted to add user-defined device to JTAG server -- internal error code <number> occurred
ID:212022 JTAG support disabled in file <name>
ID:212023 Cannot add JTAG server "<name>" -- JTAG server already exists in servers list
ID:212024 Passwords do not match
ID:212025 Passive Serial mode supports only SRAM Object Files
ID:212026 JTAG standard requires odd value for JTAG ID and JTAG ID mask
ID:212027 Cannot save Chain Description File <name> -- device list contains unknown or undetermined device(s)
ID:212028 Current programming hardware does not support <name> programming mode
ID:212029 Programmer operation was <successful, NOT successful, or stopped>
ID:212030 Quartus User-Defined Device file <file name> already exists. Do you want to overwrite the file?
ID:212031 Cannot find Quartus User-Defined Device or BSDL File <name>
ID:212032 Cannot import Quartus User-Defined File <name>
ID:212033 Cannot export Quartus User-Defined Device File <name>
ID:212034 Define user-defined device(s) to export
ID:212035 I/O Pin State File <name> is incompatible with selected device
ID:212036 Specify server name
ID:212037 Option bits for base address are invalid
ID:212038 Cannot add Flash Memory Programmer Object File at the top level
ID:212039 Only Flash Memory Programmer Object File is supported
ID:212040 The Programmer does not support multiple devices with attached Flash Memory
ID:212041 Device name <name> already exists
ID:212042 Can't create JAM, SVF, or ISC file because <file name> is not saved.
ID:212043 Can't create JAM, SVF, or ISC file because <unknown device name> is an unknown device.
ID:212044 Can't create JAM, SVF, or ISC file because <unknown device name> cannot be determined.
ID:212045 Insufficient memory to add target device <device name> to the device chain
ID:212046 Failed to extract BSDL information
ID:212047 IR length cannot be less than 2 bits or more than 255 bits
ID:212048 Unable to scan device chain. <Hardware not connected, Can't scan JTAG chain, Port in use, or Check the hardware setup.> Do you want to open the JTAG Chain Debugger to troubleshoot the JTAG chain?
ID:212049 The auto-detected device chain does not match the Programmer's device list. Do you want to update the Programmer's device list, overwriting any existing settings?
ID:212051 There is an unsaved, examined programming file. Do you want to update the Programmer's device list, overwriting any existing settings?
ID:212052 Can't close window. File creation process is in progress.
ID:212053 Programming file was generated with the security bit support enabled. Do you want to disable the security bit?
ID:212054 Can't add more than one device in Active Serial programming mode
ID:212055 Can't define a duplicated flash.
ID:212056 Fail to define a flash.
ID:212057 Invalid programming time
ID:212058 Can't define a duplicated JTAG ID.
ID:212059 NAND flash reserved block address are invalid
ID:212060 Intel FPGA IP Evaluation Mode IP is running. You must stop the Intel FPGA IP Evaluation Mode IP before closing the Programmer window.
ID:213000 Programming mode <name> is illegal. Refer to --help for legal programming modes.
ID:213001 Device name <name> is illegal
ID:213002 Programming option <name> is illegal. Refer to --help for legal programming option combinations.
ID:213003 Device <name> doesn't match device <name> from programming file
ID:213004 Device <name> doesn't match device <name> detected in the hardware
ID:213005 No programming option(s) selected for device. Refer to --help for legal programming options.
ID:213006 Device <name> is not supported in the selected programming mode or for the requested operation. Select a different programming mode or operation supported by this device.
ID:213007 Can't program with both Chain Description File and programming files or devices -- use only Chain Description File or only programming files or devices
ID:213008 Programming option string "<name>" is illegal. Refer to --help for legal programming option formats.
ID:213009 File name "<name>" does not exist or can't be read
ID:213010 Programming file <name> is not a legal programming file -- specify a legal programming file
ID:213011 Using programming file <name> with checksum 0x<number> for device <name>@<number>
ID:213012 Specify a Chain Description File
ID:213013 Programming hardware cable not detected
ID:213014 Device index <name> is already used. Specify a unique device index.
ID:213015 No programming file specified for device number <name>. Specify a legal programming file name.
ID:213016 Can't use programming option(s) for device <name> while using Passive Serial mode. Remove programming option(s) or change programming mode.
ID:213017 Active Serial Programming mode and In-Socket Programming mode support only single-device programming. Remove extra devices or change programming mode.
ID:213018 Programming mode and programming cable must be first two options specified when using -o option
ID:213019 Can't scan JTAG chain. Error code <name>.
ID:213020 Can't determine JTAG chain. Device index is missing after file name "<name>". Either specify a device index for all devices or do not specify a device index for any device.
ID:213021 Device index <name> must be less than device index of physical JTAG chain. Check board or choose legal device index.
ID:213022 Device index <name> can be used only in JTAG mode -- remove device index <name> or use JTAG mode
ID:213023 Input file <name> is incompatible with selected output programming file type. Select a different input file or select a different output programming file type.
ID:213024 Output programming file <name> has illegal file extension
ID:213025 Option file contains illegal option "<name>". Refer to --help for legal programming options.
ID:213026 Can't generate programming file <name>
ID:213027 Command-line arguments missing <name> option
ID:213028 The <type> file is missing from the command-line arguments
ID:213029 Voltage value specified to create Serial Vector Format File is illegal -- change the voltage value
ID:213030 TCK frequency value missing from command-line arguments -- specify TCK frequency value using --freq option
ID:213031 Programming option to create Serial Vector Format File is missing -- specify programming option value using --operation option
ID:213032 Can't use option <name> and <name> together -- options are mutually exclusive
ID:213033 Illegal hexadecimal address <name> in option file
ID:213034 Address count direction value <name> is illegal -- specify UP or DOWN for address direction
ID:213035 Configuration device <name> is illegal -- specify a legal configuration device
ID:213036 Argument <name> is illegal -- argument unknown
ID:213037 Programming option "<name>" is illegal -- option unknown. Refer to --help for legal programming options.
ID:213038 Can't use program option with verify option to create Serial Vector Format File -- options are mutually exclusive
ID:213039 Can't use blank-check option with verify option to create Serial Vector Format File -- options are mutually exclusive
ID:213040 Can't access JTAG chain -- check programming hardware connections, power, and board integrity
ID:213041 Can't run Programmer (quartus_pgm) -- option "<name>" is illegal or missing
ID:213042 Can't create option file -- file name is missing
ID:213043 More than one programming cable found in available hardware list -- use --list option to display available hardware list and specify correct programming cable
ID:213044 More than one programming cable option specified
ID:213045 Using programming cable "<name> [<name>]"
ID:213046 Using programming cable "<name> on <name> [<name>]"
ID:213047 Programming cable does not support <name> programming mode
ID:213048 Device <name> does not support Serial Flash Loader scheme
ID:213049 Configuration device <name> can't support Altera Serial Interface
ID:213050 Convert Programming Files was NOT successful -- refer to messages that appear above this message for more information
ID:213051 File <file name> does not contain key <key id>.
ID:213052 Design security feature is not enabled.
ID:213053 Device does not support design security.
ID:213054 Fail to <action> QUD file
ID:213055 Cannot find Quartus User-Defined Device or BSDL File <name>
ID:213056 Option "non_volatile_key" applies only to Arria II GX, Stratix III, Stratix IV, Stratix V, Cyclone V, Arria V, Arria 10, and Cyclone 10 GX devices.
ID:213057 Input programming file <name> has illegal file extension
ID:213058 Programming file was not compiled with CvP enabled.
ID:213059 The cof should only include one sof for <name>.
ID:213060 CvP is not enabled in cof.
ID:213061 Invariance verification was successful.
ID:213062 Supplied Partial Reconfiguration .sof has incorrect invariant bits.
ID:214000 Can't open file "<file>" for writing
ID:214002 Created Early Power Estimation file "<file>"
ID:215000 Command line option <name> specified, but option <name> already found on the command line.
ID:215001 Command line option <name> specified multiple times, but can only be specified once.
ID:215002 Default toggle rate of <name> is specified, but it is invalid.
ID:215003 Default toggle rate of <name> is specified as a percentage, but the value is invalid.
ID:215004 Default toggle rate of <name> is specified, but the units are invalid.
ID:215005 Toggle rate of <number> is specified for output signal "<name>", but the value is invalid.
ID:215006 Conflicting absolute and percentage toggle rate assignments are specified for output signal "<name>".
ID:215007 Toggle Rate Percentage assignments on certain nodes are ignored because a clock domain could not be identified for these nodes.
ID:215008 Toggle Rate Percentage assignment on "<name>" is ignored.
ID:215009 Static probability of <number> is specified for node "<name>", but the value is invalid.
ID:215010 Toggle Rate Percentage of <number> is specified for node "<name>", but the value is invalid.
ID:215011 VCD File parser will not perform glitch filtering because device family <name> does not support it.
ID:215012 Vectorless power estimation will not be used to calculate unspecified toggle rates and static probabilities because vectorless power estimation is not supported by device family <name>.
ID:215016 The specified <temperature> is specified as the <name> junction temperature, but the specified temperature value is different than the <name> junction temperature, which was used by the Fitter.
ID:215017 The <temperature> value is specified as the <name> junction temperature, but this value is not a valid temperature.
ID:215018 This temperature setting of <number> degrees Celsius is specified as the <name> temperature, but the specified temperature exceeds the maximum allowable temperature of <number> degrees Celsius. Setting the specified temperature to the maximum allowable temperature.
ID:215019 Military temperature grade selected. Intel recommends that careful thermal analysis and power management be required for military temperature operation. System testing should be performed at extreme operating temperature points (low and high). Please refer to the following link for more information: http://www.altera.com/products/devices/military/mil-temp.html
ID:215020 Found <number> degrees Celsius specified as the <name> temperature, but the specified temperature is below the minimum allowable temperature of <number> degrees Celsius. Setting the specified temperature to the minimum allowable temperature.
ID:215021 The setting <number> degrees Celsius is specified as the <name> temperature, but the specified temperature is below the user-specified minimum allowable temperature of <number> degrees Celsius.
ID:215022 The setting <number> degrees Celsius is specified as the <name> temperature, but the specified temperature exceeds the user-specified maximum allowable temperature of <number> degrees Celsius.
ID:215023 The calculated junction temperature exceeds the user-specified maximum allowable temperature of <number> degrees Celsius.
ID:215024 A valid <name> thermal resistance value was not found.
ID:215025 Found <name> degrees Celsius/Watt specified for the <name> thermal resistance, but the value is invalid.
ID:215026 The following preset cooling solution was specified "<name>", but the string is invalid. The following default cooling solution "<name>" will be used.
ID:215027 Preset and custom cooling solutions are specified. The preset cooling solution setting is ignored.
ID:215028 Board thermal model is specified for a device family that does not support thermal modeling of boards. The setting is ignored.
ID:215029 No power estimate was produced.
ID:215030 No power estimate was produced. Power Analyzer has no power model for the target device family. Use the Early Power Estimator spreadsheet instead.
ID:215031 Total on-chip power estimate for the design is <number>.
ID:215032 The calculated junction temperature exceeds the maximum allowable temperature, using junction temperature of <number> degrees Celsius.
ID:215033 Quartus Prime Power Analyzer cannot calculate junction temperature.
ID:215034 Toggle rates for <number> nodes were above physically achievable device limits and have been clipped.
ID:215035 Device does not support maximum power characteristics.
ID:215037 Detailed signal activity file source information is not written to output Signal Activity File.
ID:215038 No signal activity data is required. Signal Activity File and Value Change Dump file settings will be ignored.
ID:215040 The board thermal model "<name>" was specified, but the string is invalid.
ID:215041 The board thermal model "<name>" was specified, but the string is invalid.
ID:215042 The specified board thermal model "<name>" is not valid for the given part.
ID:215043 The board thermal model "<name>" was specified, but is not valid for the given part.
ID:215044 No board thermal model was selected. Analyzing without board thermal modeling.
ID:215045 The specified board temperature is less than the specified ambient temperature. Analyzing with the board temperature equal to the ambient temperature.
ID:215047 Entered board temperature <number> is greater than junction temperature <number>. Analyzing with board temperature equal to junction temperature (worst-case).
ID:215049 Average toggle rate for this design is <number>.
ID:218000 Using Advanced I/O Power to simulate I/O buffers with the specified board trace model
ID:218001 Found <number> output pins without output pin load capacitance assignment
ID:222013 Relative toggle rates could not be calculated because no clock domain could be identified for some nodes
ID:222014 Relative toggle rates were calculated using fastest clock for nodes in multiple clock domains
ID:222015 Using fastest of multiple clock domains found for node "<name>"
ID:222016 Relative toggle rates were calculated using slowest clock for nodes in multiple clock domains
ID:222017 Using slowest of multiple clock domains found for node "<name>"
ID:222018 Relative toggle rates could not be calculated because no unique clock domain could be identified for some nodes
ID:222019 Relative toggle rates could not be calculated because no unique register clock domain could be identified for some nodes
ID:223000 Starting Vectorless Power Activity Estimation
ID:223001 Completed Vectorless Power Activity Estimation
ID:223002 The given device family is not supported by Vectorless Power Activity
ID:224000 Perform analysis and synthesis with revision <name> before using Power Analyzer
ID:224001 Power Analyzer (quartus_pow) cannot be run because it requires a successful fit. Analysis and Synthesis (quartus_map) or Fitter (quartus_fit) process failed or was not run.
ID:224002 Power Analyzer (quartus_pow) cannot be run because it requires a successful fit. Fitter (quartus_fit) process either failed or was not run.
ID:224003 Project name <name> specified for Power Analyzer (quartus_pow) contains invalid characters
ID:224004 Specify a project for Power Analyzer (quartus_pow)
ID:224005 Revision name <name> specified for Power Analyzer (quartus_pow) --rev option contains invalid characters
ID:224006 Run Analysis and Synthesis (quartus_map) with device family <name> specified for --family option before running Power Analyzer (quartus_pow)
ID:224007 Run Analysis and Synthesis (quartus_map) or Fitter (quartus_fit) with device <name> specified for --part option before running Power Analyzer (quartus_pow)
ID:224008 Can't analyze current design -- target device <name> is not supported
ID:224009 Power Analyzer (quartus_pow) cannot be run -- target family <name> is not supported
ID:225000 Version compatible database generation failed. Quartus Prime will continue to archive the project without the version compatible database.
ID:225001 Can't create Quartus Prime Exported Partition (.qxp) File <name>
ID:225002 Quartus Prime failed to restore
ID:225003 Can't find required hierarchy file <name>
ID:225004 Current Quartus Prime Archive File contains megafunction files. Megafunction files may not be compatible with the current project.
ID:225005 Quartus Prime Archive File <name> already exists -- use the -u or update option to overwrite it, or use another file name
ID:225006 Can't create Quartus Prime Archive File <name>
ID:225007 Can't open file <name> for additions to or removals from the Quartus Prime Archive File (.qar)
ID:225008 Can't open Quartus Prime Archive File <name>
ID:225009 Can't create archive extraction directory <name>
ID:225010 Analysis was not performed on the current project. The Quartus Prime software may not be able to automatically locate all project files.
ID:225011 Can't add some files from file <name> to the Quartus Prime Archive File
ID:225012 Can't find file <name>
ID:225013 Ignored one or more files listed in file <name> because files with the same names were already selected
ID:226002 Cannot back-annotate assignments because design has not been compiled to the placed stage of fitter.
ID:227000 Back-annotated Global Signal logic options to node "<name>" may not work as intended as it is an internally generated name
ID:227001 There are problems back annotating Global Signal logic option from the node /"<name>/" to the node /"<name>/" -- found multiple destinations that requires different values
ID:228000 Can't back-annotate pin assignments because pin-out information for devices with preliminary support is subject to change
ID:228001 Back-annotation was successful. The locations of <name> nodes were written/updated.
ID:228002 Physical synthesis settings are on -- do you still want to back-annotate? Back-annotation will be unreliable unless you output a Verilog Quartus Mapping File and use it as the design source with your back-annotation.
ID:228003 Physical synthesis settings are on. The Quartus Prime software may create and/or rename nodes in the design. Intel recommends that you generate a VQM and use it as the design source file.
ID:228004 Can't back-annotate contents of selected LogicLock region because either the child regions or the selected region has Soft property turned on.
ID:228005 The following nodes have been placed outside of their user-specified region. New LogicLock assignments have been created automatically.
ID:228006 Node "<name>" was user assigned to LogicLock region <name> but fitter placed in LogicLock region <name>
ID:228007 Incremental compilation is on. Intel recommends using a post-fit netlist to preserve compilation results instead of back-annotation. Do you still want to back-annotate?
ID:228008 Router synthesis settings are on. Best results require a post-fit netlist to preserve compilation results instead of back-annotation. Do you still want to back-annotate?
ID:228009 No location assignments were back-annotated
ID:228010 Current device family does not support back-annotate nodes
ID:228011 Design contains LUT-RAM. Do you still want to back-annotate? Back-annotation will be unreliable since it's possible for the Fitter to place RAM into an MLAB cell.
ID:228012 Updated the size and origin of <name> LogicLock region(s) to match previous Fitter results.
ID:228013 Updated the size and origin of <number> LogicLock regions to match previous Fitter results. <number> regions were unchanged because they are already up-to-date.
ID:228014 No change was made - the selected LogicLock regions may not have previous Fitter results.
ID:229000 Tcl Script File "<name>" executed.
ID:229001 Can't run Tcl Script File "<name>". The error is: <name>
ID:230000 Device or device family does not support design partitions
ID:230001 Unable to load incremental compilation assignments. Either there is no opened project or the Quartus Prime Settings File for the project is corrupted or missing.
ID:230002 Are you sure that you want to delete <number> partition(s)? You will not be able to undo the operation.
ID:230003 Are you sure that you want to delete the netlists for <number> partition(s)? Doing so will cause the partition(s) to be compiled from scratch in the next compilation. You will not be able to undo the operation.
ID:230004 Partition(s) have an imported Quartus Prime Exported Partition File. Do you want to delete them?
ID:230005 Unable to delete at least one file
ID:230006 Unable to create a partition for the entity instance "<name>". View the message in the System tab of the Messages window for details.
ID:230007 Entity instance "<name>" is already set as a partition. Please revise your selection and try again.
ID:230008 Another partition is already using the name "<name>". Please specify another name.
ID:230009 You must select an entity instance
ID:230010 Unable to delete the partition named "<name>". View the message in the System tab of the Messages window for details.
ID:230011 Partition named "<name>" can no longer be found. It may have been deleted.
ID:230012 Unable to set the Netlist Type to "<netlist_type>" for the partition named "<name>". View the message in the System tab of the Messages window for details.
ID:230013 Unable to set the strict mode to "<mode>" for the partition named "<name>". View the message in the System tab of the Messages window for details.
ID:230014 Unable to set the input persona to "<mode>" for the partition named "<name>". View the message in the System tab of the Messages window for details.
ID:230015 Unable to set the allow multiple personas to "<mode>" for the partition named "<name>". View the message in the System tab of the Messages window for details.
ID:230016 Unable to set the preservation level to "<type>" for the partition named "<name>". View the message in the System tab of the Messages window for details.
ID:230017 Unable to set the preserve high-speed tiles setting to "<mode>" for the partition named "<name>". View the message in the System tab of the Messages window for details.
ID:230018 Unable to set the Color for the partition named "<name>". View the message in the System tab of the Messages window for details.
ID:230019 Unable to rename the partition from "<name>" to "<new_name>". View the message in the System tab of the Messages window for details.
ID:230020 Unable to change the settings of one or more design partitions. View the message in the System tab of the Messages window for details.
ID:230021 Unable to save assignments. View the message in the System tab of the Messages window for details.
ID:230022 You must perform Analysis and Elaboration before creating a partition
ID:230023 Listing name and arguments for command quartus_cdb <name> -c <name> --incremental_compilation_import
ID:230024 Can't import design partition. The command does not support the current device family.
ID:230025 Operation is disallowed while a compilation is in progress
ID:230026 Unable to export the selected partition because it cannot be found in the database. Recompile the project, then retry the operation.
ID:230027 Operation requires that incremental compilation is enabled
ID:230028 The path specified for the design partition export file is invalid. The path must not be too long or contain invalid characters, and the filename must end in a .qxp extension.
ID:230029 <name> already exists. Do you want to replace it?
ID:230030 File name is illegal. Ensure file name is legal and the file exists.
ID:230031 At least one partition must be selected
ID:230032 At least one error has occurred during importation. View the message in the System tab of the Messages window for details.
ID:230033 You must perform Analysis and Elaboration before importing
ID:230034 Perform incremental compilation before starting exportation
ID:230035 Unable to read import file at specified location -- see messages in System tab of Messages window for details
ID:230036 Can't perform partition import. See messages in System tab of Messages window for details.
ID:230037 Successfully imported <number> design partition(s)
ID:230038 No previous import file is associated with the partition "<name>". You cannot re-import a partition not imported before. No importation is performed.
ID:230039 Specify a virtual pin delay value.
ID:230040 Output directory "<name>" does not exist. Do you want to create it?
ID:230041 Could not create directory "<name>"
ID:230042 Bottom-up design partition scripts created successfully.
ID:230043 Can't generate bottom-up design partition scripts while a compilation is in progress
ID:230044 Can't generate bottom-up design partition scripts -- the command does not support the current device family
ID:230045 You must place and route the design before generating bottom-up design partition scripts
ID:230046 Bottom-up design partition script generation failed. View the message in the System tab of the Messages window for details.
ID:230047 Operation requires incremental compilation to be enabled
ID:230048 Invalid virtual pin delay "<name>".
ID:230049 Unable to merge the selected partitions. You can merge only partitions that are under the same parent partition
ID:230050 Unable to split partition "<name>" unless the child multi hierarchy partition "<name>" is split first. This restriction is to ensure that all hierarchies within a multi hierarchy partition are under a common partition
ID:230051 The device family does not support "Rapid recompile"
ID:231000 The device or device family does not support Logic Lock regions
ID:231001 The device or device family does not support exclusion of design elements by type
ID:231002 Unable to load Logic Lock region assignments. Either there is no open project, or the Quartus Prime Settings File for the project is corrupted or missing.
ID:231003 Unable to save the Logic Lock region assignments to storage. View the message in the System tab of the Messages window for details.
ID:231004 You must save any pending changes before performing the requested action. Click OK to save the changes now, or click Cancel to cancel the requested operation without saving the changes.
ID:231005 Are you sure that you want to delete the selected Logic Lock region member(s)?
ID:231006 Are you sure that you want to delete the security assignments of the selected signal(s)?
ID:231007 The selected signals are not associated with any security assignments. No operation will be performed.
ID:231008 The Logic Lock region named "<name>" can no longer be found. It may have been deleted.
ID:231009 The estimated size of the region(s) may be invalid when the location is set to locked. If you continue, the State property of the selected regions will be set to Floating. Do you want to continue with the action?
ID:231010 Unable to create a Logic Lock region with name "<name>". View the message in the System tab of the Messages window for details.
ID:231011 Unable to rename the Logic Lock region from "<name>" to "<new_name>". View the message in the System tab of the Messages window for details.
ID:231012 Unable to assign the Logic Lock region "<name>" a new parent "<name>". View the message in the System tab of the Messages window for details.
ID:231013 Are you sure that you want to delete the selected Logic Lock region and its descendants?
ID:231014 Unable to delete the Logic Lock region named "<name>". View the message in the System tab of the Messages window for details.
ID:231015 Are you sure that you want to merge the selected <region> to become a single region?
ID:231016 Unable to merge the Logic Lock regions. View the message in the System tab of the Messages window for details.
ID:231017 The width and height of a Logic Lock region must be positive integers
ID:231018 Unable to change the size for the Logic Lock region named "<name>" to <value>. View the message in the System tab of the Messages window for details.
ID:231019 Unable to change the width of the Logic Lock region named "<name>" to <value>. View the message in the System tab of the Messages window for details.
ID:231020 Unable to change the height of the Logic Lock region named "<name>" to <value>. View the message in the System tab of the Messages window for details.
ID:231021 Unable to change the State of the Logic Lock region named "<name>" to <value>. View the message in the System tab of the Messages window for details.
ID:231022 Location <name> is not a legal origin for a Logic Lock region.
ID:231023 Unable to change the Origin for the Logic Lock region named "<name>" to "<value>". View the message in the System tab of the Messages window for details.
ID:231024 Unable to change the Reserved property for the Logic Lock region named "<name>" to <value>. View the message in the System tab of the Messages window for details.
ID:231025 Unable to change the Enabled property for the Logic Lock region named "<name>" to <value>. View the message in the System tab of the Messages window for details.
ID:231026 This operation is not supported for regions with a custom shape
ID:231027 This operation is not supported for security routing interface "<name>"
ID:231028 Unable to change the security level property for the Logic Lock region named "<name>" to "<value>". View the message in the System tab of the Messages window for details.
ID:231029 Unable to change the security routing interface property for the Logic Lock region named "<name>" to "<value>". View the message in the System tab of the Messages window for details.
ID:231030 Unable to change the partial reconfiguration property for the Logic Lock region named "<name>" to "<value>". View the message in the System tab of the Messages window for details.
ID:231031 Unable to set security level of signal "<name>" to "<name>". View the message in the System tab of the Messages window for details.
ID:231032 Unable to assign signal "<name>" to Logic Lock region "<name>" to act as a security routing interface. View the message in the System tab of the Messages window for details.
ID:231033 Unable to assign "<name>" to Logic Lock region "<name>". View the message in the System tab of the Messages window for details.
ID:231034 At least one error has occurred while setting the priority of Logic Lock region members. View the message in the System tab of the Messages window for details.
ID:231035 Logic Lock region "<name>" no longer has any members. Do you also want to delete the empty Logic Lock region? (Yes is recommended)
ID:231036 "<name>" is currently assigned to Logic Lock region "<name>". Do you want to reassign this entity to another Logic Lock region?
ID:231037 "<name>" is already assigned to a Logic Lock region "<name>". Do you want to reassign this entity to a new Logic Lock region?
ID:231038 Unable to change the settings of one or more Logic Lock regions. View the message in the System tab of the Messages window for details.
ID:231039 Can't perform the operation while a compilation is in progress
ID:231040 Can't perform the operation without compiling the design
ID:231041 Can't perform the operation when the selected device is set to Auto
ID:231042 Can't perform the operation until after performing Analysis, Synthesis and Partition Merge
ID:231043 Do you also want to set the size and the origin of the selected region hierarchies to previous Fitter results? (Yes is recommended)
ID:231044 Do you also want to set the origin and the size of the selected region hierarchies to previous Fitter results? (Yes is recommended)
ID:231045 Before the regions can be resized, the region hierarchies must be converted to have a fixed size and a locked origin using previous Fitter results. Do you want to proceed? (Yes is recommended)
ID:231046 Before the regions can be moved, the region hierarchies must be converted to have a fixed size and a locked origin using previous Fitter results. Do you want to proceed? (Yes is recommended)
ID:231047 You are trying to preserve previous Fitter results; however, at least one Logic Lock region has the Size and/or State property set to Auto and/or Floating. Do you want to set the size and origin of all Logic Lock regions to previous Fitter results? (Yes is recommended)
ID:231048 Updated the size and origin of <name> Logic Lock region(s) to match previous Fitter results.
ID:231049 Updated the size and origin of <name> Logic Lock regions to match previous Fitter results. <name> regions were unchanged either because they are already up-to-date, or they have not been compiled.
ID:231050 No change was made - the selected Logic Lock regions may not have previous Fitter results because they have not been compiled.
ID:231051 Can't perform the size estimation for the Logic Lock region when the device is set to Auto
ID:231052 Can't perform the size estimation for the Logic Lock region because the current device has been changed since the last compilation
ID:231053 Device family does not support size estimation for the Logic Lock region
ID:231054 Updated the size of <number> regions to the estimated values
ID:231055 Updated the size of <number> regions to the estimated values. <number> regions are set to Auto and Floating because an estimation is not available.
ID:231056 Do you also want to delete all the descendants of the back-annotated assignments? (Yes is recommended)
ID:231057 Export focus contains an illegal character -- specify an export focus containing only legal characters
ID:231058 Export focus is invalid -- specify a valid export focus
ID:231059 Specify an export focus
ID:231060 Specify a file name
ID:231061 Can't export assignments to file <name> in current project directory -- specify a different directory
ID:231063 Can't export assignments before analyzing a design
ID:231064 Directory "<name>" does not exist. Do you want to create it?
ID:231065 Specify a Verilog Quartus Mapping File name
ID:231066 Can't create Verilog Quartus Mapping File <name> in project directory
ID:231067 Specifies the size of the region as chosen by the Fitter in the previous compilation. If the size of the region is "Auto", the Fitter may not reuse the same size in the next compilation. If you are satisfied with the settings determined by the Fitter, it is recommended that you preserve the size and location of the region by using the "Set Size and Origin to Previous Fitter Results" command.
ID:231068 The size of the region is "Auto". The width and height will remain undetermined until a full compilation is performed.
ID:231069 Specifies the size of the region.
ID:231070 Specifies the origin of the region as chosen by the Fitter in the previous compilation. If the state of the region is "Floating", the Fitter might not reuse the same origin in the next compilation. If you are satisfied with the settings determined by the Fitter, it is recommended that you preserve the size and location of the region by using the "Set Size and Origin to Previous Fitter Results" command.
ID:231071 The state of the region is "Floating". The origin will remain undetermined until a full compilation is performed.
ID:231072 Specifies the origin of the region.
ID:231073 Region has a custom shape. Edit the region size and location via the Chip Editor.
ID:233000 Can't find design entity "<name>"
ID:233001 Can't open file <name> -- file does not exist
ID:233002 Unable to change the assignments of the project -- see messages in the System tab of the Messages window for details
ID:233003 Unable to create at least one partition -- see messages in the System tab of the Messages window for details
ID:233004 Unable to remove at least one partition -- see messages in the System tab of the Messages window for details
ID:233005 Can't view encrypted file "<name>"
ID:234000 The selected I/O bank VCCIO assignment is not valid.
ID:234001 This assignment is for TX pins only.
ID:234002 This assignment is for RX pins only.
ID:234003 This assignment is for RX or TX pins only.
ID:234004 This assignment is for REFCLK pins only.
ID:234005 Board trace model assignments are not support input pins
ID:234006 Board trace model assignments are not support negative pins
ID:234007 Cannot delete negative differential pair nodes.
ID:234008 Cannot assign single-ended I/O standard on the negative node.
ID:234009 Pin Planner can't locate the specified object.
ID:234010 Finished searching.
ID:234011 Finished searching. Can't find '<name>'.
ID:234012 Reached the start of the document. Do you want to continue searching from the end?
ID:234013 Reached the end of document. Do you want to continue searching from the start?
ID:234014 Can't locate node or entity in design file
ID:234016 Fitter assignments are not available. Check the report file.
ID:234017 Can't paste all values because some of the values are read-only
ID:234018 Can't paste all values because some of the values are illegal
ID:234019 Can't paste all values because they are illegal, read-only, or the same values as the original ones
ID:234020 Can't delete empty value
ID:234021 Can't delete inherited value
ID:234022 Can't delete bus bit
ID:234023 Can't delete a Fitter-generated node
ID:234024 Node name not specified
ID:234025 Can't specify existing node name
ID:234026 Can't edit more than one node name at the same time
ID:234027 Can't edit items in different columns
ID:234028 Can't make this device specific assignment
ID:234029 Create a new node name first before making assignments
ID:234030 This is a read-only item
ID:234031 Can't change the location for assignable pins
ID:234032 Can't assign a differential pair node to a non-differential node
ID:234033 Can't edit a fitter generated node name
ID:234034 Can't edit bus bit name
ID:234035 Can't edit the current device because the device is a read-only
ID:234036 Node is currently assigned to <name>. Are you sure that you want to make the change?
ID:234037 Can't change this Enable field because there is no location assignment
ID:234038 Differential pair nodes can neither be a group nor a bus
ID:234039 <name> is a differential pair of another node already
ID:234040 Differential pair nodes need to have the same I/O standard. Do you want to change the I/O standard of <name> to <name>?
ID:234041 Differential pair nodes cannot be the same nodes as themselves
ID:234042 Slew rate assignments are intended for only output or bidirectional nodes
ID:234043 Can't create node <name>
ID:234044 Node names cannot have spaces in between
ID:234045 Finding swappable pins requires live I/O check enabled. Do you want to enable live I/O check?
ID:234046 Can't delete read-only information
ID:234047 Live I/O check is OFF
ID:234048 Live I/O check has stopped due to an error
ID:234049 When you turn on the Fitter placement, the live I/O check will be turned off
ID:234050 When you turn on the live I/O check, the Fitter placement will be turned off
ID:234051 Instance name cannot be empty
ID:234052 Can't perform auto-fill on the pin location
ID:234053 Query name <name> already exists - enter a new query name
ID:234054 <name> is an illegal instance name
ID:234055 Instance name <name> already exists
ID:234056 Are you sure that you want to change the top-level design file name from <file_name1> to <file_name2>?
ID:234057 The design file <file_name> is successfully created.
ID:234058 One or more megafunction files are created for other families. They may not work for the current device.
ID:234059 One or more megafunction files are created for other devices. They may not work for the current device.
ID:234060 Value entered is not a valid location.
ID:234061 Value entered is not a valid assignment.
ID:234062 Board trace model assignments are ignored when Advanced I/O Timing is disabled. In order to use Advanced I/O Timing, use the Timing Analyzer for timing analysis and turn on the Enable Advanced I/O Timing option on the Timing Analyzer page of the Settings dialog box.
ID:234063 Please select a megafunction .ppf file
ID:234064 Error in the megafunction file.
ID:234065 Can't export data to file <file_name>
ID:234066 Can't find the megafunction .ppf file
ID:234067 Can't read the megafunction file now.
ID:234068 Can't overwrite existing node.
ID:234069 Cannot create group node <nodename> because the name is already in use or the name is invalid.
ID:234070 Editing location assignment is not successful. <reason>.
ID:234071 Cannot open file <filename>. The file may be in use.
ID:234072 Cannot assign a node on device pins.
ID:234073 Cannot make assignment on device pins.
ID:234074 Cannot change the location for device pins.
ID:235000 Number of words is not within the range of 1 and <number>
ID:235001 Word size is not within the range of 1 and <number>
ID:235002 External text editor can be used only after you close all the opened text files in the Quartus Prime Text Editor window
ID:238000 Are you sure that you want to delete all database files? Clicking OK removes all data generated during the compilation process and cannot be undone.
ID:239000 The engine is busy processing.
ID:239001 Cannot perform request during compilation.
ID:240000 The selected non suppressible messages are not suppressed
ID:240001 You have reached the start of the messages. Do you want to continue searching from the end of the messages?
ID:240002 You have reached the end of the messages. Do you want to continue searching from the start of the messages?
ID:240003 Cannot find text <text>
ID:243000 Can't run the SSN Analyzer -- the target device does not support it
ID:243001 Do you want to stop the current process?
ID:244000 Unable to create window. The required program, quartus_sta, could not be started.
ID:244001 The Timing Analyzer (quartus_sta) has experienced an unrecoverable error. The Timing Analyzer will now close.
ID:244002 Cannot perform request while the Timing Analyzer is busy.
ID:244003 Can't perform request while the Quartus Prime software is busy
ID:244004 The SDC command <text> has been copied to the clipboard.
ID:244005 SDC commands made during the session are not automatically saved. Do you want to write an SDC file now?
ID:244007 Unable to regenerate report panel '<panel_name>'
ID:244008 <filename> already exists. Do you want to replace it?
ID:244009 The specified file <filename> can't be opened
ID:244010 Do you want to continue and override the existing conditions?
ID:245000 EDA RTL Simulation not available.
ID:245001 EDA Gate-Level Simulation not available.
ID:245003 Cannot start I/O assignment analysis. Target device does not support I/O assignment analysis.
ID:245004 Cannot analyze and generate messages for current design. Target device is not supported.
ID:245005 Specify EDA Tool options to generate output files before running the EDA Netlist Writer
ID:245006 Tasks updated with settings changed during processing
ID:245007 You changed settings while running tasks from the Tasks Window. One or more tasks may fail due to the settings change. If tasks fail, restart the tasks.
ID:245008 Analysis & Synthesis was skipped because top-level entity is undefined.
ID:245009 Design Assistant will run in Post-Fitting mode since the Fitter completed successfully
ID:245010 <string> has already run successfully. Do you want to run the task again?
ID:245011 No simulation input file assignment specified on the Simulator page of the Settings dialog box
ID:245012 Specify a custom flow name
ID:245013 No tasks selected. Click on tasks to include in the custom flow.
ID:245014 The custom flow contains one or more folders with no tasks. Continue to save anyway?
ID:245015 Invalid file "<string>". Add Tcl script files (.tcl) only.
ID:245016 Duplicate flow name "<string>". Specify a unique name.
ID:245017 Specify a Tcl script task name.
ID:245018 Specify a Tcl script file name for the task named "<string>".
ID:245019 Flow name "<name>" is illegal. Specify another name.
ID:245020 Successfully loaded and ran Tcl script <name>.
ID:245021 Failed to run Tcl script <name>. <name>
ID:251000 Do you want to save changes to the assignments?
ID:251001 <text>
ID:251002 Can't recognize value <text> as a legal integer -- specify a legal integer
ID:251003 Can't recognize value <text> as a legal floating point number -- specify a legal floating point number
ID:251004 Illegal location assignment
ID:251005 Can't recognize value <text> as a legal location -- specify a legal location
ID:251006 Can't recognize value <text> as a legal location -- specify a legal target device before making location assignments
ID:251007 Can't recognize <text> as a legal <parameter name>=<value> assignment -- specify a legal parameter assignment
ID:251008 Specified integer <text> is out of range -- the valid range is <text> - <text>
ID:251009 Can't create assignment -- can't write to Quartus Prime Settings File
ID:251010 Can't create assignment -- can't write to Quartus Prime Settings File
ID:251011 Can't remove assignment -- can't find assignment
ID:251012 Messages generated during save -- see messages in the System tab of the Messages window
ID:251013 New assignment cannot be created -- see messages in the System tab of the Messages window
ID:251014 Some assignments have problems -- see messages in the System tab of the Messages window for details. Do you want to continue to save anyway?
ID:251015 Can't save incomplete assignment -- error: <text>
ID:251016 Cannot save incorrect assignment -- error: <text>
ID:251017 Assignment details: Assignment Name: <name>; Value: <text>; From: <name>; To: <name>; Enabled: <Yes/No>; Comment: <text>
ID:251018 Assignment details: Assignment Name: <name>; Value: <text>; From: <name>; To: <name>; Entity: <name>; Enabled: <Yes/No>; Comment: <text>
ID:251019 Can't save assignment -- assignment already exists
ID:251020 Can't list I/O standards for Auto devices
ID:251021 Can't edit locations for Auto devices
ID:251022 Unable to determine the element type
ID:251023 Assignments have been reloaded in the Assignment Editor
ID:251024 Assignments have been changed outside the Assignment Editor. Do you want to save the changes before reloading the assignments? If you save the changes, you may overwrite some or all of the external changes.
ID:251025 There are no assignments to export
ID:251026 There is no project opened
ID:252000 Can't create Verilog Quartus Mapping File <name> in project directory
ID:252001 Specify a Signal Tap File name
ID:252002 File "<name>" is not a valid Signal Tap File
ID:252003 Can't export project database -- can't create version-compatible database files in current project directory or db directory
ID:252004 Time value is illegal
ID:252005 The HDL message ID is illegal. Enter an ID between <min> and <max>
ID:252006 Project directory is empty. Specify a project output directory.
ID:252007 You enabled or disabled the following Design Assistant rules: <text> but at least one of the rules contains an illegal value
ID:252008 Maximum number of processors is illegal. Enter a value greater than 0.
ID:252010 Signal Activity File name is missing. Use default <name>?
ID:252011 VCD file name is missing. Use default <name>?
ID:252012 Entity is missing. Use root entity <name>?
ID:252013 Time value in <name> box is illegal
ID:252014 You included both the root entity and a sub-entity. The Power Input File will be applied to only the sub-entity. Okay to remove the root entity '<root entity name>'?
ID:252015 Input Files are missing. Click on the Add button to add input files.
ID:252016 The Output file name is missing
ID:252017 The heat sink-to-ambient value is missing
ID:252018 Junction temperature value is missing
ID:252019 Invalid junction temperature. Enter a value between <min> and <max>
ID:252020 The case-to-heat sink value is missing
ID:252021 The case-to-heat sink value is invalid
ID:252022 The junction-to-case value is missing
ID:252023 The junction-to-case value is invalid
ID:252024 The heat sink-to-ambient value is invalid
ID:252025 Ambient temperature value is missing
ID:252026 Invalid ambient temperature. Enter a value between <min> and <max>
ID:252027 The junction-to-board value is missing
ID:252028 The junction-to-board value is invalid.
ID:252029 Board temperature value is missing
ID:252030 Invalid board temperature. Enter a value between <min> and <max>
ID:252031 Invalid PCB layer thickness '<PCB layer thickness>'. Enter a valid numeric value greater than zero.
ID:252033 Invalid timing delay requirement
ID:252034 fMAX must be greater than zero
ID:252035 Invalid default fmax value entered. Enter value that produces a legal period value
ID:252036 Can't save timing changes
ID:252037 One or more clock settings are derived from the absolute clock settings "<name>". Deleting the absolute clock settings also deletes all derived clock settings
ID:252038 Invalid required fmax value entered. Enter value that produces a legal period value
ID:252039 Specify a clock settings name
ID:252040 Clock settings "<name>" already exists
ID:252041 Duty cycle must be between 1 and 99
ID:252042 Clock phase must be between -360 degrees and 360 degrees
ID:253000 No devices installed
ID:253001 Device family selection has changed. Do you want to remove all location and I/O standard assignments?
ID:253002 Intel recommends removing all location assignments when changing the device. Do you want to remove all location and I/O standard assignments?
ID:253003 Current migration devices not compatible with device selection -- select new migration devices?
ID:253004 Device selection has changed -- previous device and new device have similar pin-outs. Do you want to use pin locations from the previous device in the new device?
ID:253005 Speed grade of target device is different from speed grade of previously selected migration device
ID:253006 Project contains illegal migration devices, <devices> for the current device <device>. Okay to delete migration devices?
ID:253007 Project contains incompatible migration devices, <devices> for the current device <device>. Okay to delete migration devices?
ID:253008 Selected target device <device> is illegal or not supported in this version of the Quartus Prime software. Okay to delete migration devices?
ID:253009 Can't find device that meets specifications - selecting auto device
ID:253010 Quartus Prime Settings File contains an illegal device <name> -- using default device instead
ID:253011 Quartus Prime Settings File contains an illegal device family <name> -- using default device family <name>
ID:253014 Project contains incompatible companion device. Companion device will be removed
ID:253015 Changing the device resets the core voltage and junction temperature range to the default values for the new device. To set the core voltage to a different value, go to the Voltage page. To set the junction temperature range to a different value, go to the Temperature page.
ID:253016 Changing the configuration scheme reverts dual-purpose pins assignments to default values consistent with the new configuration scheme.
ID:253017 Selected device <name> is supported in current version of the Quartus Prime software, but support for the device is not installed -- select an installed device
ID:253018 The migration devices, <devices> cannot migrate to each other. Only one of the devices can be included in the list of migration devices.
ID:253019 Value <name>, value, <value>, are illegal. Enter a legal value or leave it blank to set to the default value.
ID:253020 Default device <name> is automatically selected for the device family <name>
ID:254000 Select a simulation tool
ID:254003 Select at least one device family
ID:254004 Select at least one library language package
ID:254005 Specify an output directory for the compiled library
ID:254006 Output directory "<path>" doesn't exist. Do you want to create it?
ID:254007 Failed to create the directory "<name>"
ID:254008 Compilation was successful: (<number> warnings)
ID:254009 Compilation was not successful: (<number> errors, <number> warnings)
ID:254010 Compilation was stopped: (<number> errors, <number> warnings)
ID:254011 <text>
ID:255000 EDA Tool Category for <name> has changed to <name>
ID:255001 Ignoring illegal EDA <name> tool name <name>
ID:255002 Detected Obsolete <name> NativeLink Settings, migrating to test bench settings <name>
ID:255003 Removing Obsolete assignment <name> currently set to value <name>
ID:255004 Using <name> as testbench setting for NativeLink Simulation
ID:256000 Can't import Comma-Separated Value File. Use the logiclock_import Tcl command to import the CSV File.
ID:256001 Can't find file or file type is not supported -- cannot import file
ID:256002 Can't import current Quartus Prime Settings File
ID:257000 Specify a design instance name
ID:257001 Specify a script to set up simulation.
ID:257002 Cannot find script <name>
ID:257003 Specify a test bench name
ID:257004 The design instance name, <name>, in Options for Power Estimation box does not match the instance name, <name>, specified in your test bench. The Value Change Dump file (VCD) file generated using NativeLink simulation will not be accurate.
ID:257005 Specify a <type> file name
ID:257006 Cannot find test bench file <name>
ID:257007 Cannot find command script file <name>
ID:257008 Cannot compile test bench when no test bench is specified. Click Test Benches to create a test bench.
ID:257009 Specify a test bench entity name
ID:257011 The test bench <name> already exist. Specify another name.
ID:257012 Specify a signal name for VCC
ID:257013 Specify a signal name for GND
ID:258000 File "<name>" is not a valid Logic Analyzer Interface Editor file
ID:258001 Specify a Logic Analyzer Interface Editor file name
ID:258002 No files were added from the working directory
ID:259000 Not all nodes could be added
ID:259001 The following nodes could not be added:
ID:259002 Node "<name>"
ID:259003 Can't monitor the following nodes
ID:259004 Node "<name>"
ID:259005 Invalid JTAG Configuration
ID:259006 Ready
ID:259007 Not connected
ID:259008 Pins tri-stated
ID:259009 Invalid hardware
ID:259010 Invalid device
ID:259011 Instance not found
ID:259012 Version not supported
ID:259013 Incompatible instance
ID:259014 JTAG configuration error
ID:259015 <name> connected
ID:259016 JTAG ready
ID:259017 Acquisition in progress
ID:259018 Looking for devices
ID:259019 Programming device
ID:259020 No device is selected
ID:259021 No devices detected
ID:259022 Selected device not found
ID:259023 JTAG communication error
ID:259024 Reached start of document. Do you want to continue searching from end of document?
ID:259025 Reached end of document. Do you want to continue searching from start of document?
ID:259026 Finished searching the document
ID:259027 Finished searching document. Can't find searched text.
ID:259028 Do you want to enable Logic Analyzer Interface File "<name>" for the current project?
ID:259029 Logic Analyzer Interface is not supported for the currently selected device
ID:259030 Editing the State Clock node is not allowed. In the Registered/State mode, the first node of each bank is reserved for the State Clock node.
ID:259031 One or more instances is missing the Clock Core Parameter which is required in the Registered/State Output/Capture mode.
ID:259032 Invalid Logic Analyzer Interface File "<name>"
ID:260000 JTAG ready
ID:260001 Acquisition in progress
ID:260002 Looking for devices
ID:260003 Programming device
ID:260004 No device is selected
ID:260005 No devices detected
ID:260006 Selected device not found
ID:260007 JTAG communication error
ID:260008 No instances found in the current project or on the device
ID:260009 Unexpected JTAG communication error
ID:260010 Unloading data
ID:260011 Not running
ID:260012 File corrupted
ID:260013 Waiting for JTAG
ID:260014 JTAG configuration invalid
ID:260015 Acquisition in progress
ID:260016 Ready to acquire
ID:260017 Updating memory
ID:260018 Version not supported
ID:260019 Instance version mismatch
ID:260020 Invalid JTAG hardware
ID:260021 Invalid data received
ID:260022 JTAG communication in use
ID:260023 Instance not found
ID:260024 Not compatible with the device
ID:261000 <tcl command>
ID:261001 Previous TCL command has been repeated <tcl command> times.
ID:261002 Can't engage JTAG communication. Select correct communications cable and device.
ID:261003 Can't continue the established JTAG communication. Reconnect communications cable and device.
ID:261004 Version of entity "<name>" is not supported in current version of Quartus Prime software
ID:261005 Can't find the instance. Download a design with SRAM Object File containing this instance.
ID:261006 Can't engage JTAG communication. Stop other activities on communications cable and circuit board.
ID:261007 JTAG communication error. Check hardware setup.
ID:261008 Can't acquire data from unknown node instance "<name>" with manufacture ID <id> and node type ID <id>
ID:261009 Cannot run Signal Tap Logic Analyzer. Signal Tap File is not compatible with the file programmed in your device. The expected compatibility checksum value is <value>; the value read from your device is <value>
ID:261010 Can't run Signal Tap Logic Analyzer -- instance "<name>" contains advanced trigger condition with one or more errors
ID:261011 Signal Tap instance version on device is different from current instance defined in the Signal Tap File
ID:261012 Can't acquire data for all of the specified instances
ID:261013 Instance <name> current status:
ID:261014 Flag resource <name> value: <number>
ID:261015 Counter resource <name> value: <number>
ID:261016 Flow control state: <name>
ID:261017 Can't acquire data, version <number> of In-System Memory Content Editor instance is not supported in current version of the Quartus Prime software
ID:261018 The modifiable node at index <index> cannot be found
ID:261019 The modifiable node at index <index> is reprogrammed, or another program that accesses this node at the same time has been stopped
ID:261020 The modifiable node at index <index> had been accessed by another program
ID:261021 Logic Analyzer Interface instance version on device is not supported in current release of Quartus Prime software
ID:261022 Can't find instance of Logic Analyzer Interface. Download a design with current SRAM Object File.
ID:261023 JTAG sources and probes instance version on device is not supported in current release of Quartus Prime software
ID:261024 Can't find instance of sources and probes. Download a design with current SRAM Object File.
ID:261025 Instance <number> of sources and probes does not match the configuration of the instance programmed in the device which has <number> source(s) and <number> probe(s)
ID:262000 Can't compile project with Signal Tap instance "<name>" -- current Quartus Prime software version requires Signal Tap IP version <number>, but Signal Tap instance uses Signal Tap IP version <number>
ID:262001 Signal Tap data acquisition is in <type> state: <text>
ID:262002 Current trigger condition is not compatible with the last compilation result in instance "<name>"
ID:262003 Trigger condition <type>
ID:262004 Ignoring Signal Tap instance "<name>" with signal set <name>
ID:262005 Can't acquire data multiple times on Signal Tap instance "<name>" when acquiring data from multiple instances simultaneously
ID:262006 File "<name>" is not a valid Signal Tap File -- ignoring
ID:262007 File "<name>" is not a valid Logic Analyzer Interface file. It is being ignored.
ID:262008 Device family <family> does not <feature>
ID:262009 Can't open Signal Tap Logic Analyzer. Verify that the license file exists and is stored in the correct location. If you are using the Quartus Prime Lite Edition software, you must turn on the TalkBack feature to use the Signal Tap Logic Analyzer.
ID:262010 Specify a project for Signal Tap Logic Analyzer
ID:262011 Project name specified for Signal Tap Logic Analyzer contains illegal character \'<name>\'
ID:262012 Project directory "<name>" specified for Signal Tap Logic Analyzer does not exist
ID:262013 Project name "<name>" specified for Signal Tap Logic Analyzer contains illegal characters
ID:262014 Project name "<name>" specified for Signal Tap Logic Analyzer not found
ID:262015 Signal Tap Logic Analyzer top-level entity "<name>" contains illegal characters
ID:262016 Can't find Signal Tap Logic Analyzer top-level entity "<name>"
ID:262017 Can't find Signal Tap megafunction in project "<name>"
ID:262018 File name must be specified for Signal Tap File
ID:262019 Equivalent device ir and dr shift commands
ID:262020 <command>
ID:262021 No editable memory instance was found.
ID:262022 <purpose> - Command: quartus_stp <command line option>
ID:264000 JTAG ready
ID:264001 Acquisition in progress
ID:264002 Looking for devices
ID:264003 Programming device
ID:264004 No device is selected
ID:264005 No devices detected
ID:264006 Selected device not found
ID:264007 JTAG communication error
ID:264008 Not running
ID:264009 Unloading data
ID:264010 Updating memory
ID:264011 JTAG configuration invalid
ID:264012 Version not supported
ID:264013 Instance version mismatch
ID:264014 Invalid JTAG hardware
ID:264015 Invalid data received
ID:264016 JTAG communication in use
ID:264017 Instance not found
ID:264018 Unexpected JTAG communication error
ID:264019 Not compatible with the device
ID:264020 No instances found
ID:264021 Ready to acquire
ID:264022 Acquisition in progress
ID:264023 Waiting for JTAG
ID:265000 Debug node with entity name "<name>" instance name "<name>" defines parameter name <name>, but parameter must be numerical type
ID:265001 Debug node with entity name "<name>" and instance name "<name>" has duplicate ID <number> -- node ID is used by another node
ID:265002 Two instances "<name>" and "<name>" of the same debug node with entity name "<name>" have the same instance index <number>.
ID:265003 Specified instance index of <hierarchical path> has been used by another instance of the same entity that utilizes the JTAG interface. Instance index must be unique in a design. Index has been changed from <id> to <id>.
ID:265004 Number of system-level debug node instances in your project exceeds 255 while analyzing, <name>
ID:265005 Parameter SLD_NODE_INFO of instance "<name>" of the debug node "<name>" is set to an invalid value
ID:265007 On the System-level debug node, "<name>", ir_in/ir_out ports width exceeds the limit of 32-bit wide.
ID:265008 On the System-level debug node, "<name>", ir_in/ir_out ports width exceeds the limit of 24-bit wide.
ID:265009 Can't compile project with Signal Tap instance "<name>" in unsupported Signal Tap IP version <number>. Current Signal Tap IP version is <number>.
ID:265010 Current project contains Signal Tap IP VHDL design files copied from different version of Quartus Prime software
ID:265011 Current project contains In-System Memory Content Editor IP VHDL design files copied from different version of the Quartus Prime software
ID:265012 Current project contains Logic Analyzer Interface VHDL Design Files copied from different version of Quartus Prime software
ID:265013 Can't open Signal Tap Logic Analyzer. Verify that the license file exists and is stored in the correct location. If you are using the Quartus Prime Lite Edition software, you must turn on the TalkBack feature to use the Signal Tap Logic Analyzer.
ID:265014 Trigger "<name>" in instance "<name>" at advanced trigger level <number> contains syntax error at <word>
ID:265015 Can't save or compile Signal Tap File -- operand "<name>" of logical operator <name> must be a Boolean expression
ID:265016 Can't save or compile Signal Tap File -- advanced trigger expression is not a Boolean expression but must be a Boolean expression
ID:265017 Can't save or compile Signal Tap File -- operator <name> requires operands with identical output widths, but operand "<name>" output width differs from operand "<name>" output width
ID:265018 Can't save or compile Signal Tap File -- pattern length in function "<name>" does not match operand <name> output width <number>
ID:265019 Pattern match string in function "<name>" contains illegal characters
ID:265020 Can't save or compile Signal Tap File. Shift operator <name> has width <number>, but shift amount is <number> -- shift amount cannot be greater than width.
ID:265021 Input signal "<name>" cannot be used in advanced trigger condition because signal does not exist in signal set and/or is not used as trigger input
ID:265022 Can't save or compile Signal Tap File -- output bus width <number> cannot represent numerical expression "<name>" with value <number>
ID:265023 Can't save or compile Signal Tap File -- operator <name> has only numerical operands but must have at least one non-numeric operand
ID:265024 Operator <name> cannot have numerical operands
ID:265025 Can't save or compile Signal Tap File -- advanced trigger condition in Advanced Trigger Level <number> of trigger "<name>" in instance "<name>" contains semantic error(s)
ID:265026 Condition for Incrementally Routed Nodes object "<name>" has input "<name>" which is not incrementally routed
ID:265027 Condition for Incrementally Routed Nodes object "<name>" has too many input nodes. There are <number> input nodes, but Condition for Incrementally Routed Nodes object "<name>" can accept only <number> incrementally routed nodes
ID:265028 Can't save or compile Signal Tap File -- input "<name>" of Event Counter object "<name>" must be a Boolean expression
ID:265029 Can't save or compile Signal Tap File -- Event Counter object "<name>" has width <number>, but width must be integer value between 1 and 32
ID:265030 Can't save or compile Signal Tap File -- Event Counter object "<name>" has count value of <number>, but count value must be an integer value between 1 and 2^width - 1
ID:265031 Event Counter object "<name>" has delay of <number>, but delay value must be at least 1. Event Counter object delay will default to 1.
ID:265032 Trigger flow control description error in Signal Tap instance <name> line <number>: Syntax error before the token "<word>".
ID:265033 Trigger flow control description error in Signal Tap instance <name> line <number>: comment is not closed with "*/".
ID:265034 Trigger flow control description error in Signal Tap instance <name> line <number>: Value <number> exceeds the maximum limit of <number> bits.
ID:265035 Trigger flow control description error in Signal Tap instance <name> line <number>: Negative number <number> is not allowed. Only positive numbers are allowed.
ID:265036 Trigger flow control description error in Signal Tap instance <name> line <number>: Initial counter value <number> exceeds the counter width of <number> bits.
ID:265037 Trigger flow control description error in Signal Tap instance <name> line <number>: Unknown reference, "<name>", to any resources, such as flag, counter, or condition.
ID:265038 Trigger flow control description error in Signal Tap instance <name> line <number>: State name "<name>" has already been used.
ID:265039 Trigger flow control description error in Signal Tap instance <name> line <number>: Non-Boolean operand is used in the logical operator.
ID:265040 Trigger flow control description error in Signal Tap instance <name> line <number>: Compare two variables, <name> and <name>, of different width.
ID:265041 Trigger flow control description error in Signal Tap instance <name> line <number>: Compare two values.
ID:265042 Trigger flow control description error in Signal Tap instance <name> line <number>: State <name> cannot be reached
ID:265043 Trigger flow control description error in Signal Tap instance <name> line <number>: More than one state transition action (goto) is used within a single action list block.
ID:265044 Trigger flow control description error in Signal Tap instance <name> line <number>: More than one trigger action is used within a single action list block.
ID:265045 Trigger flow control description error in Signal Tap instance <name> line <number>: More than one counter action is applied to the same counter, <name>, within a single action list block.
ID:265046 Trigger flow control description error in Signal Tap instance <name> line <number>: More than one flag action is applied to the same flag, <name>, within a single action list block.
ID:265047 Trigger flow control description error in Signal Tap instance <name> line <number>: No trigger action is found. The acquisition will not stop.
ID:265048 Trigger flow control description error in Signal Tap instance <name> line <number>: No trigger action is reachable. The acquisition will not stop.
ID:265049 Trigger flow control description error in Signal Tap instance <name> line <number>: Acquisition memory segment action is used without configuring multiple segments.
ID:265050 Trigger flow control description error in Signal Tap instance <name> line <number>: Missing <token> before '<token>'.
ID:265051 Trigger flow control description error in Signal Tap instance <name> line <number>: No valid state machine body is defined.
ID:265052 Trigger flow control description error in Signal Tap instance <name> line <number>: Non-Boolean operand is specified on the <operand side> of logical operator <logical operator>.
ID:265053 Trigger flow control description error in Signal Tap instance <name> line <number>: Invalid type is used on the <operand side> of the comparison operator <logical operator>.
ID:265054 Trigger flow control description error in Signal Tap instance <name> line <number>: Multiple action statements are not enclosed by 'begin' and 'end'.
ID:265055 Trigger flow control description error in Signal Tap instance <name> line <number>: No start_store action is specified in the state-based start and stop storage qualifier mode. No sample will be saved.
ID:265056 Trigger flow control description error in Signal Tap instance <name> line <number>: either start_store or stop_store action is specified when not in the state-based start and stop storage qualifier mode. This action is ignored
ID:265057 Intel FPGA IP Evaluation Mode specification file "<name>" contains syntax error at line <number>
ID:265058 String on line number <number> in Intel FPGA IP Evaluation Mode specification file "<name>" cannot contain back-quote (`) as leading character
ID:265059 Unterminated quoted string on line number <number> in Intel FPGA IP Evaluation Mode specification file "<name>"
ID:265060 Intel FPGA IP Evaluation Mode specification file "<name>" does not contain timeout value
ID:265061 Intel FPGA IP Evaluation Mode specification file "<name>" does not contain entity name
ID:265062 Intel FPGA IP Evaluation Mode specification file "<name>" must contain the name of the associated IP core
ID:265063 Vendor and product ID of Intel FPGA IP Evaluation Mode specification file "<name>" must match vendor and product ID of the corresponding design file
ID:265064 Intel FPGA IP Evaluation Mode specification file "<name>" targets entity "<name>", but entity "<name>" is defined in specification file
ID:265065 Intel FPGA IP Evaluation Mode is not authorized for core <name>
ID:265066 Intel FPGA IP Evaluation Mode specification file "<name>" contains an illegal port type or value "<name>"
ID:265067 Design includes illegal megafunction "<name>"
ID:265068 Current device family does not support hardware evaluation of Intel FPGA IP Evaluation Mode IP.
ID:265069 Megafunction that supports Intel FPGA IP Evaluation Mode feature will stop functioning in <time> after device is programmed
ID:265070 Evaluation period of megafunction that supports Intel FPGA IP Evaluation Mode feature can be prolonged to <time> by using tethered operation
ID:265071 Evaluation period of megafunction that supports Intel FPGA IP Evaluation Mode feature can be extended indefinitely by using tethered operation
ID:265072 Messages from megafunction that supports Intel FPGA IP Evaluation Mode feature
ID:265073 Messages from megafunction that supports Intel FPGA IP Evaluation Mode feature <name>
ID:265074 <text>
ID:265075 The megafunction, <name>, required for Intel FPGA IP Evaluation Mode hardware evaluation does not match the one supplied in this release of Quartus Prime software.
ID:265076 Specified instance index of <hierarchical path> has been used by another instance. Instance index must be unique in a design. Index has been changed from <id> to <id>.
ID:266000 Can't save export file "<name>"
ID:266001 Can't open file "<name>" for import
ID:266002 Can't save JTAG Debugging Information (.jdi) file "<name>"
ID:266003 Attribute "<name>" has invalid value "<name>". It is using default value to recover.
ID:266004 Attribute "<name>" not found. Quartus Prime software is using default attribute value to recover.
ID:266005 Element "<name>" not found. Quartus Prime software will recover with default element.
ID:266006 Element "<name>" not found. The import operation halted.
ID:267000 Quartus Prime software encountered an error while reading Signal Tap File <name>, with message "<text>"
ID:267001 Signal Tap File is not in valid format
ID:267002 Entity "<type>" doesn't have name
ID:267003 Created entity with duplicate name "<name>"
ID:267004 Signal Tap File requires signals
ID:267005 Symbol "<name>" has duplicate value "<name>" in mnemonic table "<name>" -- ignoring new value "<name>"
ID:267006 Signal "<name>" does not exist in Signal Tap File
ID:267007 Trigger condition "<name>" in Signal Tap File contains undefined bus "<name>" with symbol or value "<name>"
ID:267008 Mnemonic table "<name>" does not exist in Signal Tap File
ID:267009 Symbol "<name>" does not exist in mnemonic table "<name>"
ID:267010 Condition expression defined in trigger "<name>" at level <number> contains a syntax error -- stopping processing at string "<name>"
ID:267011 Signal "<name>" exists in signal set and is defined as an input for triggering, but advanced trigger conditions in trigger "<name>" do not use the signal
ID:267012 Attribute containing the mnemonics information on the data log, <name>, is in an incorrect format.
ID:267013 A required internal mnemonics table referenced by an attribute on the data log, <name>, is missing.
ID:268000 Cannot save to the file that is currently open in the Quartus Prime software. This file is not saved. Please save as a different file name.
ID:268001 Cannot save file. Please save as a different file name or to a different path.
ID:268002 The following post-fitting nodes may not be tappable because incremental compilation is not enabled for the project.
ID:268003 The netlist type of the partitions of the following nodes should be set to Source File.
ID:268004 The netlist type of the partitions of the following nodes should be set to Post-Fit, Post-Fit (Strict), or Post-Fit (Import-based).
ID:268005 Cannot attach SRAM Object File "<name>" -- file does not exist or cannot be read
ID:268006 Cannot extract SRAM Object File. Attached SOF in Signal Tap File is corrupt, or you do not have permission to write to SOF.
ID:268007 Node "<name>"
ID:268008 Advanced Trigger <number> in instance "<name>" is incomplete or has an error that can cause compilation errors
ID:268009 Post-fitting node "<name>"
ID:268010 Post-fitting nodes may not be tappable when incremental compilation is not enabled for the project or when you are using the web edition. See the Messages window for more information.
ID:268011 Pre-synthesis nodes should be added to partitions with a netlist type of Source File. See the Messages window for more information.
ID:268012 Post-fitting nodes should be added to partitions with a netlist type of Post-Fit, Post-Fit (Strict), or Post-Fit (Import-based). See the Messages window for more information.
ID:268013 Pre-synthesis node "<name>"
ID:268014 Post-fitting node "<name>"
ID:268015 No node assigned as clock signal -- pin generated for clock signal
ID:268016 Cannot use node "<name>" as a Trigger Out signal
ID:268018 Cannot delete an instance while acquisition is in progress
ID:268019 Signal Tap File contains an instance created in a previous version of the Quartus Prime software. You must update it to compile the current project with the STP File. If you need to acquire data from the SRAM Object File generated in a previous version, make a copy of the file. Do you want to update the file?
ID:268020 Signal Tap File contains an instance created in a newer version of the Quartus Prime software. You must use a newer version of the Quartus Prime software to open this file.
ID:268021 Cannot define signal "<name>" as both clock signal and Signal Tap signal -- removing duplicate
ID:268022 Value exceeds <width> bit(s) long when converted to binary
ID:268023 Mnemonic table must have a name
ID:268024 Mnemonic table entry must contain mnemonic name
ID:268025 Mnemonic entry must contain a value
ID:268026 Cannot delete -- no tables exist
ID:268027 Cannot create List File
ID:268028 Create an instance
ID:268029 Add nodes to the current instance
ID:268030 Invalid JTAG configuration
ID:268031 Ready to acquire
ID:268032 Not running
ID:268033 Acquisition in progress
ID:268034 Compile the project to continue
ID:268035 Start Rapid Recompile to Reroute the design
ID:268036 Program the device to continue
ID:268037 Waiting for clock
ID:268038 Acquiring pre-trigger data
ID:268039 Acquiring post-trigger data
ID:268040 Offloading acquired data
ID:268041 Waiting for trigger
ID:268042 Power-up trigger waiting for clock
ID:268043 Waiting for power-up trigger
ID:268044 Acquiring power-up pre-trigger data
ID:268045 Acquiring power-up post-trigger data
ID:268046 Offloading acquired power-up data
ID:268047 Trigger in conditions met
ID:268048 Trigger level met
ID:268049 Waiting for JTAG
ID:268050 JTAG ready
ID:268051 Acquisition in progress
ID:268052 Looking for devices
ID:268053 Programming device
ID:268054 No device is selected
ID:268055 No devices detected
ID:268056 Selected device not found
ID:268057 JTAG communication error
ID:268058 JTAG is busy. Wait until JTAG chain is available.
ID:268059 Version not supported
ID:268060 Instance version mismatch
ID:268061 Invalid JTAG hardware
ID:268062 Invalid data received
ID:268063 JTAG communication in use
ID:268064 Instance not found
ID:268065 Unexpected JTAG communication error
ID:268066 Not compatible with the device
ID:268068 Specify a maximum of 4096 nodes in a Signal Tap instance
ID:268069 Ignored duplicate name
ID:268070 Input "<type>" is empty
ID:268071 File contains no instances
ID:268072 Successfully exported data to file "<name>"
ID:268073 Cannot export data -- data log contains no data
ID:268074 One or more trigger input nodes for instance "<name>" are incrementally routed, and all Trigger Levels are set to Advanced. However, the incrementally routed trigger input nodes are not used in any of the Advanced Trigger levels. The Condition for Incrementally Routed Nodes object must be connected to the Result object in at least one Advanced Trigger level.
ID:268075 Mnemonic table "<name>" already exists. Do you want to overwrite it?
ID:268076 Setting trigger nodes allocated and data nodes allocated to manual to use Lock mode
ID:268077 Set either trigger nodes allocated or data nodes allocated to a value greater than zero to allow only incremental route changes
ID:268078 Reached start of document. Do you want to continue searching from end of document?
ID:268079 Reached end of document. Do you want to continue searching from start of document?
ID:268080 Do you want to enable Signal Tap File "<name>" for the current project?
ID:268081 Cannot find Signal Tap File "<name>"
ID:268082 Invalid Signal Tap File "<name>"
ID:268103 Signal Tap is not supported for the currently selected device
ID:268104 The Add Nodes with Plug-In command could not be completed because you need to run an Analysis and Elaboration first.
ID:268105 The Add Nodes with Plug-In command could not be completed because the nodes couldn't be added to the current design.
ID:268106 The Add Nodes with Plug-In command could not be completed because the selected IP could not be found in the current design.
ID:268107 The selected member nodes of the bus added with Plug-In command are excluded from this operation. Please select a bus node of this type only.
ID:268108 The incremental routing feature is used in this STP file. The current release of the Quartus Prime software no longer supports this feature. If the STP file contains log entries, please read the system message for all entries affected.
ID:268109 The incremental routing feature is used in the instance: <name>, the signal set: <name>, and the trigger: <name>. The current release of the Quartus Prime software no longer supports this feature.
ID:268110 Please select a bus before using the Find Bus Value command.
ID:268111 Bus data not found.
ID:268112 Bus value not found.
ID:268113 Do you want to set the netlist type of the Top partition to Source File since you are adding pre-synthesis nodes? See the Messages window for more information.
ID:268114 Do you want to set the netlist type of the corresponding partition to Source File since you are adding pre-synthesis nodes? See the Messages window for more information.
ID:268115 The netlist type of the partitions of the following nodes have been set to Source File.
ID:268116 Pre-synthesis node "<name>"
ID:268117 Could not set the netlist type of the corresponding partition to Source File. See the Messages window for more information.
ID:268118 Do you want to set the Netlist Type of the Top partition to Post-Fit since you are adding post-fitting nodes? See the Messages window for more information.
ID:268119 Do you want to set the Netlist Type of the corresponding partition to Post-Fit since you are adding post-fitting nodes? See the Messages window for more information.
ID:268120 The netlist type of the partitions of the following nodes have been set to Post-Fit or Post-Fit (Import-based).
ID:268121 Post-fitting node "<name>"
ID:268122 Could not set the Netlist Type of the corresponding partition to Post-Fit or Post-Fit (Import-based). See the Messages window for more information.
ID:268123 The state-based storage qualifier is only available when using the state-based trigger flow control.
ID:268124 Cannot choose a bus. Please select a single bit node instead.
ID:268125 Can't open Signal Tap Logic Analyzer. Verify that the license file exists and is stored in the correct location. If you are using the Quartus Prime Lite Edition software, you must turn on the TalkBack feature to use the Signal Tap Logic Analyzer.
ID:268126 Enter a value between <range> and <range>
ID:268127 Do you want to set the Netlist Type of all the other partitions to Post-Fit?
ID:269000 JTAG ready
ID:269001 Acquisition in progress
ID:269002 Programming device
ID:269003 No device is selected
ID:269004 No devices detected
ID:269005 Selected device not found
ID:269006 JTAG communication error
ID:271000 Can't process assignment. Attribute name "<name>" is illegal -- use a legal attribute for assignment in ALTERA_ATTRIBUTE assignment.
ID:271001 Ignored obsolete assignment "<name>" in altera_attribute
ID:271002 Can't process assignment. Attribute value "<name>" for attribute "<name>" is illegal -- use a legal attribute value for assignment in ALTERA_ATTRIBUTE assignment.
ID:271003 Can't process assignment. Attribute section "<name>" for attribute "<name>" is illegal -- use a legal attribute section for assignment in ALTERA_ATTRIBUTE assignment.
ID:271004 Can't process assignment. Attribute format is illegal -- parsing error <text> (line <number>). Use legal format for ALTERA_ATTRIBUTE assignment.
ID:271005 Can't create assignment -- source "<name>" and destination "<name>" already specified for point-to-point assignment
ID:271006 Can't create assignment -- point-to-point assignment does not contain both source and destination values
ID:271007 Can't process assignment. Attribute format is illegal -- multiple source values "<name>" specified for assignment using '-from' option. Use legal format for ALTERA_ATTRIBUTE assignment.
ID:271008 Can't process assignment. Attribute format is illegal -- multiple destination values "<name>" specified for the assignment using '-to' option. Use legal format for ALTERA_ATTRIBUTE assignment.
ID:271009 Can't process assignment. Attribute format is illegal -- multiple section identifier values "<name>" specified for the assignment using '-section_id' option. Use legal format for ALTERA_ATTRIBUTE assignment.
ID:271010 Unrecognizable value <name> -- put the value within quotation marks
ID:271011 Can't make global setting <name> using ALTERA_ATTRIBUTE
ID:271012 Can't process ALTERA_ATTRIBUTE "<name>" from design file
ID:271013 Can't process ALTERA_ATTRIBUTE "<name>" on <name> from design file
ID:272000 Can't open DLL "<name>"
ID:272001 Can't find function "<name>" in DLL "<name>"
ID:272002 Can't open file <name>
ID:272003 cbxi.lst file <name> contains one or more syntax errors
ID:272004 Ignoring archived or saved clear box file <clearbox_file_name> for hierarchy <hierarchy_name>, because it has different set of parameters than the current elaboration.
ID:272005 Ignoring archived or saved clear box file <clearbox_file_name> for hierarchy <hierarchy_name>, because it had errors during clear box generation.
ID:272006 Error message
ID:272007 Warning message
ID:272008 Info message
ID:275002 No superset bus at connection
ID:275003 Illegal expression
ID:275004 Undeclared parameter <name>
ID:275005 Result of expression <name> for parameter <value> is not an integer
ID:275006 Can't find a definition for parameter <name> -- assuming <value> was intended to be a quoted string
ID:275007 Function <name> of instance "<name>" not used
ID:275008 Primitive "<name>" of instance "<name>" not used
ID:275009 Pin "<name>" not connected
ID:275010 Buses connected to instance "<name>" are not named - if you want to create a primitive array, you must name all nodes and buses
ID:275011 Block or symbol "<name>" of instance "<name>" overlaps another block or symbol
ID:275012 Pin "<name>" overlaps another pin, block, or symbol
ID:275013 Port "<name>" of type <name> and instance "<name>" is missing source signal
ID:275014 INPUTC, OUTPUTC and BIDIRC pins not supported for pin "<name>"
ID:275015 Design name for "<name>" contains a number -- illegal for Verilog HDL and VHDL -- adding "\\" in front of name
ID:275016 Found Altera-specific megafunction, primitive or component "<name>"
ID:275017 Component "<name>" is not instantiated in the "<name>" design because none of its input ports or output ports are connected.
ID:275019 Can't open file <name>
ID:275020 Can't open file <name>. Files created in MAX+PLUS II (DOS version) and earlier are not supported.
ID:275021 Illegal wire or bus name "<name>" of type <type>
ID:275022 Illegal bus range or name for logic function for instance "<name>" of type <type>
ID:275023 Width mismatch in <name> -- source is "<name>"
ID:275024 Width mismatch in port "<name>" of instance "<name>" and type <name> -- source is "<name>"
ID:275025 Width mismatch in mapping block "<name>" of type <name> and instance "<name>" for signal "<name>"
ID:275026 Global signal "<name>" does not exist on conduit
ID:275027 Block I/O "<name>" does not exist on block "<name>" of instance "<name>"
ID:275028 Bus name allowed only on bus line -- pin "<name>"
ID:275029 Incorrect connector style at port "<name>" for symbol "<name>" of type <name>
ID:275030 Bus name allowed only on bus line -- signal "<name>"
ID:275031 Can't use conduits in network without blocks
ID:275032 Can't connect "<name>" to "<name>" directly -- both signals are output signals
ID:275033 Can't find name for bus
ID:275034 Can't find bus signal in conduit
ID:275036 Node line contains "<name>" and "<name>", but may be named only once
ID:275037 Bus contains incompatible signal names -- "<name>" and "<name>"
ID:275038 Bus signal "<name>" not in conduit, which contains only signal "<name>"
ID:275039 I/O types on I/O block and mapping conflict
ID:275040 Pin "<name>" cannot connect to more than one source signal
ID:275041 Signal "<name>" cannot connect to more than one source signal
ID:275042 Bidirectional pin "<name>" is missing source
ID:275043 Pin "<name>" is missing source
ID:275044 Port "<name>" of type <name> of instance "<name>" is missing source signal
ID:275045 Name missing for connector connecting to port "<name>" of type <name> of instance "<name>"
ID:275046 Illegal name "<name>" -- pin name already exists
ID:275047 Can't divide expression by zero
ID:275048 Illegal multidimensional bus "<name>"
ID:275049 Expressions do not support array notation
ID:275050 Bus range <value> is illegal in signal "<name>"
ID:275051 Bus range for signal "<name>" must be a number
ID:275052 Expression passed to LOG2 is negative or zero
ID:275053 No output or bidirectional pins in design
ID:275054 Illegal default value on pin "<name>"
ID:275055 Value of parameter "<name>" has multiple declarations
ID:275056 Can't map to alias "<name>"
ID:275057 Illegal character \'<text>\' in port inversion pattern -- character must be hexadecimal
ID:275058 Signal <signal name> drives an input pin
ID:275059 Block or symbol of type <name> and instance "<name>" overlaps another pin, block, or symbol
ID:275060 Pin "<name>" overlaps another pin, block, or symbol
ID:275061 Can't name logic function <name> of instance "<name>" -- function has same name as current design file
ID:275062 Logic function of type <name> and instance "<name>" is already defined as a signal name or another logic function
ID:275063 Can't find mapping for conduit in block of type <name> of instance "<name>"
ID:275064 Can't find mapping for bus in block of type <name> of instance "<name>"
ID:275065 Can't find mapping for node in block of type <name> of instance "<name>"
ID:275066 Can't find mapping for <name> "<name>"
ID:275067 Design name "<name>" is illegal for Verilog HDL
ID:275068 Design name "<type_name>" is illegal for VHDL
ID:275069 Design file contains illegal characters for Verilog HDL
ID:275070 Name "<name>" in design file <name> contains illegal character for VHDL
ID:275071 Name "<name>" contains VHDL keyword
ID:275072 Name "<name>" contains Verilog HDL keyword
ID:275073 Illegal pins in Verilog HDL
ID:275074 Width mismatch for port "<name>" with instance "<name>" of type <name> and signal "<name>". Design will not compile in VHDL.
ID:275075 Can't create HDL Design File because <name> primitive "<name>" is missing necessary signal(s)
ID:275076 Can't create HDL Design File because TRI primitive "<name>" missing signal(s)
ID:275077 Can't create HDL Design File because LATCH primitive "<name>" is missing signal(s)
ID:275078 Can't resolve the connectivity for signal "<name>"
ID:275079 The conduit width does not match the actual signal "<name>".
ID:275080 Converted elements in bus name "<name>" using legacy naming rules. Make any assignments on the new names, not on the original names.
ID:275081 Converted element name(s) from "<name>" to "<name>"
ID:275082 Illegal values "<parameter value>" for parameter "<parameter name>". The type is "<acf type UI name>".
ID:275083 Bus "<bus name>" found using same base name as "<bus base name>", which might lead to a name conflict.
ID:275084 Inconsistent dimensions for element "<name>"
ID:275085 Found inconsistent dimensions for element "<name>"
ID:275086 Found inconsistent I/O type for element "<name>"
ID:275087 Found inconsistent default value for element "<name>"
ID:275088 Inconsistent I/O type for element "<name>"
ID:275089 Not all bits in bus "<name>" are used
ID:275090 Conversion to VHDL format for the parameter(s) isn't supported
ID:275091 Can't convert Parameter "<name>", value "<value>" : <message>
ID:275092 Parameter "<parameter name>", value "<parameter value>", type "<parameter type>"
ID:275093 Port "<name>" is missing source signal
ID:276000 Cannot synthesize initialized RAM logic "<name>"
ID:276001 Cannot synthesize dual-port RAM logic "<name>"
ID:276002 Cannot convert all sets of registers into RAM megafunctions when creating nodes; therefore, the resulting number of registers remaining in design can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis
ID:276003 Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in the device or the number specified by the assignment max_number_of_registers_from_uninferred_rams. This can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis
ID:276004 RAM logic "<name>" is uninferred due to inappropriate RAM size
ID:276005 RAM logic "<name>" is uninferred due to device family not having RAM hardware
ID:276006 RAM logic "<name>" is uninferred due to "logic" being set as ramstyle synthesis attribute
ID:276007 RAM logic "<name>" is uninferred due to asynchronous read logic
ID:276008 RAM logic "<name>" is uninferred due to illegal secondary signals in read logic
ID:276009 RAM logic "<name>" is uninferred due to unsupported read-during-write behavior
ID:276010 RAM logic "<name>" is uninferred due to unsupported read-during-write behavior with byte-enable signals
ID:276011 RAM logic "<name>" is uninferred because of a feature that is not supported by MLAB inference
ID:276012 RAM logic "<name>" is uninferred due to too many ports
ID:276014 Found <number> instances of uninferred RAM logic
ID:276015 Auto RAM Replacement option turned off for RAM logic "<name>"
ID:276016 RAM logic "<name>" is uninferred due to asynchronous write logic
ID:276017 RAM logic "<name>" is uninferred due to illegal secondary signals in write logic
ID:276018 RAM logic "<name>" is uninferred due to inconsistent secondary signals in write logic
ID:276019 Created node "<name>" as a RAM by generating an altdpram megafunction to implement register logic with MLABs. Pass-through logic has been added.
ID:276020 Inferred RAM node "<name>" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
ID:276021 Created node "<name>" as a single-port RAM by generating altsyncram megafunction to implement register logic. Power-up values at the outputs of the RAM are different from the original design.
ID:276022 Created node "<name>" as a RAM by generating altdpram megafunction to implement register logic with MLABs. Functionality differs from the original design.
ID:276023 Created node "<name>" as a dual-clock RAM by generating altdpram megafunction to implement register logic with MLABs. However, functionality differs from the original design.
ID:276024 Pass-through logic not created for RAM node "<name>"
ID:276025 Inferred RAM node "<name>" from synchronous design logic, but the read-during-write behavior of RAM does not match the read-during-write behavior of the original design
ID:276026 Inferred RAM node "<name>" from synchronous design logic. The RAM node maps into an M-RAM that powers up into an unknown state
ID:276027 Inferred dual-clock RAM node "<name>" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.
ID:276028 Inferred ROM node "<name>" from synchronous logic. The ROM output initializes to GND and may not match the power-up state of your original design.
ID:276029 Inferred altsyncram megafunction from the following design logic: "<text>"
ID:276030 ROM inference for design logic <text> using the altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=<number>, WIDTH_A=<number>) is disabled in formal verification mode
ID:276031 Inferred altsyncram megafunction from the following design logic: "<text>"
ID:276032 Inferred lpm_rom megafunction from the following design logic: "<text>"
ID:276033 Shift register inference for design logic: <text> using the altshift_taps megafunction (NUMBER_OF_TAPS=<number>, TAP_DISTANCE=<number>, WIDTH=<number>) is disabled in formal verification mode
ID:276034 Inferred altshift_taps megafunction from the following design logic: "<text>"
ID:276035 Created node "<name>" as a RAM by generating altdpram megafunction to implement register logic with MLABs. Expect to get an error or a mismatch for this block in the formal verification tool.
ID:276036 Top level entity of a design cannot be treated as a black-box for formal verification
ID:276037 Created node "<name>" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Expect to get an error or a mismatch for this block in the formal verification tool.
ID:276038 Inferred altdpram megafunction from the following logic: "<text>"
ID:278000 Shift operator shift amount is too wide: shift distance is <number> bits wide, data width is <number> bits
ID:278001 Inferred <number> megafunctions from design logic
ID:278002 Inferred adder/subtractor megafunction ("<text>") from the following logic: "<text>"
ID:278003 Inferred multiplier megafunction ("<text>") from the following logic: "<text>"
ID:278004 Inferred divider/modulo megafunction ("<text>") from the following logic: "<text>"
ID:278005 Inferred shifter megafunction ("<text>") from the following logic: "<text>"
ID:278006 Inferred comparator megafunction ("<text>") from the following logic: "<text>"
ID:278007 Inferred mux megafunction ("<text>") from the following logic: "<text>"
ID:278008 Inferred decoder megafunction ("<text>") from the following logic: "<text>"
ID:278009 Parameter <text> set to <text>
ID:283000 Encountered unknown disk error while writing to file <name>
ID:283001 Can't create Component Declaration or Verilog Instantiation File for entity "<name>" which has two or more dimensional ports
ID:284000 Cannot use minimal number of bits to encode state machine "<name>"
ID:284001 Cannot choose best encoding method for state machine "<name>"
ID:284002 Cannot process state machine "<name>" using user-encoded method
ID:284003 State machine "<name>" must be reset to ensure proper operation
ID:284004 State bit assignments are not unique for state "<name>" and state "<name>"
ID:284005 Ignored Power-Up Level logic option setting for state bit "<name>" -- using reset state's zero value instead
ID:284006 Flipped <number> bits in user-encoded state machine <name>
ID:284007 State machine "<name>" will be implemented as a safe state machine.
ID:286001 WYSIWYG primitive <name> has missing connection on input port <name>
ID:286002 Ignored following assignments for SYNTH_CRITICAL_CLOCK
ID:286003 Ignored following assignments for SYNTH_CRITICAL_CLOCK for hierarchy "<name>"
ID:286004 Ignored following assignments for SYNTH_CRITICAL_CLOCK for partition "<name>"
ID:286005 Ignored assignment for SYNTH_CRITICAL_CLOCK from clock "<name>" to clock "<name>" -- no registers were found for clock "<name>"
ID:286006 Ignored assignment for SYNTH_CRITICAL_CLOCK for clock "<name>" -- no registers were found for this clock
ID:286007 Ignored following assignments for SYNTH_CRITICAL_INPUT_TO_CLOCK
ID:286008 Ignored following assignments for SYNTH_CRITICAL_INPUT_TO_CLOCK for hierarchy "<name>"
ID:286009 Ignored following assignments for SYNTH_CRITICAL_INPUT_TO_CLOCK for partition "<name>"
ID:286010 Ignored assignment for SYNTH_CRITICAL_INPUT_TO_CLOCK for clock "<name>" -- no registers were found
ID:286011 Ignored following assignments for SYNTH_CRITICAL_CLOCK_TO_OUTPUT
ID:286012 Ignored following assignments for SYNTH_CRITICAL_CLOCK_TO_OUTPUT for hierarchy "<name>"
ID:286013 Ignored following assignments for SYNTH_CRITICAL_CLOCK_TO_OUTPUT for partition "<name>"
ID:286014 Ignored assignment for SYNTH_CRITICAL_CLOCK_TO_OUTPUT for clock "<name>" -- no registers were found
ID:286015 Ignored following assignments for SYNTH_CRITICAL_ENABLE
ID:286016 Ignored assignment for SYNTH_CRITICAL_ENABLE for register "<name>" -- register not found
ID:286017 Ignored following assignments for SYNTH_CRITICAL_PIN
ID:286018 Ignored assignment for SYNTH_CRITICAL_PIN for pin "<name>" -- pin not found
ID:286019 Cannot translate WYSIWYG DLL "<name>" in <name> mode to family <name> because it is not in normal mode
ID:286020 Cannot translate WYSIWYG DQS I/O "<name>" to family <name> because it is not in BYPASS mode nor is all of its delayctrlin inputs directly fed by a WYSIWYG DLL
ID:286021 WYSIWYG DLL "<name>" has delay chain length of <number>, but the recommended delay chain length in <name> with a <number> MHz clock is <number>. The compiler will use the recommended delay chain length.
ID:286022 DQS WYSIWYG "<name>" has delay chain length of <number>, but the recommended delay chain length in <name> is <number>. The compiler will use the recommended delay chain length to achieve a phase shift of <number> degrees.
ID:286023 Cannot translate WYSIWYG Clock Delay Control "<name>" to family <name> because it is not in static or none mode
ID:286024 Cannot translate the phase shift of DQS I/O WYSIWYG "<name>" to family <name> because it's using the custom phase shift value of <number> (expected phase shift setting of <number>)
ID:286025 WYSIWYG I/O Input Buffer primitive "<name>" uses bus hold function and is not connected properly. The Quartus Prime software will unmap the illegal buffer and ignore the bus hold property.
ID:286026 WYSIWYG I/O Output Buffer primitive "<name>" uses bus hold function and is not connected properly. The Quartus Prime software will unmap the illegal buffer and ignore the bus hold property.
ID:286027 I/O WYSIWYG "<name>" will have different synchronous clear/preset behavior after translated to family <name>.
ID:286029 Timing-Driven Synthesis is skipped because the Synthesis Effort is set to Fast
ID:286030 Timing-Driven Synthesis is running
ID:286031 Timing-Driven Synthesis is running on partition "<name>"
ID:286033 Parameter <text> set to <text>
ID:286034 Cannot find Memory Initialization File or Hexadecimal (Intel-Format) File <name> for ROM instance <name>
ID:287000 Assertion information: <text>
ID:287001 Assertion warning: <text>
ID:287002 Group MSB <name> <number> overrides BIT0 = LSB in actual or default Options Statement
ID:287003 Group LSB <name> <number> overrides BIT0 = MSB in Options Statement
ID:287004 Group name "<name>" is missing brackets ([ ])
ID:287005 Group name "<name>" is missing two sets of brackets ([ ][ ])
ID:287006 Constant or parameter "<text>" is used but not defined -- interpreted constant or parameter as quoted string
ID:287007 Options Statement contains more than one BIT0 option -- using only first BIT0 option
ID:287008 Options Statement contains more than one <name> option -- used only first instance of option
ID:287009 Result of LOG2 is not an integer -- rounded result to next whole number
ID:287010 Result of division operation "<number>/<number>" contains a remainder -- truncated result
ID:287011 Replaced illegal text "<text>" with replacement text "<text>"
ID:287012 Numerical value "<text>" that is assigned to state has more bits than the state -- attempted to fit value into state
ID:287013 Variable or input pin "<name>" is defined but never used.
ID:287014 Ignored named operator "<name>" -- operator is named in arithmetic expression and not in Boolean expression that generates logic
ID:287015 Name "<name>" used for more than one Boolean expression operator or comparator in Text Design File -- ignored all but first use of name
ID:287016 Memory declaration warning: ignored duplicates of attribute "<name>" -- recognized only last use of attribute
ID:287017 Group is used as "<name>[<number>..<number>]" and defined using a different range order ("<name>[<number>..<number>]")
ID:287018 Ignored Design Section -- it is not supported
ID:287019 Symbolic name "<name>" is used but not defined as a group -- attempted to use existing nodes
ID:287020 Symbolic name "<name>" is used but not defined as a single-range group -- attempted to use existing nodes
ID:287021 Symbolic name "<name>" is used but not defined as a dual-range group -- attempted to use existing nodes
ID:287022 Argument "<name>" for USED function is not a pin or a parameter
ID:287023 Ignored all options except BIT0 in Options Statement -- only BIT0 option is supported
ID:287024 State machine name "<name>" must be assigned or compared to state value
ID:287025 Text Design File contains constant, but must contain state name
ID:287027 State must be used in expression that describes state machine
ID:287028 List of states in WHEN clause of state machine Case Statement cannot be enclosed in parentheses
ID:287029 Format of base number "<number>" is illegal
ID:287030 Base number "<number>" cannot contain digit <character>
ID:287031 State machine name "<name>" must be assigned or compared to state value
ID:287032 Constant cannot be defined with quoted number or arithmetic expression "<text>"
ID:287033 Output pin "<name>" defined with group range in Subdesign Section cannot be defined with different group range in Variable Section
ID:287034 Pin "<name>" defined in Subdesign Section as input, machine input, or machine output pin cannot be defined in Register Declaration
ID:287035 Text Design File must contain a Subdesign and Logic Section
ID:287036 Can't resolve arithmetic expression because nesting is too deep
ID:287037 Argument for LOG2 cannot be negative number or zero
ID:287038 Text Design File cannot contain more than one Title Statement
ID:287039 Parameters cannot be specified for primitives
ID:287040 Arithmetic expression cannot contain divisor of zero
ID:287041 Arithmetic expression cannot compare a number to a quoted string
ID:287042 Arithmetic expression contains node or group name(s) "<name(s)>", but only Boolean expressions can contain nodes and groups
ID:287043 Name "<name>" used in arithmetic expression must be evaluated function or constant
ID:287044 Evaluated function "<name>" cannot be defined more than once
ID:287045 Evaluated function "<name>" contains <number> arguments, but must contain <number> arguments
ID:287046 Boolean expression contains evaluated function "<name>", but only arithmetic expressions can contain evaluated functions
ID:287047 Result of arithmetic expression ("<text>") cannot be negative
ID:287048 Iterator variable has name "<name>", but name is already used as a constant, parameter, or node name
ID:287049 Truncated number -- number cannot be assigned to group of lesser width
ID:287050 Group or node "<name>" in arithmetic or logical operation cannot contain don't care value
ID:287051 One group in operation has <number> bits and a second group has <number> bits, but the groups must be the same size
ID:287052 Node cannot be used as operand for arithmetic operator in Boolean expression
ID:287053 Node cannot be used as operand for arithmetic comparison in Boolean expression
ID:287054 Right of Boolean equation cannot contain text "<text>"
ID:287055 Ignored don't care value "<text>" -- value is in Boolean expression that contains comparator
ID:287056 Text Design File syntax error: <text>
ID:287057 Can't open file <name>
ID:287058 Can't compile design containing encrypted file <name> -- current license does not allow this file to be opened
ID:287059 Text Design File syntax error: Text Design File contains <text> where <text> was expected
ID:287060 INCLUDE keyword in Include Statement must be followed by a file name enclosed in quotation marks ("")
ID:287061 Text Design File syntax error: Text Design File is missing semicolon (;)
ID:287062 Can't open AHDL Include File <name>
ID:287063 Include Statements in Text Design File cannot include file <name> more than once
ID:287064 Defaults Statement must be first item in Logic Section
ID:287065 Output port(s) cannot have default value of GND or VCC
ID:287066 Symbolic name "<name>" cannot be defined more than once, and cannot be a reserved keyword
ID:287067 Symbolic name "<name>" is used but not defined
ID:287068 Symbolic name "<name>" cannot be used for more than one port in Function Prototype "<name>"
ID:287069 Symbolic name "<name>" must be input port of megafunction, macrofunction, primitive, or state machine "<name>"
ID:287070 Symbolic name "<name>" must be output port of megafunction, macrofunction, primitive, or state machine "<name>"
ID:287071 Symbolic name "<name>" must be port of megafunction, macrofunction, primitive, or state machine "<name>"
ID:287072 Symbolic name "<name>" is used but not defined
ID:287073 Text Design File contains "<text>" item, but must contain state name, node, constant, or parameter
ID:287074 Text Design File contains group, but must contain node
ID:287075 Arithmetic expression cannot contain quoted string "<text>"
ID:287076 Can't find an inherited or default value for parameter "<name>" -- specify a parameter value
ID:287077 Parameter "<name>" cannot be assigned more than one value
ID:287078 Assertion error: <text>
ID:287079 Assert Statement message string uses <number> message variables, but uses only <number> variables
ID:287080 Message variable in Assert Statement must be constant, parameter, or arithmetic expression
ID:287081 Severity level keyword in Assert Statement is <text>, but must be INFO, ERROR, or WARNING
ID:287082 Setting for BIT0 option in Options Statement must be LSB, MSB, or ANY
ID:287083 Setting for "<name>" option in Options Statement must be "<text>"
ID:287084 Symbolic name "<name>" is used but not defined as a group
ID:287085 Symbolic name "<name>" is used but not defined as a single-range group
ID:287086 Symbolic name "<name>" is used but not defined as a dual-range group
ID:287087 Group range of arithmetic expression contains negative number <number>, but numbers in group ranges cannot be negative
ID:287088 Expression to the left of period (.) must be symbolic name for megafunction, macrofunction, primitive, or state machine
ID:287089 Group "<name>" cannot be redefined with a different range
ID:287090 Result of arithmetic expression (<text>) cannot be negative
ID:287091 Symbolic name "<name>" is used but not defined as a megafunction or macrofunction
ID:287092 Symbolic name "<name>" cannot have port
ID:287093 Symbolic name "<name>" must be port of megafunction, macrofunction, primitive, or state machine "<name>"
ID:287094 Symbolic name "<name>" is used as megafunction or macrofunction, but is defined as something other than a megafunction or macrofunction
ID:287095 Port count (<number>) for instance of logic function "<name>" must agree with Function Prototype port count (<number>)
ID:287096 Right of Boolean equation cannot contain text "<text>"
ID:287097 Left of Boolean equation cannot contain text "<text>"
ID:287098 Size of WHEN group differs from size of CASE group, but the two groups must be the same size
ID:287099 One group in operation has <number> bits and a second group has <number> bits, but the groups must be the same size
ID:287100 AHDL feature ("<text>") not currently supported
ID:287101 Value cannot be specified for constant or parameter "<name>" in Logic Section
ID:287102 Input pin "<name>" cannot be assigned a value
ID:287103 Input port "<name>.<name>" cannot be used as a value
ID:287104 Output port "<name>.<name>" cannot be assigned a value
ID:287105 State bit "<name>" of state machine "<name>" cannot be assigned a value
ID:287106 Megafunction or macrofunction name "<name>" cannot be used as an instance name for the logic function
ID:287107 BIDIR pin "<name>" cannot be assigned more than one value. Created single value from multiple values, but single value cannot be used.
ID:287108 Unsupported feature error: imported state machine or machine alias "<name>" is unsupported
ID:287109 Expression to the left of period (.) must be symbolic name for megafunction, macrofunction, primitive, or state machine
ID:287110 Symbolic name "<name>" is used but not defined as a state of state machine "<name>"
ID:287111 State machine name "<name>" must be assigned or compared to state value
ID:287112 Unsupported feature error: state machine input port or machine alias "<name>" is unsupported
ID:287113 Numbers cannot be assigned to nodes
ID:287114 Groups cannot be assigned to nodes
ID:287115 Number of group bits (<number>) on left of Boolean equation must be evenly divisible by number of group bits (<number>) on right
ID:287116 Row(s) and heading in table of Truth Table Statement must have equal number of items
ID:287117 Memory declaration error: group declarations are not supported
ID:287118 Memory declaration error: function must have attribute "<name>"
ID:287119 Memory declaration error: attribute "<name>" is illegal
ID:287120 Memory declaration error: attribute "<name>" has illegal value "<text>"
ID:287121 Memory declaration error: SEGMENTSIZE <number> must be a power of 2
ID:287122 Memory declaration error: SEGMENTSIZE <number> is too large (maximum size is <number>)
ID:287123 Memory declaration error: number of segments declared (<number>) must equal number of segments expected (<number>)
ID:287124 Group name in Text Design File must use legal single-range, dual-range, or sequential group name notation
ID:287125 Dual-range group name in Text Design File contains an illegal character
ID:287126 Text Design File cannot contain more than one Subdesign Section and Logic Section
ID:287127 Text Design File syntax error: Text Design File contains <text> where <text> was expected
ID:287128 Text Design File syntax error: Text Design File contains <text> with name "<name>" where <text> was expected
ID:287129 Text Design File syntax error: expected letter, digit, slash (/), dash (-), or underscore (_) in quoted symbolic name
ID:287130 Canceled analysis of design entity "<name>" -- number of errors in Text Design File for entity cannot exceed maximum of <number>
ID:287131 For Generate Statement generates <number> instances of megafunction, macrofunction, or primitive, but Instance Declaration contains only <number> instance names
ID:287132 Name substitution feature used in Function Prototype Statement, Variable Section, or in-line logic function reference, but not enabled in Options Statement
ID:287133 Can't create path "<name>"
ID:287134 Parameter string format error.
ID:287135 Bidirectional port types not supported.
ID:289000 Can't find project <name>
ID:289001 Specify a project name, working directory, and top-level design entity
ID:289002 Length of the directory plus project setting and/or database files exceed the operating system limit of <number>. Try specifying a shorter directory path or project name.
ID:289003 Are you sure that you want to remove the settings for project <name>?
ID:289004 Project directory "<name>" already contains a project. If the projects share the same files, edits made while working on one project could affect the other project. Do you want to select a different project directory?
ID:289005 Directory "<name>" does not exist. Do you want to create it?
ID:289006 Can't create working directory "<name>"
ID:290000 Processing of the Quartus Prime software <number> started at time <number>
ID:291000 TalkBack feature must be enabled to run this version of the Quartus Prime software
ID:291001 Opening Licensing section of the Intel FPGA website at <text>
ID:291002 Can't connect to the Intel FPGA website to check for license file updates. Verify that you have an active internet connection. To prevent the Quartus Prime software from connecting to the internet to check for updates, in the Options dialog box, on the Internet Connectivity page, turn off the options under Startup.
ID:291003 Can't connect to the Intel FPGA website to check for license file updates. Verify that you have an active internet connection. To prevent the Quartus Prime software from connecting to the internet to check for updates, in the Options dialog box, on the Internet Connectivity page, turn off the options under Startup.
ID:291004 Found multiple license files for this system at the Intel FPGA website. Do you want to connect to the Intel FPGA Licensing Center to download one of the license files?
ID:291005 Can't find a newer license file for this system at the Intel FPGA website. Do you want to connect to the Intel FPGA Licensing Center?
ID:291006 Downloaded a new license file from the Intel FPGA website -- do you want to use the new license file?
ID:291007 New feature lines merged with the current license file successfully. The Quartus Prime software is now enabled. If you have not already requested for your ModelSim - Intel FPGA license, you can visit the Intel FPGA License Center to do so and have your complete license emailed to you. Do you want to visit the Intel FPGA License Center now to request for your ModelSim - Intel FPGA license?
ID:291009 Saved the new license file to "<name>" -- the license file is added to the Quartus Prime software license file specification. The Quartus Prime software is now enabled. If you have not already requested for your ModelSim - Intel FPGA license, you can visit the Intel FPGA License Center to do so and have your complete license emailed to you. Do you want to visit the Intel FPGA License Center now to request for your ModelSim - Intel FPGA license?
ID:291011 Quartus Prime software cannot determine the current license file and therefore cannot merge the new feature lines to it. Specify a location to save new feature lines (for example, c:\\licenses\\license.dat).
ID:291012 Can't save new license file to "<name>"
ID:291013 <text>
ID:291014 Quartus Prime software is unable to activate your license
ID:292000 FLEXlm software error: <text>.
ID:292001 Lost license server connection for feature <text>, reconnection attempt <number>.
ID:292002 Connection to license server reestablished for feature <text>.
ID:292003 Quartus Prime Software does not support platform <name>.
ID:292004 Beta version of the Quartus Prime software expired on <date>. Upgrade to a newer version of the Quartus Prime software.
ID:292005 TalkBack feature must be enabled to run this version of the Quartus Prime software. Run tb2_install to enable the TalkBack feature.
ID:292006 Can't contact license server "<name>" -- this server will be ignored.
ID:292007 Additional floating licenses for feature <name> not available -- all available floating licenses are in use.
ID:292008 All instances of floating feature <name> are currently in use, waiting for one to become available...
ID:292009 License checkout failed for feature <name> -- your node-locked license is not enabled for use under Windows Remote Desktop.
ID:292010 You have both a USB and parallel port software guard connected to your computer. Quartus Prime is ignoring the parallel port software guard.
ID:292011 Can't generate programming files because you are currently using the Quartus Prime software in Evaluation Mode.
ID:292012 Feature <name> is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
ID:292013 Feature <name> is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
ID:292014 Can't find valid feature line for core <name> (Vendor: <vendor>) in current license.
ID:292015 License for core <name>, version <version> is expired.
ID:292016 All floating licenses for core <name> are currently in use.
ID:292017 License for core <name> is not enabled for use under Windows Remote Desktop.
ID:292018 Defaulting to OpenCore or OpenCore Plus compilation for core <name>.
ID:292019 IP core <name> not supported in device family <family>. Choose a new device family or upgrade your IP core to a newer version. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/kdb-filter.html and search for this specific error message number.
ID:292020 Support for IP core <name> in device family <family> is preliminary and core functionality has not been fully verified.
ID:292021 Support for IP core <name> in device family <family> is preliminary and specifications are subject to change.
ID:292022 OpenCore Plus time-limited core <name> may be used for hardware evaluation only.
ID:292023 Encrypted file <name> is corrupt and cannot be read.
ID:292024 Can't open file <name> for output.
ID:292025 License file is not specified.
ID:292026 Specified license file does not exist.
ID:292027 Specified license does not contain information required to run the Quartus Prime software.
ID:292028 Specified license is not valid for this machine.
ID:292029 Specified license has expired. To use the License Setup Manager to specify a valid license, click License Setup on the Tools menu. If you do not have a valid license, try re-downloading your license from https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/licensing.html or contact your local Intel sales representative or Intel Customer Services (https://www.intel.com/content/www/us/en/programmable/support/support-resources.html).
ID:292030 License is not valid for this version of the Quartus Prime software. However, the specified license will continue to work for versions of the Quartus Prime software that were released before the specified license expired.
ID:292031 Specified license does not have a SIGN= field -or- the specified license server is not FLEXlm 8.x or later.
ID:292032 You cannot use the specified license with Remote Desktop.
ID:292033 No more license seats available from specified license server.
ID:292034 Thank you for installing the Quartus Prime software - the #1 in performance and productivity. To upgrade to a full featured edition, please https://www.intel.com/content/www/us/en/products/programmable.html.
ID:292035 Quartus Prime software is currently being used under the "Subscription Expiration" grace period. You must obtain an updated license file to permanently enable this version of the Quartus Prime software. You have <number> days left (until <date>) before the programming file support is disabled.
ID:292036 Thank you for using the Quartus Prime software 30-day evaluation. You have <number> days remaining (until <date>) to use the Quartus Prime software with compilation and simulation support.
ID:292037 Thank you for using the Quartus Prime software. Your 30-day evaluation period has expired.
ID:292038 Your subscription has expired. However, the specified license will continue to work for versions of the Quartus Prime software that were released before the specified license expired. To obtain a license that supports newer versions of the Quartus Prime software, contact your local Intel sales representative or Intel Customer Services (https://www.intel.com/content/www/us/en/programmable/support/support-resources.html).
ID:292039 You have a valid up-to-date license.
ID:293000 Quartus Prime <name> was successful. <number> error<name>, <number> warning<name>
ID:293001 Quartus Prime <name> was unsuccessful. <number> error<name>, <number> warning<name>
ID:293002 Can't find design file <name>
ID:293003 Smart recompilation skipped module <name> because it is not required
ID:293006 Flow or module <name> does not exist
ID:293007 Current module <name> terminated with unexpected exit code <exit_code>. This may be because some system resource has been exhausted. You can view system resource requirements on the System and Software Requirements page of the Intel FPGA website (https://fpgasoftware.intel.com/requirements/).
ID:293008 Can't perform Signal Probe compilation because design requires a full compilation. To perform a Signal Probe compilation, recompile the design.
ID:293009 Can't perform Signal Tap Logic Analyzer compilation because design requires a full compilation. To perform a Signal Tap Logic Analyzer compilation, recompile the design.
ID:293017 Post-flow processing script assignment value <name> is illegal
ID:293018 Pre-flow processing script assignment value <name> is illegal
ID:293019 Post-module processing script assignment value <name> is illegal
ID:293020 Error(s) found while running <module>
ID:293021 No companion revision found while running <name>
ID:293022 Illegal companion revision <name1> found while running <name2> -- make sure the revision exists for the current project
ID:293024 Incremental compilation is not supported for the current target device family
ID:293025 Running full compilation because the target device has changed
ID:293026 Skipped module <name> due to the assignment <name>
ID:293027 Source file: <name> has changed.
ID:293028 Assignment <name> changed value from <value> to <value>.
ID:293029 New assignment <name> with value <value> has been added.
ID:293030 Assignment <name> with value <value> has been deleted.
ID:293031 Detected changes in Quartus Prime Settings File (.qsf).
ID:293032 Detected changes in source files.
ID:293033 A new file was added to the project: <name>.
ID:293034 Current flow <name> ended unexpectedly
ID:293035 Can't perform <name> because you are currently running <name>. To perform <name>, stop the current flow or wait for the current flow to finish.
ID:295001 Do you want to check the Intel FPGA website for updates? Allocate some time for the Intel Quartus Prime software to make the connection.
ID:295002 No web browser has been set up for use with the Intel Quartus Prime software -- specify a web browser in the Internet Connectivity page of the Options dialog box on the Tools menu.
ID:295003 Can't locate the web browser. Specify a web browser in the Internet Connectivity page of the Options dialog box on the Tools menu.
ID:296000 Current project is not elaborated. Running Analysis & Elaboration provides an accurate file set for the archiving process. Do you want to run Analysis & Elaboration as part of the archiving process?
ID:296001 Version-compatible database files do not exist. Do you want to run Export Database as part of the archiving process before archiving version compatible-database files?
ID:296002 <text>
ID:296003 Cannot find the file <name>
ID:296004 Quartus Prime Archive File <name> already exists. Do you want to replace it?
ID:296005 The device family <family name> is no longer supported by the Quartus Prime software. The current revision will not be opened.
ID:296006 A license file is required to enable compilation of your design for this family of devices. Visit the <licensing center url> section of the Intel FPGA website to request a license.
ID:296007 Device <name> does not belong to device family <name> -- Choose an appropriate device from the available devices. Intel recommends removing all family-specific assignments when changing the device. Do you want to remove all family-specific assignments?
ID:296008 Support for device <name> not installed -- switching to an appropriate device from the available devices. Intel recommends removing all family-specific assignments when changing the device. Do you want to remove all family-specific assignments?
ID:296009 You must have device support installed before you can open a project. To download device support, go to the <download center url> section of the Intel FPGA website.
ID:296010 Support for device family <name> not installed -- switching to device family <name> and choosing an appropriate device from the available devices. Intel recommends removing all family-specific assignments when changing the device. Do you want to remove all family-specific assignments?
ID:296011 Can't find SOPC Builder
ID:296012 This command will reformat your Quartus Prime Settings File to organize assignments based on categories. This command will reorder lines in the file and will remove any comments beginning with # that you have directly added to the file. Do you want to proceed?
ID:296013 Quartus Prime software cannot organize the Quartus Prime Settings File
ID:296014 Can't generate Early Power Estimation file. The target device does not support exporting Early Power Estimation files.
ID:296015 This command is not available while auto-device selection is enabled.
ID:296017 Stratix III companion device is not selected -- a companion revision cannot be created until a Stratix III companion device is selected
ID:296018 Stratix IV companion device is not selected -- a companion revision cannot be created until a Stratix IV companion device is selected
ID:296024 <text>
ID:296025 <text>
ID:296026 Assignment file <name> does not exist
ID:296027 Can't import assignments from Quartus Prime Setting File <name> because file is current QSF
ID:296028 Can't find input project file or design file <name>
ID:296029 Successfully imported assignments from Synplify SDC File <name>
ID:296030 Selected SDC file <name> is not in Synplify SDC File format. No assignment is imported.
ID:296031 Can't import assignments from Synplify SDC File <name>
ID:296032 Successfully imported assignments from FPGA Xchange File <name>
ID:296033 Can't import assignments from FPGA Xchange File <name>
ID:296034 Successfully imported assignments from ORCAD EXP File <name>
ID:296035 Can't import assignments from ORCAD EXP File <name>
ID:296036 Successfully imported assignments from MAX+PLUS II Assignment and Configuration File <name>
ID:296037 Can't import assignments from MAX+PLUS II Assignment and Configuration File <name>
ID:296038 Specify at least one MAX+PLUS II assignment type to import
ID:296039 Specify a MAX+PLUS II Assignment and Configuration File
ID:296045 Removing device assignments without removing all assignments from design may cause problems in future design compilation. Do you want to remove only the device assignments and the other assignments you turned on?
ID:296046 Destination directory "<name>" does not exist. Do you want to create it?
ID:296047 Directory "<name>" already contains a project. Project files in this directory may be overwritten during copying of a project. Do you want to continue?
ID:296048 Can't copy current project to current project directory
ID:296049 Type a Tcl Script File name
ID:296050 File <name> already exists. Do you want to overwrite it?
ID:296051 Can't access project assignment
ID:296052 Can't create or overwrite file <name>
ID:296053 Not all selected revisions have compilation information for comparison.
ID:296054 Assignment group named <name> already exists.
ID:296055 The compare revisions file has been successfully exported to: <name>.
ID:296056 Can't find the <toolkit name>
ID:296057 Revision name contains illegal character <name>
ID:296058 Revision name cannot contain white space or illegal character
ID:296059 Cannot find Platform Designer.
ID:296060 Can't overwrite directory <name> because you do not have the permission to overwrite it. Do you want to change the properties of the directory so that it is writable?
ID:296061 Are you sure you want to delete the revision <name>?
ID:296062 Cannot start Check and Save All Netlist Changes. No changes have been made.
ID:296063 Toolbar name field cannot be blank. Type a name in the Toolbar field.
ID:296064 Toolbar name '<name>' already exists. Type another name in the Toolbar name field.
ID:297000 Can't close project while a process is in progress
ID:297006 Project "<name>" does not exist
ID:297007 Project "<name>" already exists
ID:297009 Can't open project -- you do not have permission to write to all the files or create new files in the project's database directory
ID:297010 Can't remove incompatible database files from project
ID:297011 Can't open project "<name>" -- no Quartus Prime Settings Files exist for any revision listed in the Quartus Prime Project File
ID:297012 Deleted original project file <name> and saved copy of original project file and settings files in backup directory "<name>"
ID:297014 The current revision does not have a companion revision associated with it
ID:297019 This feature is only available when the family of the current revision is either Stratix III or Stratix IV
ID:297020 This feature is only available when the family of the current revision is either Stratix III or Stratix IV
ID:297022 This feature is only available when the family of the current revision is HardCopy II
ID:297023 This feature is only available when the family of the current revision is HardCopy II, HardCopy III or HardCopy IV
ID:297024 This feature is only available when the family of the current revision is HardCopy II, HardCopy III or HardCopy IV
ID:297027 This feature is only available when the family of the current revision is Stratix II, Stratix III or Stratix IV
ID:297028 This feature is only available when the family of the current revision is Stratix II, Stratix III or Stratix IV
ID:297030 Companion revision for the current revision does not recognize the current revision as its companion. Use the Set Current HardCopy Companion Revision dialog box to re-associate the two revisions
ID:297031 Unable to open the revision settings file for writing
ID:297032 Unable to open the revision settings file for writing
ID:297033 Selected feature is not available with your current license, or license does not exist
ID:297034 Selected feature is not available with your current license
ID:297035 No web browser has been set up for use with the Quartus Prime software -- specify a web browser in the Internet Connectivity page of the Options dialog box on the Tools menu
ID:297036 Can't locate the web browser. Specify a web browser in the Internet Connectivity page of the Options dialog box on the Tools menu.
ID:298000 <text>
ID:298001 <text>
ID:298002 <text>
ID:299000 Unable to open the revision settings file for writing
ID:299001 Unable to open the revision settings file for writing
ID:299002 Selected feature is not available with your current license, or license does not exist
ID:299003 Selected feature is not available with your current license
ID:299005 Companion revision for the current revision does not recognize the current revision as its companion. Use the Set Current HardCopy Companion Revision dialog box to reassociate the two revisions
ID:299016 This feature is only available when the family of the current revision is Stratix III
ID:299017 This feature is only available when the family of the current revision is Stratix III
ID:299018 This feature is only available when the family of the current revision is Stratix III
ID:299019 This feature is only available when the family of the current revision is Stratix III
ID:299022 Project "<name>" already exists
ID:300000 Signal Tap File creation was <successful, NOT successful>
ID:302000 Syntax error "<Syntax error text from XML parser>" at line <Line number at which syntax error occurred>, column <Column number at which syntax error occurred> while reading the XML file <XML file name>
ID:302001 Can't find top-level EDA_tool_info tag in the XML file "<XML file name>"
ID:302002 Found more than one top-level EDA_tool_info tag in the XML file "<XML file name>". The first one will be used.
ID:302003 Can't find tool category section in the XML file "<XML file name>"
ID:302004 Can't find tools section in the tool category <Tool category name> of the XML file "<XML file name>"
ID:302005 Found more than one tools section in the category tool <Tool category name> of the XML file "<XML file name>". The first one will be used.
ID:302006 Can't find tools section in the tool category <Tool category name> of the XML file "<XML file name>"
ID:302007 Can't find tool category name in the XML file "<XML file name>"
ID:302008 Found an invalid tool category name <Tool category name> in the XML file "<XML file name>"
ID:302009 Found a duplicate tool category name <Tool category name> in the XML file "<XML file name>"
ID:302010 Tool-specific user defaults section is missing for the tool name "<Tool name>" in the category <Tool category name> of the XML file "<XML file name>"
ID:302011 Found more than one user defaults section in the tool category <Tool category name> of the XML file "<XML file name>"
ID:302012 Found missing tool-specific control setting defaults section for tool name "<Tool name>" in the category <Tool category name> of the XML file "<XML file name>"
ID:302013 Found more than one control defaults section in tool the category name <Tool category name> of the XML file "<XML file name>"
ID:302014 Attribute <Attribute name> is missing from the setting line in the tool category name <Tool category name> of the XML file "<XML file name>"
ID:302015 Attribute <Attribute name> is missing from the setting line in the tool category name <Tool category name> of the XML file "<XML file name>". Therefore the setting is ignored.
ID:302016 Found an invalid or missing setting name <Setting name> specified in the tool category name <Tool category name> of the XML file "<XML file name>"
ID:302017 Found an invalid setting name <Setting name> specified in the tool category name <Tool category name> of the XML file "<XML file name>". The invalid setting name is ignored.
ID:302018 Found a duplicate setting name <Setting name> in the tool category name <Tool category name> of the XML file "<XML file name>"
ID:302019 Setting name <Setting name> in the tool category name <Tool category name> of the XML file "<XML file name>" is not valid for that category
ID:302020 Found an illegal setting type name <Setting type name> in the tool category name <Tool category name> of the XML file "<XML file name>"
ID:302021 Found a missing tool name attribute in the tool category name <Tool category name> of the XML file "<XML file name>"
ID:302022 Found a missing tool format attribute for tool name <Tool name> in the tool category name <Tool category name> of the XML file "<XML file name>"
ID:302023 Found a missing tool name with format line for tool name <Tool name> in the tool category name <Tool category name> of the XML file "<XML file name>"
ID:302024 Found an illegal tool name with format line for tool name <Tool name> in the tool category <Tool category name> of the XML file "<XML file name>"
ID:302025 Found a duplicate tool name with format line for tool name <Tool name> in the tool category name <Tool category name> of the XML file "<XML file name>". The duplicate tool name is ignored.
ID:302026 Found a missing attribute name at the tool name with format line, in the tool category <Tool category name> of the XML file "<XML file name>"
ID:302027 Found a missing attribute number at the tool name with format line, in the tool category <Tool category name> of the XML file "<XML file name>"
ID:302028 Found a duplicate aliases section for tool name <Tool name> in the tool category name <Tool category name> of the XML file "<XML file name>". The duplicate aliases section is ignored
ID:302029 Found a missing alias name attribute at alias line for the tool name <Tool name> in the tool category name <Tool category name> of the XML file "<XML file name>"
ID:302030 Found a missing supported families section for tool name <Tool name> in the tool category name <Tool category name> of the XML file "<XML file name>"
ID:302031 Found a duplicate supported families section for tool name <Tool name> in the tool category name <Tool category name> of the XML file "<XML file name>". The duplicate section is ignored.
ID:302032 Found missing family lines in the families section for tool name <Tool name> in the tool category name <Tool category name> of the XML file "<XML file name>"
ID:302033 Found a missing family name attribute in the family line for tool name <Tool name> in the tool category <Tool category name> of the XML file "<XML file name>"
ID:302034 Found an illegal family name <specified family name> for the tool name <Tool name> in the tool category <Tool category name> of the XML file "<XML file name>"
ID:302035 Found an illegal value name <specified value of setting> for the setting name <name of setting> in the tool category name <Tool category name> of the XML file "<XML file name>"
ID:302036 Found an illegal value <specified value of setting> in the setting name <name of setting> for the tool category name <Tool category name> of the XML file "<XML file name>". The setting name is ignored.
ID:302037 Setting name <name of setting> is not specified for the tool name <Tool name> or in its category in the XML file "<plug-in XML file name>". The default value is used.
ID:302038 Setting name <name of setting> is not specified for the tool name <Tool name> or in its category in the XML file "<plug-in XML file name>"
ID:302039 Setting name <name of setting> cannot not be specified for the tool name <Tool name> or in its category in the XML file "<plug-in XML file name>"
ID:302040 Found errors while processing plug-in in the XML file "<plug-in XML file name>". The file is ignored.
ID:302041 Display tool name <Tool name> in the XML file <plug-in XML file name> is in conflict with another display tool name specified for a tool in <XML file name or Quartus>
ID:302042 Tool <description of tool or alias name> of the tool name <Tool or alias name> in the XML file <plug-in XML file name> is in conflict with another tool name specified for a tool in <plug-in XML file name or Quartus>
ID:302043 Tool category name <Tool category name> in the XML file "<plug-in XML file name>" is not supported in the plug-in tools
ID:302044 Found an invalid tool format name <Tool format name> specified for the tool category name <Tool category name> in the XML file "<plug-in XML file name>"
ID:302045 Setting name <Setting name> in the tool name <Tool name> of the plug-in XML file "<plug-in XML file name>" is not valid for the tool format name <Tool format name>. The setting name is ignored.
ID:302046 Found an invalid setting value <Setting value> assigned to the setting name <Setting name> in the tool category name <Tool category name> of the XML file "<XML file name>"
ID:316000 Project name required
ID:316001 Illegal project name "<name>"
ID:316002 Illegal top-level entity name "<name>"
ID:316003 Can't run Timing Analyzer (quartus_sta) with options <name> and <name> -- options are mutually exclusive
ID:316004 Can't run the Timing Analyzer (quartus_sta) -- Analysis and Synthesis (quartus_map) failed
ID:316005 Illegal speed grade <name> for device <name>. The list of legal speed grades is <name>.
ID:316006 Illegal temperature grade <name> for device <name>
ID:316007 Illegal temperature grade <name> and speed grade <name> combination for device <name>
ID:316008 Selected feature of the Timing Analyzer is not available with your current license, or license does not exist
ID:316009 Running timing analysis with a modified temperature grade of the current device from <Name> to <Name>
ID:318000 Timing-Driven Synthesis is skipped because it could not initialize the timing model
ID:329000 Unable to compute I/O buffer delays for pin "<name>" using Advanced I/O Timing due to problematic board trace model; using capacitive load of <number> pF to determine buffer delay
ID:329001 Unable to simulate I/O buffer for <num> pin(s) at the corner <corner> of the board trace model
ID:329002 Unable to simulate I/O buffer for pin "<name>" due to a problematic board trace model. The Quartus Prime software will use the default board trace model for the I/O buffer
ID:329003 Unable to simulate the I/O buffer for pin "<name>". The signal swing at the near-end or far-end of the board trace did not cross the VMEAS point for the I/O standard. The Quartus Prime software will use the default board trace model for the I/O buffer.
ID:329004 The effective capacitive load computed from the board trace model specified for pin "<name>" is greater than the maximum allowable <number> pF.
ID:329005 Pin "<name>" has an invalid assignment "<assignment>" made on the board trace model parameter "<circuit element>", using the default board trace parameters for this pin.
ID:329006 Some pins have illegal board trace models.
ID:329007 Board trace assignment "<parameter>" on pin "<name>" must have a capacitance value of less than <value>
ID:329008 Board trace assignment "<parameter>" on pin "<name>" must have a series resistance value of less than <value>
ID:329009 Board trace assignment "<parameter>" on pin "<name>" must have a parallel resistance value of less than <value>
ID:329010 Capacitance parameter for the <location> transmission line is missing or illegal in the board trace assignment for pin "<name>"
ID:329011 Inductance parameter for the <location> transmission line is missing or illegal in the board trace assignment for pin "<name>"
ID:329012 Capacitance and inductance parameters for the <location> transmission line are missing or illegal in the board trace assignment for pin "<name>"
ID:329013 Board trace assignment "<parameter>" on pin "<name>" must contain a positive value
ID:329014 Delay for pin "<name>" is longer than 10ns. Advanced I/O Timing does not support <location> transmission lines with delays longer than 10ns.
ID:329015 Ignoring board trace model assignment <name> made on the negative terminal "<name>"
ID:329016 Reading Electronic Board Description File "<filename>"
ID:329017 I/O Output Timing Vmeas value for <key> is out of range for pin "<name>"
ID:329018 The I/O timing model for <name> is not correlated to the silicon. The I/O timing model is subject to change in the Quartus Prime software version 11.1.
ID:330000 Timing-Driven Synthesis is skipped because it could not initialize the timing netlist
ID:332000 <Message String>
ID:332001 The selected device family is not supported by the report_metastability command.
ID:332004 The collections specified by this assignment were not specific enough (-from * -thru * -to * is not allowed). This assignment will be ignored.
ID:332005 The calculated rise and fall waveform edges for clock: <Clock Name> were found to be identical (rise: <Rise Edge>, fall: <Fall Edge>). This clock will be ignored.
ID:332006 The calculated rise and fall waveform edges for clock: <Clock Name> were found to have a difference that is greater than or equal to the period value for this clock (rise: <Rise Edge>, fall: <Fall Edge>). This clock will be ignored.
ID:332008 Read_sdc failed due to errors in the SDC file
ID:332010 The option -less_than_slack with value <Time Value> is not recognized as a valid time value
ID:332011 Constraint <Constraint> is ignored
ID:332012 Synopsys Design Constraints File file not found: '<SDC File name>'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
ID:332013 The specified clock: '<clock_name>' cannot be found.
ID:332014 The requested histogram cannot be created.
ID:332015 Clock <name> has no paths with slack. Specify a clock that has paths with slack.
ID:332016 Argument: the -master_clock option must contain exactly one valid clock.
ID:332017 Command get_clock_info option <name> is invalid for clock: <name> because this clock is illegal. Run update_timing_netlist for more details.
ID:332018 Argument <Argument Name> is not <Article> <Required Arg Type List>
ID:332019 Argument <Argument Name> is an empty collection
ID:332020 Argument <Argument Name> gives an empty collection
ID:332021 Argument <Argument Name> is a collection with more than one object
ID:332022 Argument <Argument Name> gives a collection with more than one object
ID:332023 Argument <Argument Name> is a collection that is not of <Required Col Type List> type
ID:332024 Argument <Argument Name> gives a collection that is not of <Required Col Type List> type
ID:332025 Argument <Argument Name> is not a collection ID
ID:332026 Argument <Argument Name> is a collection ID that does not link to any collection
ID:332027 Argument <Argument Name> is not a legal object
ID:332028 Argument <Argument Name> is an object that is not of <Obj Type List> type
ID:332029 Argument <Argument Name> gives an object that is not of <Obj Type List> type
ID:332030 Argument <Argument Name> is not an object ID
ID:332031 Argument <Argument Name> is an object ID that does not link to any object
ID:332032 Argument <Argument Name> is an object filter that matches no objects
ID:332033 Argument <Argument Name> is an object filter that matches more than one object
ID:332034 Specified master clock: <Master Clock Name> not found on or feeding the specified source node: <Source Node>
ID:332035 No clocks found on or feeding the specified source node: <Source Node>
ID:332036 Clock: <Clock Name> found as a potential master clock candidate
ID:332037 Update_timing_netlist must be called before the command <Command name> can be executed
ID:332038 Item <Collection description> of collection type of <Collection type string> is not supported by SDC2EDA Writer
ID:332039 Object <Object description> of object type of <Object type string> is not supported by SDC2EDA Writer
ID:332040 Constraint <Collection type (source, destination, through or target)> collection is empty
ID:332041 Cannot find corresponding <Pin type (synch, asynch, clock, fanout, etc.)> pins of register <Register name>
ID:332042 Source node: <Source Node Name> exists in the clock target list
ID:332043 Overwriting existing clock: <Clock Name>
ID:332044 Rise and fall source and destination collections can only be clock collections. The <From or To> collection is not valid.
ID:332046 Timing netlist is empty. No timing reports will be generated.
ID:332047 Ignored assignment: <Assignment Name>
ID:332048 Ignored <name>: <text>
ID:332049 Ignored <name> at <file>(<number>): <text>
ID:332050 <text>
ID:332051 Check timing found bad checks specified by user. Only reporting valid checks.
ID:332052 <Assignment Name> is not a recognized check performed by check_timing
ID:332053 Assignment <name> is accepted but has some problems: <text>
ID:332054 Assignment <name> is accepted but has some problems at <name>(<number>): <text>
ID:332055 Command <Assignment Name> failed
ID:332056 <Message String>
ID:332057 Command <Command Name> could not find any constraints or exceptions to report
ID:332058 No ignored assignments to report
ID:332059 The set_active_clocks command has set all clocks to inactive
ID:332060 Node: <Node name> was determined to be a clock but was found without an associated clock assignment.
ID:332061 Virtual clock <Clock Name> is never referenced in any input or output delay assignment.
ID:332062 The clock <Clock Name> was found in more than one -group argument. A clock cannot be in a different group from itself.
ID:332063 Cannot find the specified edge.
ID:332064 Cannot find the specified register
ID:332065 Delay value "<Delay>" is not valid
ID:332066 Cannot find the specified collection with name of <Collection name>.
ID:332067 The <family name> Device Family does not support the --risefall option. Option will be ignored.
ID:332068 No clocks defined in design.
ID:332069 <message>
ID:332070 Port "<name>" relative to the <name> edge of clock "<name>" does not specify a <number>-<number> <text> delay
ID:332071 Port "<name>" relative to the reference pin "<name>" of the <name> edge of clock "<name>" does not specify a <number>-<number> <text> delay
ID:332072 Trying to set <First Latency> clock latency that is <Comparison> than previously set <Second Latency> latency. New <First Latency> latency was ignored.
ID:332073 Trying to set clock latency using the -clock option when object_list is of type clock. Ignoring the -clock option as it only applies to nodes.
ID:332074 "<Delay>" is not a valid delay value.
ID:332075 Positional argument <targets> with value <Object List Value>: Port <Port Name> is not an <Port Type> port.
ID:332076 Positional argument: object_list targets with value <Object List Value> contains no <Port Type> ports
ID:332077 Set_input_delay/set_output_delay has replaced one or more delays on port "<Port>". Use -add_delay option if you meant to add additional constraints.
ID:332078 Argument -reference_pin with value <Object List> contains zero elements.
ID:332079 Reference pin <Reference Pin> is invalid. It is not clocked by the clock specified in set_input_delay/set_output_delay's -clock option.
ID:332080 Option <name>: <text>
ID:332081 Design contains combinational loop of <number> nodes. Estimating the delays through the loop.
ID:332082 All paths through the combinational loop are disabled.
ID:332083 Incorrect assignment for clock. Source node: <Source Node> already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated.
ID:332084 Option <name>: <text>
ID:332085 Time value "<Time Value>" is not valid
ID:332086 Ignoring clock spec: <Clock Name> Reason: <Reason> <Parent clock>. Clock assignment is being ignored.
ID:332087 The master clock for this clock assignment could not be derived. Clock: <Clock Name> was not created.
ID:332088 No paths exist between clock target "<Node Name>" of clock "<Clock Name>" and its clock source. Assuming zero source clock latency.
ID:332089 <Argument Name> with value <Collection Filter> could not match any element of the following types: <Collection Allowed Types>
ID:332090 <Argument Name> with value <Collection Filter> contains more than one element
ID:332091 <Argument Name> with value <Collection Filter> contains zero elements
ID:332092 Collection filter <Argument Name> with value <Collection Filter> requires type <Required Type>, but found type <Found Type>.
ID:332093 Collections <Collection 1> and <Collection 2> are not compatible for <Command Name>.
ID:332094 Argument <Argument Name> with value <Collection Filter> contains zero nets
ID:332095 <msg>
ID:332096 The derive_clocks command did not find any clocks to derive. No clocks were created or changed.
ID:332097 The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network.
ID:332098 <Message String>
ID:332099 You called the derive_pll_clocks command. User-defined clock found on pll: <Target Node Name>. Original clock has priority over derived pll clocks. No clocks added to this pll.
ID:332100 You called the derive_lvds_clocks command. User-defined clock found on the register: <Target Node Name>. Original clock has priority over derived LVDS clocks. No clocks added to this register.
ID:332101 Design is fully constrained for <Setup or hold> requirements
ID:332102 Design is not fully constrained for <Setup or hold> requirements
ID:332103 Returned collection objects are limited by the default setting limit, <Limit>
ID:332104 Reading SDC File: '<SDC File Name>'
ID:332105 <Message String>
ID:332106 <Message String>
ID:332107 <Message String>
ID:332108 <Message String>
ID:332109 <Message String>
ID:332110 <Message String>
ID:332111 <Message String>
ID:332112 <Message String>
ID:332113 <Message String>
ID:332114 <Message String>
ID:332115 <Message String>
ID:332116 <Message String>
ID:332117 <Message String>
ID:332118 <Message String>
ID:332119 <Message String>
ID:332120 <Message String>
ID:332121 <Message String>
ID:332122 <Message String>
ID:332123 <Message String>
ID:332124 <Message String>
ID:332125 Found combinational loop of <number> nodes
ID:332126 Node "<name>"
ID:332127 Assuming a default timing requirement
ID:332128 Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
ID:332129 Detected timing requirements -- optimizing circuit to achieve only the specified requirements
ID:332130 Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
ID:332131 Timing report panel "<name>" was deleted.
ID:332132 Timing report panel "<original name>" was renamed to "<new name>".
ID:332133 No timing report panel with a name matching "<name>" was found.
ID:332134 Maximum precision of decimal places for <Name> is <Number>
ID:332135 Project does not include any partitions
ID:332136 Option <Option Name> is not supported by <Command Name>
ID:332137 No locations were found
ID:332138 Assignment group <Assignment Group Name> couldn't be found.
ID:332139 SDC Command entered is not currently supported by the Timing Analyzer.
ID:332140 No <Analysis Type> paths to report
ID:332141 Option <Rise/Fall Option> requires -no_logic to be specified
ID:332143 No user constrained clock uncertainty found in the design. Calling <command>
ID:332144 No user constrained <name> found in the design. They will be automatically derived.
ID:332145 Command "<command>" found in SDC file is not a proper SDC command and is being ignored
ID:332146 Worst-case <Analysis Type> slack is <Number>
ID:332147 Family name "<name>" is illegal
ID:332148 Timing requirements not met
ID:332149 Intel strongly recommends that you perform SI analysis for the chosen Drive Strength and Output Pin Load combination.
ID:332150 Cannot use the '<Clock Filter Option Name>' option when a clock collection is used for the '<Endpoint Filter Option Name>' option
ID:332151 Clock uncertainty is not calculated until you update the timing netlist.
ID:332152 Existing clock uncertainty assignments were detected. They will take precedence over the derive_clock_uncertainty command
ID:332153 Family doesn't support jitter analysis.
ID:332154 The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
ID:332155 Fmax Summary
ID:332156 <Message String>
ID:332157 The base clock assignment for generated clock <PLL clock name> cannot be derived
ID:332158 Clock uncertainty characteristics of the <Family> device family are preliminary
ID:332159 No clocks to report
ID:332161 The base clock assignment for generated clock <PLL clock name> cannot be derived
ID:332162 Node: <Node Name> does not have a clock assignment. DQS delay will be calculated using DQS input frequency
ID:332163 <Message String>
ID:332164 Evaluating HDL-embedded SDC commands
ID:332165 Entity <Entity Name>
ID:332166 <SDC Command>
ID:332167 No <Analysis Type> clock uncertainty specified for this clock to clock transfer.
ID:332168 The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
ID:332169 From <Clock Name> to <Clock Name> (<Analysis Type>)
ID:332170 <Analysis Type> uncertainty <Number> is less than the recommended uncertainty <Number>
ID:332171 The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command
ID:332172 <Analysis Type> clock transfer from <Clock Name> to <Clock Name> has uncertainty <Number> that is less than the recommended uncertainty <Number>
ID:332173 Ignored filter: <Filter> could not be matched with a <Type>
ID:332174 Ignored filter at <name>(<number>): <name> could not be matched with a <type>
ID:332175 Overwriting existing derive_clock_uncertainty assignment
ID:332176 Previous call "<Command Name>" is overwritten by the new call "<Command Name>"
ID:332177 No <Name>dedicated SERDES <Name> circuitry present in device or used in design
ID:332178 No annotated delays found on the design
ID:332179 No set_timing_derate assignments found on the design
ID:332180 <Argument Name> collection with value <Collection Filter> must include output pins or nets
ID:332181 <Message String>
ID:332182 <Message String> path is found satisfying assignment "<Message String>". This assignment will be ignored.
ID:332183 <Message String> path is found. This report will be ignored.
ID:332184 Input port <Name> has no clock(s) assigned to it
ID:332185 Clock port <Name> has multiple clock assignments
ID:332186 Clock <name> is not found on clock port <name>
ID:332187 Argument <name> with value <number>: Port <name> is not an <type> port
ID:332188 Argument <name> with value <number> contains no <type> ports
ID:332189 derive_pll_clocks was called multiple times with different options. Repeated calls to derive_pll_clocks do not modify existing clocks.
ID:332190 Using the <Name> option with a derate factor of <Number>, i.e., <Name> than 1.0, causes less conservative delays which might lead to optimistic results from timing analysis.
ID:332191 Clock target <Name> of clock <Name> is fed by another target of the same clock.
ID:332192 "<number>" delay setting is not valid
ID:332193 "<number>" is not a valid iteration value
ID:332194 Current device family does not support crosstalk analysis
ID:332195 Found minimum delays greater than maximum delays for <number> timing edges
ID:332196 Edge from "<name>" to "<name>"
ID:332197 Results limited to <number> timing edges
ID:332198 Analyzing the post-synthesis netlist because the Fitter has not been run. Timing analysis will be approximate.
ID:332199 Ignored -post_map option. The Timing Analyzer does not allow timing analysis of the post-synthesis netlist after you run the Fitter.
ID:332202 <Message String>
ID:335006 Ignored timing assignments to "<name>" -- cannot find entity in netlist
ID:335091 The Timing Analyzer found <number of latches> latches that cannot be analyzed as synchronous elements. For more details, run the Check Timing command in the Timing Analyzer to see the list of unsupported latches.
ID:335095 The Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family.
ID:335097 The Timing Analyzer is analyzing <number of latches> registers as latches. For more details, view the "User-Specified and Inferred Latches" table in the Synthesis report.
ID:336004 The Timing Analyzer will use the Classic Timing Analyzer's FMAX_REQUIREMENT assignment (or --fmax command-line argument) as default timing requirement. Any other Classic Timing Analyzer assignment will be ignored.
ID:343000 Process is currently running and must be stopped before closing the Quartus Prime software.
ID:345000 Could not find hierarchy name for connection <connection name>.
ID:345001 Linking device <hardware name> on hardware <device name> using project .jdi file in <jdi file name>.
ID:345002 Linking device <hardware name> on hardware <device name> using .jdi file <jdi file name>.
ID:345003 Using hierarchy path <hpath name> for connection <connection name>.
ID:345004 Relinking your project to your device after refreshing connection.
ID:345005 Could not create process for System Console using command <command name>. Ensure that System Console is correctly installed.
ID:345006 Could not find the TCP port for the System Console process within the elapsed time limit.
ID:345007 Could not cleanly shut down System Console. Killing the System Console process.
ID:345008 The connection to System Console was forcibly killed. Check if shutdown_systemconsole was performed.
ID:345009 A connection to System Console was successfully established on port <tcp port>
ID:345010 An error occurred when you were trying to shut down System Console. <error msg>
ID:345011 The connection to System Console has been shutdown successfully.
ID:345012 The chosen generic device family is illegal. Choose a legal device family.
ID:345013 The chosen device family is illegal. Choose a legal device family.
ID:345014 The use of an "AUTO" device is not supported by the External Memory Interface Toolkit. Choose a specific device.
ID:345015 The chosen device is illegal. Choose a legal device family.
ID:345016 Successfully established a connection to target <connection path>.
ID:345017 The specified emulation mode XML file <xml file> cannot be found. Verify that the file exists.
ID:345018 Emulation mode was enabled, but no emulation XML file was specified. Ensure that a valid file name is specified using the quartus.ini emitt_emulation_file.
ID:345019 An error occurred while parsing the XML emulation file <xml file>. Verify that the syntax of the XML is correct.
ID:345020 Successfully created <report type> report for target <connection path> in <time> seconds.
ID:345021 An error occurred when creating the <report type> report for target <connection path>.
ID:345022 The selected device family <family name> is not supported by the external memory interface toolkit.
ID:345023 Successfully wrote report to <report file> for target <connection path>.
ID:345024 Connection target has not completed the generation of the report.
ID:345025 Calibration was not detected to complete for connection target in the timeout interval.
ID:345026 Retrieval of the debug log did not complete for connection target in the timeout interval.
ID:345027 Reading connection log for connection target. This may take some time.
ID:345028 Calibration report could not be generated as the report was disabled.
ID:345029 The margin report could not be generated as the report was not enabled.
ID:345030 Connection target <Connection Target> failed to execute the command. The interface was not marked as ready to accept commands within the allowed time.
ID:345031 Connection target <Connection Target> failed to execute the command. A response was not received from the connection target within the allowed time.
ID:345032 Connection target <Connection Target> failed to execute the command. The command with code <Connection Code> was identified as illegal by the connection target.
ID:345033 Successfully executed command <command name> on target <connection path>.
ID:345034 Cannot establish a connection to target <Connection Target> as a connection has already been established.
ID:345035 Command cannot be executed as the payload element number <Element Number> supplied to the command <Command Name> was illegal.
ID:345036 Command cannot be executed as the payload element number <Element Number> supplied to the command <Command Name> was illegal.
ID:345037 Command <Command Name> cannot be executed as the command requires a payload of size <Expected Payload> and a payload of size <Actual Payload> was provided.
ID:345038 Command <Command Name> could not be executed as the command does not accept a payload and a payload of size <Actual Payload> was provided.
ID:345039 Command <Command Name> could not be executed as the command requires a payload of at least <Min Payload> and a payload of size <Actual Payload> was provided.
ID:345040 Could not accurately determine connection type for connection <connection name> as the clock of the connection is inactive.
ID:345041 No active clock was detected for connection <connection name>.
ID:345042 Preparing to query the <Setting> of group <Group> for target <connection path>.
ID:345043 Preparing to rerun memory interface calibration for target <connection path>.
ID:345044 Preparing to send a no-operation command to target <connection path>.
ID:345045 Preparing to query calibration status for the target <connection path>.
ID:345046 Preparing to query parameterization information for the target <connection path>.
ID:345047 Preparing to create a connection to System Console. This may take several seconds.
ID:345048 Memory interface <Connection> calibration ended after <Time> seconds.
ID:345049 Preparing to query the <Setting> of bit <Pin> of the current group for target <connection path>.
ID:345050 Preparing to clear the <Setting> calibration mask for target <connection path>.
ID:345051 Preparing to set the <Setting> calibration mask for <Name> <id> target <connection path>.
ID:345052 Calibration must be rerun after enabling the margining report to regenerate calibration results.
ID:345053 Calibration must be rerun after changing ranks or groups masked from calibration.
ID:345054 Efficiency monitor <Connection Name> could not be stopped.
ID:345055 Efficiency monitor <Connection Name> could not start as it is currently running.
ID:345056 Noise generator <Connection Name> could not be stopped.
ID:345057 Noise generator <Connection Name> could not start as the noise generator is running.
ID:345058 Noise generator clock <Connection Name> could not be stopped.
ID:345059 Noise generator clock <Connection Name> could not start.
ID:345060 Successfully dumped internal data for connection <id>.

Contact Intel | Terms of Use | Trademarks | Privacy | Send Feedback

Copyright© Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.