ID:23336 WYSIWYG RAM primitive "<name>" has different clock signals feeding bits of <name> input bus port
CAUSE: The specified WYSIWYG RAM primitive has different clock signals feeding the bits of the specified input bus port. All of the bits of the port must be fed by the same clock signal.
ACTION: If you are using an EDA tool, please contact the technical support for the EDA tool regarding this message. For further assistance, contact Intel Technical Support by creating a Service Request at www.altera.com/mysupport.