ID:13320 Verilog HDL User-Defined Primitive (UDP) Declaration warning at <location>: UDP table is empty

CAUSE: In a User-Defined Primitive (UDP) Declaration at the specified location in a Verilog Design File (.v), you used a UDP table that is empty. As a result, Integrated Syntheses will create an empty primitive gate.

ACTION: No action is required. To avoid receiving this message in the future, enter the correct logic function information into the UDP table.