ID:15705 Ignored locations or region assignments to the following nodes

CAUSE: The Fitter ignored assignments to the following node names because the specified node names do not exist in the design. These assignments can be created by the Quartus Prime software in the following scenarios:

• The design contains old assignments that are no longer valid. Invalid assignments can occur when the source files change.
• The design was previously compiled with Fitter netlist optimizations and then back-annotated. Back-annotation writes out location assignments for any nodes created by Fitter netlist optimizations. However, there is no guarantee that Fitter netlist optimizations will re-create the same nodes on this compile. The recommended method to preserve the results of a compile, with Fitter netlist optimizations on, is to back-annotate locations and to use a Verilog Quartus Mapping File (.vqm) to save the netlist changes made by the Fitter.
• The design uses a VQM file as source that was generated from a previous compilation with register packing on and then back-annotated. Back-annotation writes out location assignments for both parts of a packing operation. Because the VQM file represents the netlist after the packing operations have already been performed, one of the assignments may no longer apply.