ID:13297 Verilog HDL error at <location>: expression cannot reference entire array "<name>"

CAUSE: In a Verilog Design File (.v) at the specified location, you attempted to reference an entire array. Verilog HDL does not support references or assignments to all or part of an array, only to individual elements in an array.

ACTION: Modify the expression so that it refers to an element in the array, as shown in the following example:

module mem_fixed(x);
   output [1:0] x;
   reg mem1bit[1:0];
   always
   begin
      x[1] = mem1bit[1];
      x[0] = mem1bit[0];
   end
endmodule