ID:21392 Verilog HDL warning at <location>: generate block is allowed only inside loop and conditional generate in SystemVerilog mode

CAUSE: Intel Quartus Prime Synthesis generated the specified warning message for the specified location in a Design File.

ACTION: No action is required. To remove the warning, address the issue identified by the message text. A future version of the Intel Quartus Prime software will provide more extensive Help for this warning message.