ID:22921 Verilog HDL error at <location>: hierarchy depth of <number> was exceeded; value of runtime-flag 'veri_max_hierarchy_depth_in_static_elab' may be increased if desired

CAUSE: Intel Quartus Prime Synthesis generated the specified error message for the specified location in a Design File.

ACTION: Fix the problem identified by the message text. A future version of the Intel Quartus Prime software will provide more extensive Help for this error message.