ID:13458 Verilog HDL Continuous Assignment error at <location>: object "<text>" on left-hand side of assignment must have a net type

CAUSE: The left-hand side (LHS) of a continuous assignment at the specified location in a Verilog Design File (.v) contains the specified variable, which does not have a net type. However, only variables with a net type (wire, wand, etc.) may be assigned using continuous assignments.

ACTION: Declare the specified variable with a net type, or assign it a value in a procedural statement such as an always construct.