Cache_Coherency_Unit Summary

Registers in NoC accessible through regbus

Base Address: 0xF7000000

Register Address Offset	Bit Fields
`i_ccu_noc_registers`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ios_sprt_iospace0a_0` `0x38400` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x2000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x2000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x2000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x2000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ios_sprt_iospace0b_0` `0x38420` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ios_sprt_iospace1a_0` `0x38440` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E40000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E40000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E40000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E40000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ios_sprt_iospace1b_0` `0x38460` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E80000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ios_sprt_iospace1c_0` `0x38480` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3F00000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3F00000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3F00000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3F00000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ios_sprt_iospace1d_0` `0x384A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3F80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3F80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3F80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3F80000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ios_sprt_iospace1e_0` `0x384C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FC0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ios_sprt_iospace1f_0` `0x384E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FE0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FE0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FE0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FE0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ios_sprt_iospace1g_0` `0x38500` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_mem0_sprt_memspace0_0` `0x38520` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x0`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_mem0_sprt_memspace1a_0` `0x38540` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x4000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x4000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x4000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x4000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_mem0_sprt_memspace1b_0` `0x38560` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x8000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x8000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x8000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x8000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_mem0_sprt_memspace1c_0` `0x38580` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x10000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x10000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x10000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x10000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_mem0_sprt_memspace1d_0` `0x385A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x20000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x20000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x20000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x20000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_mem0_sprt_memspace1e_0` `0x385C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x40000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x40000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x40000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x40000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ram_sprt_ramspace0_0` `0x385E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF8000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF8000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF8000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF8000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ram_sprt_ramspace1_0` `0x38600` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF9000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF9000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF9000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF9000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ram_sprt_ramspace2_0` `0x38620` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFA000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFA000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFA000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFA000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ram_sprt_ramspace3_0` `0x38640` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFA800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFA800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFA800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFA800`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ram_sprt_ramspace4_0` `0x38660` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFB000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFB000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFB000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFB000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_adbase_mem_ram_sprt_ramspace5_0` `0x38680` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFB800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFB800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFB800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFB800`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ios_sprt_iospace0a_0` `0x38408` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFF000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFF000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFF000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFF000000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ios_sprt_iospace0b_0` `0x38428` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFF800000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFF800000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFF800000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFF800000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ios_sprt_iospace1a_0` `0x38448` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFC0000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ios_sprt_iospace1b_0` `0x38468` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFF80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFF80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFF80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFF80000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ios_sprt_iospace1c_0` `0x38488` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFF80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFF80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFF80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFF80000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ios_sprt_iospace1d_0` `0x384A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFC0000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ios_sprt_iospace1e_0` `0x384C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFE0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFE0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFE0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFE0000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ios_sprt_iospace1f_0` `0x384E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF0000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ios_sprt_iospace1g_0` `0x38508` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF8000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF8000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF8000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF8000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_mem0_sprt_memspace0_0` `0x38528` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFE000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFE000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFE000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFE000000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_mem0_sprt_memspace1a_0` `0x38548` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFC000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFC000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFC000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFC000000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_mem0_sprt_memspace1b_0` `0x38568` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FF8000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FF8000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FF8000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FF8000000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_mem0_sprt_memspace1c_0` `0x38588` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FF0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FF0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FF0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FF0000000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_mem0_sprt_memspace1d_0` `0x385A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FE0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FE0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FE0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FE0000000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_mem0_sprt_memspace1e_0` `0x385C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FC0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FC0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FC0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FC0000000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ram_sprt_ramspace0_0` `0x385E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ram_sprt_ramspace1_0` `0x38608` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ram_sprt_ramspace2_0` `0x38628` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ram_sprt_ramspace3_0` `0x38648` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ram_sprt_ramspace4_0` `0x38668` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_admask_mem_ram_sprt_ramspace5_0` `0x38688` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_ccc0_mprt_6_81_am_bridge_id` `0x3BD08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x6`
`bridge_ccc0_mprt_6_81_am_err` `0x3BE00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`E40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`E34` `RW 0x0`	`E33` `RW 0x0`	`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`E24` `RW 0x0`	`E23` `RW 0x0`	`E22` `RW 0x0`	`E21` `RW 0x0`	`E20` `RW 0x0`	`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`E8` `RW 0x0`	`E7` `RW 0x0`	`E6` `RW 0x0`	`E5` `RW 0x0`	`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_ccc0_mprt_6_81_am_intm` `0x3BE40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`M40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`M34` `RW 0x1`	`M33` `RW 0x1`	`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`M24` `RW 0x0`	`M23` `RW 0x0`	`M22` `RW 0x1`	`M21` `RW 0x0`	`M20` `RW 0x0`	`M19` `RW 0x1`	`M18` `RW 0x0`	`M17` `RW 0x0`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`M8` `RW 0x0`	`M7` `RW 0x0`	`M6` `RW 0x1`	`M5` `RW 0x0`	`M4` `RW 0x0`	`M3` `RW 0x1`	`M2` `RW 0x0`	`M1` `RW 0x0`	`M0` `RW 0x1`
`bridge_ccc0_mprt_6_81_am_sts` `0x3BD00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_8` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_8` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_8` `RO 0x0`								`AWO` `RO 0x0`	`ARO` `RO 0x0`	`AWS` `RO 0x0`	`ARS` `RO 0x0`	`WOE` `RO 0x1`	`ROE` `RO 0x1`	`WOF` `RO 0x0`	`ROF` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_0` `0x38130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_1` `0x38138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_10` `0x38180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_11` `0x38188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_12` `0x38190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_13` `0x38198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_14` `0x381A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_15` `0x381A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_2` `0x38140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_3` `0x38148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_4` `0x38150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_5` `0x38158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_6` `0x38160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_7` `0x38168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_8` `0x38170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brs_9` `0x38178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_mprt_6_81_brus` `0x381B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_ccc0_mprt_6_81_btrl_0` `0x38080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_ccc0_mprt_6_81_btrl_1` `0x38088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_ccc0_mprt_6_81_btrl_2` `0x38090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_ccc0_mprt_6_81_btrl_3` `0x38098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_ccc0_mprt_6_81_btus_0` `0x38058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_ccc0_mprt_6_81_btus_1` `0x38060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_ccc0_mprt_6_81_p_0` `0x38000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_ccc0_mprt_6_81_p_1` `0x38008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_ccc0_mprt_6_81_p_2` `0x38010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_ccc0_mprt_6_81_p_3` `0x38018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_ccc0_mprt_6_81_rxid` `0x381B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x6`
`bridge_ccc0_mprt_6_81_txid` `0x38078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x6`
`bridge_ccc0_sprt_7_82_as_bridge_id` `0x3DD08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x7`
`bridge_ccc0_sprt_7_82_as_err` `0x3DE00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_ccc0_sprt_7_82_as_intm` `0x3DE40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`M19` `RW 0x1`	`M18` `RW 0x0`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`M4` `RW 0x1`	`M3` `RW 0x0`	`M2` `RW 0x0`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_ccc0_sprt_7_82_as_sts` `0x3DD00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_4` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_4` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_4` `RO 0x0`												`ROE` `RO 0x1`	`WOE` `RO 0x1`	`ROF` `RO 0x0`	`WOF` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_0` `0x3C130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_1` `0x3C138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_10` `0x3C180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_11` `0x3C188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_12` `0x3C190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_13` `0x3C198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_14` `0x3C1A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_15` `0x3C1A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_2` `0x3C140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_3` `0x3C148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_4` `0x3C150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_5` `0x3C158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_6` `0x3C160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_7` `0x3C168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_8` `0x3C170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brs_9` `0x3C178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ccc0_sprt_7_82_brus` `0x3C1B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_ccc0_sprt_7_82_btrl_0` `0x3C080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_ccc0_sprt_7_82_btrl_1` `0x3C088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_ccc0_sprt_7_82_btrl_2` `0x3C090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_ccc0_sprt_7_82_btrl_3` `0x3C098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_ccc0_sprt_7_82_btus_0` `0x3C058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_ccc0_sprt_7_82_btus_1` `0x3C060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_ccc0_sprt_7_82_p_0` `0x3C000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_ccc0_sprt_7_82_p_1` `0x3C008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_ccc0_sprt_7_82_p_2` `0x3C010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_ccc0_sprt_7_82_p_3` `0x3C018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_ccc0_sprt_7_82_rxid` `0x3C1B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x7`
`bridge_ccc0_sprt_7_82_txid` `0x3C078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x7`
`bridge_cpu0_mprt_0_37_SYSCOACK_reg` `0x7F78` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD` `RO 0x0`															`STAT_REG` `RO 0x1`
`bridge_cpu0_mprt_0_37_SYSCOREQ_reg` `0x7F70` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD` `RO 0x0`															`REQ_REG` `RW 0x1`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ddrreg_sprt_ddrregspace0_0` `0x4400` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E00000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E00000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E00000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E00000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_gic_sprt_gicspace_0` `0x4420` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFF000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace0a_0` `0x4440` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x2000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x2000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x2000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x2000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace0b_0` `0x4460` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace1a_0` `0x4480` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E40000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E40000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E40000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E40000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace1b_0` `0x44A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E80000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace1c_0` `0x44C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3F00000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3F00000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3F00000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3F00000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace1d_0` `0x44E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3F80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3F80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3F80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3F80000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace1e_0` `0x4500` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FC0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace1f_0` `0x4520` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FE0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FE0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FE0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FE0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace1g_0` `0x4540` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace2a_0` `0x4560` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x80000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x80000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x80000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x80000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace2b_0` `0x4580` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x100000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x100000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x100000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x100000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ios_sprt_iospace2c_0` `0x45A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x200000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x200000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x200000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x200000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_mem0_sprt_memspace0_0` `0x45C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x0`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_mem0_sprt_memspace1a_0` `0x45E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x4000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x4000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x4000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x4000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_mem0_sprt_memspace1b_0` `0x4600` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x8000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x8000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x8000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x8000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_mem0_sprt_memspace1c_0` `0x4620` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x10000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x10000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x10000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x10000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_mem0_sprt_memspace1d_0` `0x4640` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x20000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x20000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x20000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x20000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_mem0_sprt_memspace1e_0` `0x4660` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x40000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x40000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x40000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x40000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ram_sprt_ramspace0_0` `0x4680` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF8000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF8000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF8000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF8000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x1`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ram_sprt_ramspace1_0` `0x46A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF9000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF9000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF9000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF9000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ram_sprt_ramspace2_0` `0x46C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFA000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFA000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFA000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFA000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ram_sprt_ramspace3_0` `0x46E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFA800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFA800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFA800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFA800`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ram_sprt_ramspace4_0` `0x4700` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFB000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFB000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFB000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFB000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_ram_sprt_ramspace5_0` `0x4720` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFB800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFB800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFB800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFB800`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_rbm_s_regspace_rd_0` `0x4740` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3DC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3DC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3DC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3DC0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x1`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_adbase_mem_rbm_s_regspace_wr_0` `0x4760` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3DC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3DC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3DC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3DC0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x1`
`bridge_cpu0_mprt_0_37_am_admask_mem_ddrreg_sprt_ddrregspace0_0` `0x4408` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_gic_sprt_gicspace_0` `0x4428` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFFE00`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFFE00`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFFE00`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFFE00`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ios_sprt_iospace0a_0` `0x4448` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFF000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFF000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFF000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFF000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ios_sprt_iospace0b_0` `0x4468` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFF800000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFF800000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFF800000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFF800000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ios_sprt_iospace1a_0` `0x4488` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ios_sprt_iospace1b_0` `0x44A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFF80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFF80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFF80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFF80000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ios_sprt_iospace1c_0` `0x44C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFF80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFF80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFF80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFF80000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ios_sprt_iospace1d_0` `0x44E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ios_sprt_iospace1e_0` `0x4508` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFE0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFE0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFE0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFE0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ios_sprt_iospace1f_0` `0x4528` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ios_sprt_iospace1g_0` `0x4548` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF8000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF8000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF8000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF8000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ios_sprt_iospace2a_0` `0x4568` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3F80000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3F80000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3F80000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3F80000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ios_sprt_iospace2b_0` `0x4588` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3F00000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3F00000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3F00000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3F00000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ios_sprt_iospace2c_0` `0x45A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3E00000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3E00000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3E00000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3E00000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_mem0_sprt_memspace0_0` `0x45C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFE000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFE000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFE000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFE000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_mem0_sprt_memspace1a_0` `0x45E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFC000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFC000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFC000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFC000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_mem0_sprt_memspace1b_0` `0x4608` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FF8000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FF8000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FF8000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FF8000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_mem0_sprt_memspace1c_0` `0x4628` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FF0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FF0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FF0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FF0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_mem0_sprt_memspace1d_0` `0x4648` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FE0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FE0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FE0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FE0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_mem0_sprt_memspace1e_0` `0x4668` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FC0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FC0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FC0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FC0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ram_sprt_ramspace0_0` `0x4688` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x1`	`P` `RW 0x1`
`bridge_cpu0_mprt_0_37_am_admask_mem_ram_sprt_ramspace1_0` `0x46A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ram_sprt_ramspace2_0` `0x46C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ram_sprt_ramspace3_0` `0x46E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ram_sprt_ramspace4_0` `0x4708` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_ram_sprt_ramspace5_0` `0x4728` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_rbm_s_regspace_rd_0` `0x4748` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x1`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_admask_mem_rbm_s_regspace_wr_0` `0x4768` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x1`	`I` `RW 0x0`	`NS` `RW 0x1`	`P` `RW 0x1`
`bridge_cpu0_mprt_0_37_am_bridge_id` `0x7D08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x0`
`bridge_cpu0_mprt_0_37_am_err` `0x7E00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`E40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`E34` `RW 0x0`	`E33` `RW 0x0`	`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`E24` `RW 0x0`	`E23` `RW 0x0`	`E22` `RW 0x0`	`E21` `RW 0x0`	`E20` `RW 0x0`	`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`E8` `RW 0x0`	`E7` `RW 0x0`	`E6` `RW 0x0`	`E5` `RW 0x0`	`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_cpu0_mprt_0_37_am_intm` `0x7E40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`M40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`M34` `RW 0x1`	`M33` `RW 0x1`	`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`M24` `RW 0x0`	`M23` `RW 0x0`	`M22` `RW 0x1`	`M21` `RW 0x0`	`M20` `RW 0x0`	`M19` `RW 0x1`	`M18` `RW 0x1`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`M8` `RW 0x0`	`M7` `RW 0x0`	`M6` `RW 0x1`	`M5` `RW 0x0`	`M4` `RW 0x0`	`M3` `RW 0x1`	`M2` `RW 0x1`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_cpu0_mprt_0_37_am_sts` `0x7D00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_8` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_8` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_8` `RO 0x0`								`AWO` `RO 0x0`	`ARO` `RO 0x0`	`AWS` `RO 0x0`	`ARS` `RO 0x0`	`WOE` `RO 0x1`	`ROE` `RO 0x1`	`WOF` `RO 0x0`	`ROF` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_0` `0x4130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_1` `0x4138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_10` `0x4180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_11` `0x4188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_12` `0x4190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_13` `0x4198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_14` `0x41A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_15` `0x41A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_2` `0x4140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_3` `0x4148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_4` `0x4150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_5` `0x4158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_6` `0x4160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_7` `0x4168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_8` `0x4170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brs_9` `0x4178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_cpu0_mprt_0_37_brus` `0x41B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_cpu0_mprt_0_37_btrl_0` `0x4080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_cpu0_mprt_0_37_btrl_1` `0x4088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_cpu0_mprt_0_37_btrl_2` `0x4090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_cpu0_mprt_0_37_btrl_3` `0x4098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_cpu0_mprt_0_37_btus_0` `0x4058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_cpu0_mprt_0_37_btus_1` `0x4060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_cpu0_mprt_0_37_p_0` `0x4000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_cpu0_mprt_0_37_p_1` `0x4008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_cpu0_mprt_0_37_p_2` `0x4010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_cpu0_mprt_0_37_p_3` `0x4018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_cpu0_mprt_0_37_rxid` `0x41B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x0`
`bridge_cpu0_mprt_0_37_txid` `0x4078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x0`
`bridge_ddrreg_sprt_8_118_as_bridge_id` `0x9D08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x8`
`bridge_ddrreg_sprt_8_118_as_err` `0x9E00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_ddrreg_sprt_8_118_as_intm` `0x9E40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`M19` `RW 0x1`	`M18` `RW 0x0`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`M4` `RW 0x1`	`M3` `RW 0x0`	`M2` `RW 0x0`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_ddrreg_sprt_8_118_as_sts` `0x9D00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_4` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_4` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_4` `RO 0x0`												`ROE` `RO 0x1`	`WOE` `RO 0x1`	`ROF` `RO 0x0`	`WOF` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_0` `0x8130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_1` `0x8138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_10` `0x8180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_11` `0x8188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_12` `0x8190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_13` `0x8198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_14` `0x81A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_15` `0x81A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_2` `0x8140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_3` `0x8148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_4` `0x8150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_5` `0x8158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_6` `0x8160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_7` `0x8168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_8` `0x8170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brs_9` `0x8178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ddrreg_sprt_8_118_brus` `0x81B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_ddrreg_sprt_8_118_btrl_0` `0x8080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_ddrreg_sprt_8_118_btrl_1` `0x8088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_ddrreg_sprt_8_118_btrl_2` `0x8090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_ddrreg_sprt_8_118_btrl_3` `0x8098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_ddrreg_sprt_8_118_btus_0` `0x8058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_ddrreg_sprt_8_118_btus_1` `0x8060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_ddrreg_sprt_8_118_p_0` `0x8000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_ddrreg_sprt_8_118_p_1` `0x8008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_ddrreg_sprt_8_118_p_2` `0x8010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_ddrreg_sprt_8_118_p_3` `0x8018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_ddrreg_sprt_8_118_rxid` `0x81B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x8`
`bridge_ddrreg_sprt_8_118_txid` `0x8078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x8`
`bridge_dvm0_sprt_9_70_as_bridge_id` `0x41D08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x9`
`bridge_dvm0_sprt_9_70_as_err` `0x41E00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_dvm0_sprt_9_70_as_intm` `0x41E40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`M19` `RW 0x1`	`M18` `RW 0x0`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`M4` `RW 0x1`	`M3` `RW 0x0`	`M2` `RW 0x0`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_dvm0_sprt_9_70_as_sts` `0x41D00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_4` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_4` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_4` `RO 0x0`												`ROE` `RO 0x1`	`WOE` `RO 0x1`	`ROF` `RO 0x0`	`WOF` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_0` `0x40130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_1` `0x40138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_10` `0x40180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_11` `0x40188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_12` `0x40190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_13` `0x40198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_14` `0x401A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_15` `0x401A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_2` `0x40140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_3` `0x40148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_4` `0x40150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_5` `0x40158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_6` `0x40160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_7` `0x40168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_8` `0x40170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brs_9` `0x40178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_dvm0_sprt_9_70_brus` `0x401B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_dvm0_sprt_9_70_btrl_0` `0x40080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_dvm0_sprt_9_70_btrl_1` `0x40088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_dvm0_sprt_9_70_btrl_2` `0x40090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_dvm0_sprt_9_70_btrl_3` `0x40098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_dvm0_sprt_9_70_btus_0` `0x40058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_dvm0_sprt_9_70_btus_1` `0x40060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_dvm0_sprt_9_70_p_0` `0x40000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_dvm0_sprt_9_70_p_1` `0x40008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_dvm0_sprt_9_70_p_2` `0x40010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_dvm0_sprt_9_70_p_3` `0x40018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_dvm0_sprt_9_70_rxid` `0x401B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x9`
`bridge_dvm0_sprt_9_70_txid` `0x40078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x9`
`bridge_fpga0ace_mprt_1_118_SYSCOACK_reg` `0xFF78` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD` `RO 0x0`															`STAT_REG` `RO 0x1`
`bridge_fpga0ace_mprt_1_118_SYSCOREQ_reg` `0xFF70` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD` `RO 0x0`															`REQ_REG` `RW 0x1`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ddrreg_sprt_ddrregspace0_0` `0xC400` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E00000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E00000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E00000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E00000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ios_sprt_iospace0a_0` `0xC420` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x2000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x2000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x2000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x2000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ios_sprt_iospace0b_0` `0xC440` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ios_sprt_iospace1a_0` `0xC460` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E40000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E40000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E40000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E40000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ios_sprt_iospace1b_0` `0xC480` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E80000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ios_sprt_iospace1c_0` `0xC4A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3F00000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3F00000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3F00000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3F00000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ios_sprt_iospace1d_0` `0xC4C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3F80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3F80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3F80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3F80000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ios_sprt_iospace1e_0` `0xC4E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FC0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ios_sprt_iospace1f_0` `0xC500` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FE0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FE0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FE0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FE0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ios_sprt_iospace1g_0` `0xC520` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ios_sprt_iospace2a_0` `0xC540` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x80000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x80000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x80000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x80000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ios_sprt_iospace2b_0` `0xC560` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x100000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x100000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x100000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x100000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ios_sprt_iospace2c_0` `0xC580` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x200000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x200000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x200000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x200000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_mem0_sprt_memspace0_0` `0xC5A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x0`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_mem0_sprt_memspace1a_0` `0xC5C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x4000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x4000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x4000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x4000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_mem0_sprt_memspace1b_0` `0xC5E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x8000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x8000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x8000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x8000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_mem0_sprt_memspace1c_0` `0xC600` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x10000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x10000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x10000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x10000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_mem0_sprt_memspace1d_0` `0xC620` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x20000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x20000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x20000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x20000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_mem0_sprt_memspace1e_0` `0xC640` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x40000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x40000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x40000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x40000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ram_sprt_ramspace0_0` `0xC660` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF8000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF8000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF8000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF8000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x1`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ram_sprt_ramspace1_0` `0xC680` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF9000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF9000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF9000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF9000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ram_sprt_ramspace2_0` `0xC6A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFA000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFA000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFA000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFA000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ram_sprt_ramspace3_0` `0xC6C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFA800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFA800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFA800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFA800`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ram_sprt_ramspace4_0` `0xC6E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFB000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFB000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFB000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFB000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_adbase_mem_ram_sprt_ramspace5_0` `0xC700` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFB800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFB800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFB800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFB800`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ddrreg_sprt_ddrregspace0_0` `0xC408` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ios_sprt_iospace0a_0` `0xC428` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFF000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFF000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFF000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFF000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ios_sprt_iospace0b_0` `0xC448` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFF800000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFF800000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFF800000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFF800000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ios_sprt_iospace1a_0` `0xC468` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ios_sprt_iospace1b_0` `0xC488` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFF80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFF80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFF80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFF80000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ios_sprt_iospace1c_0` `0xC4A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFF80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFF80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFF80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFF80000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ios_sprt_iospace1d_0` `0xC4C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ios_sprt_iospace1e_0` `0xC4E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFE0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFE0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFE0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFE0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ios_sprt_iospace1f_0` `0xC508` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ios_sprt_iospace1g_0` `0xC528` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF8000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF8000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF8000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF8000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ios_sprt_iospace2a_0` `0xC548` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3F80000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3F80000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3F80000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3F80000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ios_sprt_iospace2b_0` `0xC568` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3F00000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3F00000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3F00000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3F00000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ios_sprt_iospace2c_0` `0xC588` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3E00000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3E00000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3E00000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3E00000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_mem0_sprt_memspace0_0` `0xC5A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFE000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFE000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFE000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFE000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_mem0_sprt_memspace1a_0` `0xC5C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFC000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFC000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFC000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFC000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_mem0_sprt_memspace1b_0` `0xC5E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FF8000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FF8000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FF8000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FF8000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_mem0_sprt_memspace1c_0` `0xC608` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FF0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FF0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FF0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FF0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_mem0_sprt_memspace1d_0` `0xC628` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FE0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FE0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FE0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FE0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_mem0_sprt_memspace1e_0` `0xC648` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FC0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FC0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FC0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FC0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ram_sprt_ramspace0_0` `0xC668` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x1`	`P` `RW 0x1`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ram_sprt_ramspace1_0` `0xC688` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ram_sprt_ramspace2_0` `0xC6A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ram_sprt_ramspace3_0` `0xC6C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ram_sprt_ramspace4_0` `0xC6E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_admask_mem_ram_sprt_ramspace5_0` `0xC708` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_bridge_id` `0xFD08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x1`
`bridge_fpga0ace_mprt_1_118_am_err` `0xFE00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`E40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`E34` `RW 0x0`	`E33` `RW 0x0`	`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`E24` `RW 0x0`	`E23` `RW 0x0`	`E22` `RW 0x0`	`E21` `RW 0x0`	`E20` `RW 0x0`	`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`E8` `RW 0x0`	`E7` `RW 0x0`	`E6` `RW 0x0`	`E5` `RW 0x0`	`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_fpga0ace_mprt_1_118_am_intm` `0xFE40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`M40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`M34` `RW 0x1`	`M33` `RW 0x1`	`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`M24` `RW 0x0`	`M23` `RW 0x0`	`M22` `RW 0x1`	`M21` `RW 0x0`	`M20` `RW 0x0`	`M19` `RW 0x1`	`M18` `RW 0x1`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`M8` `RW 0x0`	`M7` `RW 0x0`	`M6` `RW 0x1`	`M5` `RW 0x0`	`M4` `RW 0x0`	`M3` `RW 0x1`	`M2` `RW 0x1`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_fpga0ace_mprt_1_118_am_sts` `0xFD00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_8` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_8` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_8` `RO 0x0`								`AWO` `RO 0x0`	`ARO` `RO 0x0`	`AWS` `RO 0x0`	`ARS` `RO 0x0`	`WOE` `RO 0x1`	`ROE` `RO 0x1`	`WOF` `RO 0x0`	`ROF` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_0` `0xC130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_1` `0xC138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_10` `0xC180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_11` `0xC188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_12` `0xC190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_13` `0xC198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_14` `0xC1A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_15` `0xC1A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_2` `0xC140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_3` `0xC148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_4` `0xC150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_5` `0xC158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_6` `0xC160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_7` `0xC168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_8` `0xC170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brs_9` `0xC178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_brus` `0xC1B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_btrl_0` `0xC080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_fpga0ace_mprt_1_118_btrl_1` `0xC088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_fpga0ace_mprt_1_118_btrl_2` `0xC090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_fpga0ace_mprt_1_118_btrl_3` `0xC098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_fpga0ace_mprt_1_118_btus_0` `0xC058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_btus_1` `0xC060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_fpga0ace_mprt_1_118_p_0` `0xC000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_fpga0ace_mprt_1_118_p_1` `0xC008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_fpga0ace_mprt_1_118_p_2` `0xC010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_fpga0ace_mprt_1_118_p_3` `0xC018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_fpga0ace_mprt_1_118_rxid` `0xC1B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x1`
`bridge_fpga0ace_mprt_1_118_txid` `0xC078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x1`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ddrreg_sprt_ddrregspace0_0` `0x10400` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E00000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E00000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E00000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E00000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ios_sprt_iospace0a_0` `0x10420` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x2000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x2000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x2000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x2000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ios_sprt_iospace0b_0` `0x10440` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ios_sprt_iospace1a_0` `0x10460` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E40000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E40000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E40000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E40000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ios_sprt_iospace1b_0` `0x10480` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E80000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ios_sprt_iospace1c_0` `0x104A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3F00000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3F00000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3F00000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3F00000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ios_sprt_iospace1d_0` `0x104C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3F80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3F80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3F80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3F80000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ios_sprt_iospace1e_0` `0x104E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FC0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ios_sprt_iospace1f_0` `0x10500` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FE0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FE0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FE0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FE0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ios_sprt_iospace1g_0` `0x10520` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ios_sprt_iospace2a_0` `0x10540` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x80000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x80000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x80000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x80000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ios_sprt_iospace2b_0` `0x10560` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x100000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x100000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x100000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x100000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ios_sprt_iospace2c_0` `0x10580` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x200000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x200000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x200000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x200000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_mem0_sprt_memspace0_0` `0x105A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x0`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_mem0_sprt_memspace1a_0` `0x105C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x4000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x4000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x4000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x4000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_mem0_sprt_memspace1b_0` `0x105E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x8000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x8000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x8000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x8000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_mem0_sprt_memspace1c_0` `0x10600` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x10000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x10000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x10000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x10000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_mem0_sprt_memspace1d_0` `0x10620` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x20000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x20000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x20000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x20000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_mem0_sprt_memspace1e_0` `0x10640` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x40000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x40000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x40000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x40000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ram_sprt_ramspace0_0` `0x10660` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF8000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF8000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF8000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF8000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x1`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ram_sprt_ramspace1_0` `0x10680` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF9000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF9000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF9000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF9000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ram_sprt_ramspace2_0` `0x106A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFA000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFA000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFA000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFA000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ram_sprt_ramspace3_0` `0x106C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFA800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFA800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFA800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFA800`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ram_sprt_ramspace4_0` `0x106E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFB000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFB000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFB000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFB000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_adbase_mem_ram_sprt_ramspace5_0` `0x10700` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFB800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFB800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFB800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFB800`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ddrreg_sprt_ddrregspace0_0` `0x10408` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ios_sprt_iospace0a_0` `0x10428` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FF000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FF000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FF000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FF000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ios_sprt_iospace0b_0` `0x10448` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FF800000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FF800000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FF800000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FF800000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ios_sprt_iospace1a_0` `0x10468` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ios_sprt_iospace1b_0` `0x10488` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFF80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFF80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFF80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFF80000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ios_sprt_iospace1c_0` `0x104A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFF80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFF80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFF80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFF80000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ios_sprt_iospace1d_0` `0x104C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ios_sprt_iospace1e_0` `0x104E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFE0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFE0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFE0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFE0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ios_sprt_iospace1f_0` `0x10508` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFF0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFF0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFF0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFF0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ios_sprt_iospace1g_0` `0x10528` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFF8000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFF8000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFF8000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFF8000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ios_sprt_iospace2a_0` `0x10548` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x380000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x380000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x380000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x380000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ios_sprt_iospace2b_0` `0x10568` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x300000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x300000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x300000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x300000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ios_sprt_iospace2c_0` `0x10588` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x200000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x200000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x200000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x200000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_mem0_sprt_memspace0_0` `0x105A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FE000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FE000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FE000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FE000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_mem0_sprt_memspace1a_0` `0x105C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FC000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FC000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FC000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FC000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_mem0_sprt_memspace1b_0` `0x105E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3F8000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3F8000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3F8000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3F8000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_mem0_sprt_memspace1c_0` `0x10608` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3F0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3F0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3F0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3F0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_mem0_sprt_memspace1d_0` `0x10628` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3E0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3E0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3E0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3E0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_mem0_sprt_memspace1e_0` `0x10648` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3C0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3C0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3C0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3C0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ram_sprt_ramspace0_0` `0x10668` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x1`	`P` `RW 0x1`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ram_sprt_ramspace1_0` `0x10688` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ram_sprt_ramspace2_0` `0x106A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ram_sprt_ramspace3_0` `0x106C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ram_sprt_ramspace4_0` `0x106E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_admask_mem_ram_sprt_ramspace5_0` `0x10708` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_bridge_id` `0x13D08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x4`
`bridge_fpga1acel_mprt_4_118_am_err` `0x13E00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`E40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`E34` `RW 0x0`	`E33` `RW 0x0`	`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`E24` `RW 0x0`	`E23` `RW 0x0`	`E22` `RW 0x0`	`E21` `RW 0x0`	`E20` `RW 0x0`	`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`E8` `RW 0x0`	`E7` `RW 0x0`	`E6` `RW 0x0`	`E5` `RW 0x0`	`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_am_intm` `0x13E40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`M40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`M34` `RW 0x1`	`M33` `RW 0x1`	`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`M24` `RW 0x0`	`M23` `RW 0x0`	`M22` `RW 0x1`	`M21` `RW 0x0`	`M20` `RW 0x0`	`M19` `RW 0x1`	`M18` `RW 0x1`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`M8` `RW 0x0`	`M7` `RW 0x0`	`M6` `RW 0x1`	`M5` `RW 0x0`	`M4` `RW 0x0`	`M3` `RW 0x1`	`M2` `RW 0x1`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_fpga1acel_mprt_4_118_am_sts` `0x13D00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_8` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_8` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_8` `RO 0x0`								`AWO` `RO 0x0`	`ARO` `RO 0x0`	`AWS` `RO 0x0`	`ARS` `RO 0x0`	`WOE` `RO 0x1`	`ROE` `RO 0x1`	`WOF` `RO 0x0`	`ROF` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_0` `0x10130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_1` `0x10138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_10` `0x10180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_11` `0x10188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_12` `0x10190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_13` `0x10198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_14` `0x101A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_15` `0x101A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_2` `0x10140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_3` `0x10148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_4` `0x10150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_5` `0x10158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_6` `0x10160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_7` `0x10168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_8` `0x10170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brs_9` `0x10178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_brus` `0x101B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_btrl_0` `0x10080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_fpga1acel_mprt_4_118_btrl_1` `0x10088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_fpga1acel_mprt_4_118_btrl_2` `0x10090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_fpga1acel_mprt_4_118_btrl_3` `0x10098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_fpga1acel_mprt_4_118_btus_0` `0x10058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_btus_1` `0x10060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_fpga1acel_mprt_4_118_p_0` `0x10000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_fpga1acel_mprt_4_118_p_1` `0x10008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_fpga1acel_mprt_4_118_p_2` `0x10010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_fpga1acel_mprt_4_118_p_3` `0x10018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_fpga1acel_mprt_4_118_rxid` `0x101B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x4`
`bridge_fpga1acel_mprt_4_118_txid` `0x10078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x4`
`bridge_gic_sprt_10_100_as_bridge_id` `0x15D08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xA`
`bridge_gic_sprt_10_100_as_err` `0x15E00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_gic_sprt_10_100_as_intm` `0x15E40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`M19` `RW 0x1`	`M18` `RW 0x0`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`M4` `RW 0x1`	`M3` `RW 0x0`	`M2` `RW 0x0`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_gic_sprt_10_100_as_sts` `0x15D00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_4` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_4` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_4` `RO 0x0`												`ROE` `RO 0x1`	`WOE` `RO 0x1`	`ROF` `RO 0x0`	`WOF` `RO 0x0`
`bridge_gic_sprt_10_100_brs_0` `0x14130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_1` `0x14138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_10` `0x14180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_11` `0x14188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_12` `0x14190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_13` `0x14198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_14` `0x141A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_15` `0x141A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_2` `0x14140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_3` `0x14148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_4` `0x14150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_5` `0x14158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_6` `0x14160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_7` `0x14168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_8` `0x14170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brs_9` `0x14178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_gic_sprt_10_100_brus` `0x141B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_gic_sprt_10_100_btrl_0` `0x14080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_gic_sprt_10_100_btrl_1` `0x14088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_gic_sprt_10_100_btrl_2` `0x14090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_gic_sprt_10_100_btrl_3` `0x14098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_gic_sprt_10_100_btus_0` `0x14058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_gic_sprt_10_100_btus_1` `0x14060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_gic_sprt_10_100_p_0` `0x14000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_gic_sprt_10_100_p_1` `0x14008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_gic_sprt_10_100_p_2` `0x14010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_gic_sprt_10_100_p_3` `0x14018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_gic_sprt_10_100_rxid` `0x141B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xA`
`bridge_gic_sprt_10_100_txid` `0x14078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xA`
`bridge_iocb0_mprt_2_82_SYSCOACK_reg` `0x47F78` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD` `RO 0x0`															`STAT_REG` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ios_sprt_iospace0a_0` `0x44400` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x2000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x2000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x2000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x2000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ios_sprt_iospace0b_0` `0x44420` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ios_sprt_iospace1a_0` `0x44440` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E40000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E40000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E40000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E40000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ios_sprt_iospace1b_0` `0x44460` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E80000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ios_sprt_iospace1c_0` `0x44480` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3F00000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3F00000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3F00000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3F00000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ios_sprt_iospace1d_0` `0x444A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3F80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3F80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3F80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3F80000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ios_sprt_iospace1e_0` `0x444C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FC0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ios_sprt_iospace1f_0` `0x444E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FE0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FE0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FE0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FE0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ios_sprt_iospace1g_0` `0x44500` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_mem0_sprt_memspace0_0` `0x44520` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x0`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_mem0_sprt_memspace1a_0` `0x44540` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x4000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x4000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x4000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x4000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_mem0_sprt_memspace1b_0` `0x44560` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x8000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x8000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x8000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x8000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_mem0_sprt_memspace1c_0` `0x44580` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x10000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x10000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x10000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x10000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_mem0_sprt_memspace1d_0` `0x445A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x20000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x20000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x20000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x20000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_mem0_sprt_memspace1e_0` `0x445C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x40000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x40000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x40000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x40000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ram_sprt_ramspace0_0` `0x445E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF8000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF8000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF8000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF8000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ram_sprt_ramspace1_0` `0x44600` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF9000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF9000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF9000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF9000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ram_sprt_ramspace2_0` `0x44620` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFA000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFA000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFA000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFA000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ram_sprt_ramspace3_0` `0x44640` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFA800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFA800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFA800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFA800`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ram_sprt_ramspace4_0` `0x44660` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFB000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFB000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFB000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFB000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_adbase_mem_ram_sprt_ramspace5_0` `0x44680` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFB800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFB800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFB800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFB800`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ios_sprt_iospace0a_0` `0x44408` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFF000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFF000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFF000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFF000000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ios_sprt_iospace0b_0` `0x44428` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFF800000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFF800000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFF800000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFF800000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ios_sprt_iospace1a_0` `0x44448` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFC0000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ios_sprt_iospace1b_0` `0x44468` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFF80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFF80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFF80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFF80000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ios_sprt_iospace1c_0` `0x44488` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFF80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFF80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFF80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFF80000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ios_sprt_iospace1d_0` `0x444A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFC0000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ios_sprt_iospace1e_0` `0x444C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFE0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFE0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFE0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFE0000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ios_sprt_iospace1f_0` `0x444E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF0000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ios_sprt_iospace1g_0` `0x44508` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF8000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF8000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF8000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF8000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_mem0_sprt_memspace0_0` `0x44528` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFE000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFE000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFE000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFE000000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_mem0_sprt_memspace1a_0` `0x44548` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFC000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFC000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFC000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFC000000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_mem0_sprt_memspace1b_0` `0x44568` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FF8000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FF8000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FF8000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FF8000000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_mem0_sprt_memspace1c_0` `0x44588` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FF0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FF0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FF0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FF0000000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_mem0_sprt_memspace1d_0` `0x445A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FE0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FE0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FE0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FE0000000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_mem0_sprt_memspace1e_0` `0x445C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FC0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FC0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FC0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FC0000000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ram_sprt_ramspace0_0` `0x445E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ram_sprt_ramspace1_0` `0x44608` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF000`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ram_sprt_ramspace2_0` `0x44628` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ram_sprt_ramspace3_0` `0x44648` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ram_sprt_ramspace4_0` `0x44668` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_admask_mem_ram_sprt_ramspace5_0` `0x44688` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RO 0x0`	`I` `RO 0x0`	`NS` `RO 0x0`	`P` `RO 0x0`
`bridge_iocb0_mprt_2_82_am_bridge_id` `0x47D08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x2`
`bridge_iocb0_mprt_2_82_am_err` `0x47E00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`E40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`E34` `RW 0x0`	`E33` `RW 0x0`	`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`E24` `RW 0x0`	`E23` `RW 0x0`	`E22` `RW 0x0`	`E21` `RW 0x0`	`E20` `RW 0x0`	`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`E8` `RW 0x0`	`E7` `RW 0x0`	`E6` `RW 0x0`	`E5` `RW 0x0`	`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_iocb0_mprt_2_82_am_intm` `0x47E40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`M40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`M34` `RW 0x1`	`M33` `RW 0x1`	`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`M24` `RW 0x0`	`M23` `RW 0x0`	`M22` `RW 0x1`	`M21` `RW 0x0`	`M20` `RW 0x0`	`M19` `RW 0x1`	`M18` `RW 0x0`	`M17` `RW 0x0`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`M8` `RW 0x0`	`M7` `RW 0x0`	`M6` `RW 0x1`	`M5` `RW 0x0`	`M4` `RW 0x0`	`M3` `RW 0x1`	`M2` `RW 0x0`	`M1` `RW 0x0`	`M0` `RW 0x1`
`bridge_iocb0_mprt_2_82_am_sts` `0x47D00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_8` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_8` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_8` `RO 0x0`								`AWO` `RO 0x0`	`ARO` `RO 0x0`	`AWS` `RO 0x0`	`ARS` `RO 0x0`	`WOE` `RO 0x1`	`ROE` `RO 0x1`	`WOF` `RO 0x0`	`ROF` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_0` `0x44130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_1` `0x44138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_10` `0x44180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_11` `0x44188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_12` `0x44190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_13` `0x44198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_14` `0x441A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_15` `0x441A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_2` `0x44140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_3` `0x44148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_4` `0x44150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_5` `0x44158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_6` `0x44160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_7` `0x44168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_8` `0x44170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brs_9` `0x44178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_mprt_2_82_brus` `0x441B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_iocb0_mprt_2_82_btrl_0` `0x44080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_iocb0_mprt_2_82_btrl_1` `0x44088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_iocb0_mprt_2_82_btrl_2` `0x44090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_iocb0_mprt_2_82_btrl_3` `0x44098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_iocb0_mprt_2_82_btus_0` `0x44058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_iocb0_mprt_2_82_btus_1` `0x44060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_iocb0_mprt_2_82_p_0` `0x44000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_iocb0_mprt_2_82_p_1` `0x44008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_iocb0_mprt_2_82_p_2` `0x44010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_iocb0_mprt_2_82_p_3` `0x44018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_iocb0_mprt_2_82_rxid` `0x441B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x2`
`bridge_iocb0_mprt_2_82_txid` `0x44078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x2`
`bridge_iocb0_sprt_11_67_as_bridge_id` `0x49D08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xB`
`bridge_iocb0_sprt_11_67_as_err` `0x49E00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_iocb0_sprt_11_67_as_intm` `0x49E40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`M19` `RW 0x1`	`M18` `RW 0x0`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`M4` `RW 0x1`	`M3` `RW 0x0`	`M2` `RW 0x0`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_iocb0_sprt_11_67_as_sts` `0x49D00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_4` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_4` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_4` `RO 0x0`												`ROE` `RO 0x1`	`WOE` `RO 0x1`	`ROF` `RO 0x0`	`WOF` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_0` `0x48130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_1` `0x48138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_10` `0x48180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_11` `0x48188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_12` `0x48190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_13` `0x48198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_14` `0x481A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_15` `0x481A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_2` `0x48140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_3` `0x48148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_4` `0x48150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_5` `0x48158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_6` `0x48160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_7` `0x48168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_8` `0x48170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brs_9` `0x48178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iocb0_sprt_11_67_brus` `0x481B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_iocb0_sprt_11_67_btrl_0` `0x48080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_iocb0_sprt_11_67_btrl_1` `0x48088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_iocb0_sprt_11_67_btrl_2` `0x48090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_iocb0_sprt_11_67_btrl_3` `0x48098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_iocb0_sprt_11_67_btus_0` `0x48058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_iocb0_sprt_11_67_btus_1` `0x48060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_iocb0_sprt_11_67_p_0` `0x48000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_iocb0_sprt_11_67_p_1` `0x48008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_iocb0_sprt_11_67_p_2` `0x48010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_iocb0_sprt_11_67_p_3` `0x48018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_iocb0_sprt_11_67_rxid` `0x481B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xB`
`bridge_iocb0_sprt_11_67_txid` `0x48078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xB`
`bridge_iom_mprt_5_63_am_adbase_mem_ddrreg_sprt_ddrregspace0_0` `0x18400` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E00000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E00000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E00000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E00000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_gic_sprt_gicspace_0` `0x18420` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFF000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace0a_0` `0x18440` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x2000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x2000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x2000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x2000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace0b_0` `0x18460` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace1a_0` `0x18480` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E40000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E40000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E40000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E40000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace1b_0` `0x184A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E80000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace1c_0` `0x184C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3F00000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3F00000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3F00000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3F00000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace1d_0` `0x184E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3F80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3F80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3F80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3F80000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace1e_0` `0x18500` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FC0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace1f_0` `0x18520` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FE0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FE0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FE0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FE0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_ios_sprt_iospace1g_0` `0x18540` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_mem0_sprt_memspace0_0` `0x18560` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x0`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_mem0_sprt_memspace1a_0` `0x18580` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x4000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x4000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x4000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x4000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_mem0_sprt_memspace1b_0` `0x185A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x8000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x8000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x8000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x8000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_mem0_sprt_memspace1c_0` `0x185C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x10000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x10000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x10000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x10000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_mem0_sprt_memspace1d_0` `0x185E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x20000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x20000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x20000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x20000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_mem0_sprt_memspace1e_0` `0x18600` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x40000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x40000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x40000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x40000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_ram_sprt_ramspace0_0` `0x18620` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF8000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF8000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF8000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF8000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x1`
`bridge_iom_mprt_5_63_am_adbase_mem_ram_sprt_ramspace1_0` `0x18640` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF9000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF9000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF9000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF9000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_ram_sprt_ramspace2_0` `0x18660` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFA000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFA000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFA000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFA000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_ram_sprt_ramspace3_0` `0x18680` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFA800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFA800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFA800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFA800`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_ram_sprt_ramspace4_0` `0x186A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFB000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFB000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFB000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFB000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_ram_sprt_ramspace5_0` `0x186C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFB800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFB800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFB800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFB800`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_rbm_s_regspace_rd_0` `0x186E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3DC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3DC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3DC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3DC0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x1`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_adbase_mem_rbm_s_regspace_wr_0` `0x18700` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3DC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3DC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3DC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3DC0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x1`
`bridge_iom_mprt_5_63_am_admask_mem_ddrreg_sprt_ddrregspace0_0` `0x18408` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_gic_sprt_gicspace_0` `0x18428` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFE00`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFE00`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFE00`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFE00`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_ios_sprt_iospace0a_0` `0x18448` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FF000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FF000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FF000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FF000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_ios_sprt_iospace0b_0` `0x18468` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FF800000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FF800000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FF800000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FF800000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_ios_sprt_iospace1a_0` `0x18488` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_ios_sprt_iospace1b_0` `0x184A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFF80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFF80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFF80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFF80000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_ios_sprt_iospace1c_0` `0x184C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFF80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFF80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFF80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFF80000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_ios_sprt_iospace1d_0` `0x184E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_ios_sprt_iospace1e_0` `0x18508` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFE0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFE0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFE0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFE0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_ios_sprt_iospace1f_0` `0x18528` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFF0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFF0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFF0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFF0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_ios_sprt_iospace1g_0` `0x18548` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFF8000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFF8000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFF8000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFF8000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_mem0_sprt_memspace0_0` `0x18568` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FE000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FE000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FE000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FE000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_mem0_sprt_memspace1a_0` `0x18588` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FC000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FC000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FC000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FC000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_mem0_sprt_memspace1b_0` `0x185A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3F8000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3F8000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3F8000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3F8000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_mem0_sprt_memspace1c_0` `0x185C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3F0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3F0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3F0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3F0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_mem0_sprt_memspace1d_0` `0x185E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3E0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3E0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3E0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3E0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_mem0_sprt_memspace1e_0` `0x18608` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3C0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3C0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3C0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3C0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_ram_sprt_ramspace0_0` `0x18628` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x1`	`P` `RW 0x1`
`bridge_iom_mprt_5_63_am_admask_mem_ram_sprt_ramspace1_0` `0x18648` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_ram_sprt_ramspace2_0` `0x18668` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_ram_sprt_ramspace3_0` `0x18688` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_ram_sprt_ramspace4_0` `0x186A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_ram_sprt_ramspace5_0` `0x186C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_rbm_s_regspace_rd_0` `0x186E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x1`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_iom_mprt_5_63_am_admask_mem_rbm_s_regspace_wr_0` `0x18708` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x1`	`I` `RW 0x0`	`NS` `RW 0x1`	`P` `RW 0x1`
`bridge_iom_mprt_5_63_am_bridge_id` `0x1BD08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x5`
`bridge_iom_mprt_5_63_am_err` `0x1BE00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`E40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`E34` `RW 0x0`	`E33` `RW 0x0`	`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`E24` `RW 0x0`	`E23` `RW 0x0`	`E22` `RW 0x0`	`E21` `RW 0x0`	`E20` `RW 0x0`	`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`E8` `RW 0x0`	`E7` `RW 0x0`	`E6` `RW 0x0`	`E5` `RW 0x0`	`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_iom_mprt_5_63_am_intm` `0x1BE40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`M40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`M34` `RW 0x1`	`M33` `RW 0x1`	`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`M24` `RW 0x0`	`M23` `RW 0x0`	`M22` `RW 0x1`	`M21` `RW 0x0`	`M20` `RW 0x0`	`M19` `RW 0x1`	`M18` `RW 0x1`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`M8` `RW 0x0`	`M7` `RW 0x0`	`M6` `RW 0x1`	`M5` `RW 0x0`	`M4` `RW 0x0`	`M3` `RW 0x1`	`M2` `RW 0x1`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_iom_mprt_5_63_am_sts` `0x1BD00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_8` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_8` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_8` `RO 0x0`								`AWO` `RO 0x0`	`ARO` `RO 0x0`	`AWS` `RO 0x0`	`ARS` `RO 0x0`	`WOE` `RO 0x1`	`ROE` `RO 0x1`	`WOF` `RO 0x0`	`ROF` `RO 0x0`
`bridge_iom_mprt_5_63_brs_0` `0x18130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_1` `0x18138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_10` `0x18180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_11` `0x18188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_12` `0x18190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_13` `0x18198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_14` `0x181A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_15` `0x181A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_2` `0x18140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_3` `0x18148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_4` `0x18150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_5` `0x18158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_6` `0x18160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_7` `0x18168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_8` `0x18170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brs_9` `0x18178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_iom_mprt_5_63_brus` `0x181B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_iom_mprt_5_63_btrl_0` `0x18080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_iom_mprt_5_63_btrl_1` `0x18088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_iom_mprt_5_63_btrl_2` `0x18090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_iom_mprt_5_63_btrl_3` `0x18098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_iom_mprt_5_63_btus_0` `0x18058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_iom_mprt_5_63_btus_1` `0x18060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_iom_mprt_5_63_p_0` `0x18000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_iom_mprt_5_63_p_1` `0x18008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_iom_mprt_5_63_p_2` `0x18010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_iom_mprt_5_63_p_3` `0x18018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_iom_mprt_5_63_rxid` `0x181B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x5`
`bridge_iom_mprt_5_63_txid` `0x18078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x5`
`bridge_ios_sprt_12_63_as_bridge_id` `0x1DD08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xC`
`bridge_ios_sprt_12_63_as_err` `0x1DE00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_ios_sprt_12_63_as_intm` `0x1DE40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`M19` `RW 0x1`	`M18` `RW 0x0`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`M4` `RW 0x1`	`M3` `RW 0x0`	`M2` `RW 0x0`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_ios_sprt_12_63_as_sts` `0x1DD00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_4` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_4` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_4` `RO 0x0`												`ROE` `RO 0x1`	`WOE` `RO 0x1`	`ROF` `RO 0x0`	`WOF` `RO 0x0`
`bridge_ios_sprt_12_63_brs_0` `0x1C130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_1` `0x1C138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_10` `0x1C180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_11` `0x1C188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_12` `0x1C190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_13` `0x1C198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_14` `0x1C1A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_15` `0x1C1A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_2` `0x1C140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_3` `0x1C148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_4` `0x1C150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_5` `0x1C158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_6` `0x1C160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_7` `0x1C168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_8` `0x1C170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brs_9` `0x1C178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ios_sprt_12_63_brus` `0x1C1B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_ios_sprt_12_63_btrl_0` `0x1C080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_ios_sprt_12_63_btrl_1` `0x1C088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_ios_sprt_12_63_btrl_2` `0x1C090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_ios_sprt_12_63_btrl_3` `0x1C098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_ios_sprt_12_63_btus_0` `0x1C058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_ios_sprt_12_63_btus_1` `0x1C060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_ios_sprt_12_63_p_0` `0x1C000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_ios_sprt_12_63_p_1` `0x1C008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_ios_sprt_12_63_p_2` `0x1C010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_ios_sprt_12_63_p_3` `0x1C018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_ios_sprt_12_63_rxid` `0x1C1B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xC`
`bridge_ios_sprt_12_63_txid` `0x1C078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xC`
`bridge_mem0_sprt_13_118_as_bridge_id` `0x21D08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xD`
`bridge_mem0_sprt_13_118_as_err` `0x21E00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_mem0_sprt_13_118_as_intm` `0x21E40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`M19` `RW 0x1`	`M18` `RW 0x0`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`M4` `RW 0x1`	`M3` `RW 0x0`	`M2` `RW 0x0`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_mem0_sprt_13_118_as_sts` `0x21D00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_4` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_4` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_4` `RO 0x0`												`ROE` `RO 0x1`	`WOE` `RO 0x1`	`ROF` `RO 0x0`	`WOF` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_0` `0x20130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_1` `0x20138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_10` `0x20180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_11` `0x20188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_12` `0x20190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_13` `0x20198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_14` `0x201A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_15` `0x201A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_2` `0x20140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_3` `0x20148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_4` `0x20150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_5` `0x20158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_6` `0x20160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_7` `0x20168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_8` `0x20170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brs_9` `0x20178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_mem0_sprt_13_118_brus` `0x201B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_mem0_sprt_13_118_btrl_0` `0x20080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_mem0_sprt_13_118_btrl_1` `0x20088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_mem0_sprt_13_118_btrl_2` `0x20090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_mem0_sprt_13_118_btrl_3` `0x20098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_mem0_sprt_13_118_btus_0` `0x20058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_mem0_sprt_13_118_btus_1` `0x20060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_mem0_sprt_13_118_p_0` `0x20000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_mem0_sprt_13_118_p_1` `0x20008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_mem0_sprt_13_118_p_2` `0x20010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_mem0_sprt_13_118_p_3` `0x20018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_mem0_sprt_13_118_rxid` `0x201B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xD`
`bridge_mem0_sprt_13_118_txid` `0x20078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xD`
`bridge_ram_sprt_14_80_as_bridge_id` `0x25D08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xE`
`bridge_ram_sprt_14_80_as_err` `0x25E00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_ram_sprt_14_80_as_intm` `0x25E40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`M19` `RW 0x1`	`M18` `RW 0x0`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`M4` `RW 0x1`	`M3` `RW 0x0`	`M2` `RW 0x0`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_ram_sprt_14_80_as_sts` `0x25D00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_4` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_4` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_4` `RO 0x0`												`ROE` `RO 0x1`	`WOE` `RO 0x1`	`ROF` `RO 0x0`	`WOF` `RO 0x0`
`bridge_ram_sprt_14_80_brs_0` `0x24130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_1` `0x24138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_10` `0x24180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_11` `0x24188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_12` `0x24190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_13` `0x24198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_14` `0x241A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_15` `0x241A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_2` `0x24140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_3` `0x24148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_4` `0x24150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_5` `0x24158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_6` `0x24160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_7` `0x24168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_8` `0x24170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brs_9` `0x24178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_ram_sprt_14_80_brus` `0x241B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_ram_sprt_14_80_btrl_0` `0x24080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_ram_sprt_14_80_btrl_1` `0x24088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_ram_sprt_14_80_btrl_2` `0x24090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_ram_sprt_14_80_btrl_3` `0x24098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_ram_sprt_14_80_btus_0` `0x24058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_ram_sprt_14_80_btus_1` `0x24060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_ram_sprt_14_80_p_0` `0x24000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_ram_sprt_14_80_p_1` `0x24008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_ram_sprt_14_80_p_2` `0x24010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_ram_sprt_14_80_p_3` `0x24018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_ram_sprt_14_80_rxid` `0x241B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xE`
`bridge_ram_sprt_14_80_txid` `0x24078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xE`
`bridge_rbm_s_15_66_as_bridge_id` `0x29D08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xF`
`bridge_rbm_s_15_66_as_err` `0x29E00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_rbm_s_15_66_as_intm` `0x29E40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_33` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_33` `RO 0x0`															`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_20` `RO 0x0`												`M19` `RW 0x1`	`M18` `RW 0x0`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_5` `RO 0x0`											`M4` `RW 0x1`	`M3` `RW 0x0`	`M2` `RW 0x0`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_rbm_s_15_66_as_sts` `0x29D00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_4` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_4` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_4` `RO 0x0`												`ROE` `RO 0x1`	`WOE` `RO 0x1`	`ROF` `RO 0x0`	`WOF` `RO 0x0`
`bridge_rbm_s_15_66_brs_0` `0x28130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_1` `0x28138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_10` `0x28180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_11` `0x28188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_12` `0x28190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_13` `0x28198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_14` `0x281A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_15` `0x281A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_2` `0x28140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_3` `0x28148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_4` `0x28150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_5` `0x28158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_6` `0x28160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_7` `0x28168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_8` `0x28170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brs_9` `0x28178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_s_15_66_brus` `0x281B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_rbm_s_15_66_btrl_0` `0x28080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_rbm_s_15_66_btrl_1` `0x28088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_rbm_s_15_66_btrl_2` `0x28090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_rbm_s_15_66_btrl_3` `0x28098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_rbm_s_15_66_btus_0` `0x28058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_rbm_s_15_66_btus_1` `0x28060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_rbm_s_15_66_p_0` `0x28000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_rbm_s_15_66_p_1` `0x28008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_rbm_s_15_66_p_2` `0x28010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_rbm_s_15_66_p_3` `0x28018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_rbm_s_15_66_rxid` `0x281B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xF`
`bridge_rbm_s_15_66_txid` `0x28078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0xF`
`bridge_tcu_mprt_3_70_SYSCOACK_reg` `0x2FF78` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD` `RO 0x0`															`STAT_REG` `RO 0x1`
`bridge_tcu_mprt_3_70_SYSCOREQ_reg` `0x2FF70` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD` `RO 0x0`															`REQ_REG` `RW 0x1`
`bridge_tcu_mprt_3_70_am_adbase_mem_ios_sprt_iospace0a_0` `0x2C400` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x2000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x2000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x2000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x2000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_ios_sprt_iospace0b_0` `0x2C420` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3000000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_ios_sprt_iospace1a_0` `0x2C440` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E40000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E40000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E40000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E40000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_ios_sprt_iospace1b_0` `0x2C460` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3E80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3E80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3E80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3E80000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_ios_sprt_iospace1c_0` `0x2C480` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3F00000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3F00000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3F00000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3F00000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_ios_sprt_iospace1d_0` `0x2C4A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3F80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3F80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3F80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3F80000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_ios_sprt_iospace1e_0` `0x2C4C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FC0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_ios_sprt_iospace1f_0` `0x2C4E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FE0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FE0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FE0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FE0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_ios_sprt_iospace1g_0` `0x2C500` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF0000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_mem0_sprt_memspace0_0` `0x2C520` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x0`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_mem0_sprt_memspace1a_0` `0x2C540` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x4000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x4000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x4000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x4000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_mem0_sprt_memspace1b_0` `0x2C560` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x8000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x8000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x8000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x8000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_mem0_sprt_memspace1c_0` `0x2C580` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x10000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x10000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x10000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x10000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_mem0_sprt_memspace1d_0` `0x2C5A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x20000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x20000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x20000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x20000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_mem0_sprt_memspace1e_0` `0x2C5C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x40000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x40000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x40000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x40000000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_ram_sprt_ramspace0_0` `0x2C5E0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF8000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF8000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF8000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF8000`										`LLC` `RO 0x0`	`DI` `RW 0x0`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x1`
`bridge_tcu_mprt_3_70_am_adbase_mem_ram_sprt_ramspace1_0` `0x2C600` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FF9000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FF9000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FF9000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FF9000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_ram_sprt_ramspace2_0` `0x2C620` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFA000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFA000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFA000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFA000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_ram_sprt_ramspace3_0` `0x2C640` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFA800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFA800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFA800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFA800`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_ram_sprt_ramspace4_0` `0x2C660` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFB000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFB000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFB000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFB000`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_adbase_mem_ram_sprt_ramspace5_0` `0x2C680` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`BASE_ADDRESS` `RW 0x3FFB800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`BASE_ADDRESS` `RW 0x3FFB800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`BASE_ADDRESS` `RW 0x3FFB800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`BASE_ADDRESS` `RW 0x3FFB800`										`LLC` `RO 0x0`	`DI` `RW 0x1`	`R_Wn` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_ios_sprt_iospace0a_0` `0x2C408` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFF000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFF000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFF000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFF000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_ios_sprt_iospace0b_0` `0x2C428` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFF800000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFF800000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFF800000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFF800000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_ios_sprt_iospace1a_0` `0x2C448` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_ios_sprt_iospace1b_0` `0x2C468` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFF80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFF80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFF80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFF80000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_ios_sprt_iospace1c_0` `0x2C488` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFF80000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFF80000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFF80000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFF80000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_ios_sprt_iospace1d_0` `0x2C4A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFC0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFC0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFC0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFC0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_ios_sprt_iospace1e_0` `0x2C4C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFE0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFE0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFE0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFE0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_ios_sprt_iospace1f_0` `0x2C4E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF0000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF0000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF0000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF0000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_ios_sprt_iospace1g_0` `0x2C508` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFF8000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFF8000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFF8000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFF8000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_mem0_sprt_memspace0_0` `0x2C528` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFE000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFE000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFE000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFE000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_mem0_sprt_memspace1a_0` `0x2C548` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFC000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFC000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFC000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFC000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_mem0_sprt_memspace1b_0` `0x2C568` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FF8000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FF8000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FF8000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FF8000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_mem0_sprt_memspace1c_0` `0x2C588` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FF0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FF0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FF0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FF0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_mem0_sprt_memspace1d_0` `0x2C5A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FE0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FE0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FE0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FE0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_mem0_sprt_memspace1e_0` `0x2C5C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FC0000000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FC0000000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FC0000000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FC0000000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_ram_sprt_ramspace0_0` `0x2C5E8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x1`	`P` `RW 0x1`
`bridge_tcu_mprt_3_70_am_admask_mem_ram_sprt_ramspace1_0` `0x2C608` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF000`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF000`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF000`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF000`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_ram_sprt_ramspace2_0` `0x2C628` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_ram_sprt_ramspace3_0` `0x2C648` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_ram_sprt_ramspace4_0` `0x2C668` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_admask_mem_ram_sprt_ramspace5_0` `0x2C688` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`MASK` `RW 0x3FFFFFF800`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`MASK` `RW 0x3FFFFFF800`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`MASK` `RW 0x3FFFFFF800`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`MASK` `RW 0x3FFFFFF800`										`RSV` `RW 0x0`		`VALID` `RW 0x0`	`I` `RW 0x0`	`NS` `RW 0x0`	`P` `RW 0x0`
`bridge_tcu_mprt_3_70_am_bridge_id` `0x2FD08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x3`
`bridge_tcu_mprt_3_70_am_err` `0x2FE00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`E40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`E34` `RW 0x0`	`E33` `RW 0x0`	`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`E24` `RW 0x0`	`E23` `RW 0x0`	`E22` `RW 0x0`	`E21` `RW 0x0`	`E20` `RW 0x0`	`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`E8` `RW 0x0`	`E7` `RW 0x0`	`E6` `RW 0x0`	`E5` `RW 0x0`	`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_tcu_mprt_3_70_am_intm` `0x2FE40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`M40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`M34` `RW 0x1`	`M33` `RW 0x1`	`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`M24` `RW 0x0`	`M23` `RW 0x0`	`M22` `RW 0x1`	`M21` `RW 0x0`	`M20` `RW 0x0`	`M19` `RW 0x1`	`M18` `RW 0x1`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`M8` `RW 0x0`	`M7` `RW 0x0`	`M6` `RW 0x1`	`M5` `RW 0x0`	`M4` `RW 0x0`	`M3` `RW 0x1`	`M2` `RW 0x1`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_tcu_mprt_3_70_am_sts` `0x2FD00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_8` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_8` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_8` `RO 0x0`								`AWO` `RO 0x0`	`ARO` `RO 0x0`	`AWS` `RO 0x0`	`ARS` `RO 0x0`	`WOE` `RO 0x1`	`ROE` `RO 0x1`	`WOF` `RO 0x0`	`ROF` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_0` `0x2C130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_1` `0x2C138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_10` `0x2C180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_11` `0x2C188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_12` `0x2C190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_13` `0x2C198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_14` `0x2C1A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_15` `0x2C1A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_2` `0x2C140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_3` `0x2C148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_4` `0x2C150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_5` `0x2C158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_6` `0x2C160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_7` `0x2C168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_8` `0x2C170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brs_9` `0x2C178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_tcu_mprt_3_70_brus` `0x2C1B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_tcu_mprt_3_70_btrl_0` `0x2C080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_tcu_mprt_3_70_btrl_1` `0x2C088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_tcu_mprt_3_70_btrl_2` `0x2C090` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_tcu_mprt_3_70_btrl_3` `0x2C098` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x1`	`CNT` `RW 0x4`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0xFF`
`bridge_tcu_mprt_3_70_btus_0` `0x2C058` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_tcu_mprt_3_70_btus_1` `0x2C060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_tcu_mprt_3_70_p_0` `0x2C000` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_3` `RW 0x3`								`WT_QOS_2` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_1` `RW 0x3`								`WT_QOS_0` `RW 0x3`
`bridge_tcu_mprt_3_70_p_1` `0x2C008` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_7` `RW 0x3`								`WT_QOS_6` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_5` `RW 0x3`								`WT_QOS_4` `RW 0x3`
`bridge_tcu_mprt_3_70_p_2` `0x2C010` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_11` `RW 0x3`								`WT_QOS_10` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_9` `RW 0x3`								`WT_QOS_8` `RW 0x3`
`bridge_tcu_mprt_3_70_p_3` `0x2C018` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`WT_QOS_15` `RW 0x3`								`WT_QOS_14` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT_QOS_13` `RW 0x3`								`WT_QOS_12` `RW 0x3`
`bridge_tcu_mprt_3_70_rxid` `0x2C1B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x3`
`bridge_tcu_mprt_3_70_txid` `0x2C078` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x3`
`bridge_rbm_m_16_66_am_bridge_id` `0x3D08` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_16` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_16` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x10`
`bridge_rbm_m_16_66_am_err` `0x3E00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`E40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`E34` `RW 0x0`	`E33` `RW 0x0`	`E32` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`E24` `RW 0x0`	`E23` `RW 0x0`	`E22` `RW 0x0`	`E21` `RW 0x0`	`E20` `RW 0x0`	`E19` `RW 0x0`	`E18` `RW 0x0`	`E17` `RW 0x0`	`E16` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`E8` `RW 0x0`	`E7` `RW 0x0`	`E6` `RW 0x0`	`E5` `RW 0x0`	`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`bridge_rbm_m_16_66_am_intm` `0x3E40` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_41` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_41` `RO 0x0`							`M40` `RW 0x0`	`UNSD_39_35` `RO 0x0`					`M34` `RW 0x1`	`M33` `RW 0x1`	`M32` `RW 0x1`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_25` `RO 0x0`							`M24` `RW 0x0`	`M23` `RW 0x0`	`M22` `RW 0x1`	`M21` `RW 0x0`	`M20` `RW 0x0`	`M19` `RW 0x1`	`M18` `RW 0x1`	`M17` `RW 0x1`	`M16` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_9` `RO 0x0`							`M8` `RW 0x0`	`M7` `RW 0x0`	`M6` `RW 0x1`	`M5` `RW 0x0`	`M4` `RW 0x0`	`M3` `RW 0x1`	`M2` `RW 0x1`	`M1` `RW 0x1`	`M0` `RW 0x1`
`bridge_rbm_m_16_66_am_nocver_id` `0x3D10` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_32` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_32` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_VERSION_ID` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_VERSION_ID` `RO 0x0`
`bridge_rbm_m_16_66_am_sts` `0x3D00` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_8` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_8` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_8` `RO 0x0`								`AWO` `RO 0x0`	`ARO` `RO 0x0`	`AWS` `RO 0x0`	`ARS` `RO 0x0`	`WOE` `RO 0x1`	`ROE` `RO 0x1`	`WOF` `RO 0x0`	`ROF` `RO 0x0`
`bridge_rbm_m_16_66_brs_0` `0x130` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_1` `0x138` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_10` `0x180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_11` `0x188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_12` `0x190` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_13` `0x198` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_14` `0x1A0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_15` `0x1A8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_2` `0x140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_3` `0x148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_4` `0x150` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_5` `0x158` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_6` `0x160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_7` `0x168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_8` `0x170` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brs_9` `0x178` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_30` `RO 0x0`		`F_3` `RO 0x0`	`B_3` `RO 0x0`	`S_3` `RO 0x0`	`V_3` `RO 0x0`	`OUTI_3` `RO 0x0`		`UNSD_23_22` `RO 0x0`		`F_2` `RO 0x0`	`B_2` `RO 0x0`	`S_2` `RO 0x0`	`V_2` `RO 0x0`	`OUTI_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_14` `RO 0x0`		`F_1` `RO 0x0`	`B_1` `RO 0x0`	`S_1` `RO 0x0`	`V_1` `RO 0x0`	`OUTI_1` `RO 0x0`		`UNSD_7_6` `RO 0x0`		`F_0` `RO 0x0`	`B_0` `RO 0x0`	`S_0` `RO 0x0`	`V_0` `RO 0x0`	`OUTI_0` `RO 0x0`
`bridge_rbm_m_16_66_brus` `0x1B0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_31_4` `RO 0x0`												`VALID_IF_D` `RO 0x0`	`VALID_IF_C` `RO 0x0`	`VALID_IF_B` `RO 0x0`	`VALID_IF_A` `RO 0x0`
`bridge_rbm_m_16_66_btrl_0` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_rbm_m_16_66_btrl_1` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_rbm_m_16_66_btrl_2` `0x90` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_rbm_m_16_66_btrl_3` `0x98` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_21` `RO 0x0`											`EN` `RW 0x0`	`CNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`WT` `RW 0x0`
`bridge_rbm_m_16_66_btus_0` `0x58` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_7_INTF_D_STS` `RO 0x0`	`NOC_7_INTF_C_STS` `RO 0x0`	`NOC_7_INTF_B_STS` `RO 0x0`	`NOC_7_INTF_A_STS` `RO 0x0`	`NOC_6_INTF_D_STS` `RO 0x0`	`NOC_6_INTF_C_STS` `RO 0x0`	`NOC_6_INTF_B_STS` `RO 0x0`	`NOC_6_INTF_A_STS` `RO 0x0`	`NOC_5_INTF_D_STS` `RO 0x0`	`NOC_5_INTF_C_STS` `RO 0x0`	`NOC_5_INTF_B_STS` `RO 0x0`	`NOC_5_INTF_A_STS` `RO 0x0`	`NOC_4_INTF_D_STS` `RO 0x0`	`NOC_4_INTF_C_STS` `RO 0x0`	`NOC_4_INTF_B_STS` `RO 0x0`	`NOC_4_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_3_INTF_D_STS` `RO 0x0`	`NOC_3_INTF_C_STS` `RO 0x0`	`NOC_3_INTF_B_STS` `RO 0x0`	`NOC_3_INTF_A_STS` `RO 0x0`	`NOC_2_INTF_D_STS` `RO 0x0`	`NOC_2_INTF_C_STS` `RO 0x0`	`NOC_2_INTF_B_STS` `RO 0x0`	`NOC_2_INTF_A_STS` `RO 0x0`	`NOC_1_INTF_D_STS` `RO 0x0`	`NOC_1_INTF_C_STS` `RO 0x0`	`NOC_1_INTF_B_STS` `RO 0x0`	`NOC_1_INTF_A_STS` `RO 0x0`	`NOC_0_INTF_D_STS` `RO 0x0`	`NOC_0_INTF_C_STS` `RO 0x0`	`NOC_0_INTF_B_STS` `RO 0x0`	`NOC_0_INTF_A_STS` `RO 0x0`
`bridge_rbm_m_16_66_btus_1` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`NOC_15_INTF_D_STS` `RO 0x0`	`NOC_15_INTF_C_STS` `RO 0x0`	`NOC_15_INTF_B_STS` `RO 0x0`	`NOC_15_INTF_A_STS` `RO 0x0`	`NOC_14_INTF_D_STS` `RO 0x0`	`NOC_14_INTF_C_STS` `RO 0x0`	`NOC_14_INTF_B_STS` `RO 0x0`	`NOC_14_INTF_A_STS` `RO 0x0`	`NOC_13_INTF_D_STS` `RO 0x0`	`NOC_13_INTF_C_STS` `RO 0x0`	`NOC_13_INTF_B_STS` `RO 0x0`	`NOC_13_INTF_A_STS` `RO 0x0`	`NOC_12_INTF_D_STS` `RO 0x0`	`NOC_12_INTF_C_STS` `RO 0x0`	`NOC_12_INTF_B_STS` `RO 0x0`	`NOC_12_INTF_A_STS` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`NOC_11_INTF_D_STS` `RO 0x0`	`NOC_11_INTF_C_STS` `RO 0x0`	`NOC_11_INTF_B_STS` `RO 0x0`	`NOC_11_INTF_A_STS` `RO 0x0`	`NOC_10_INTF_D_STS` `RO 0x0`	`NOC_10_INTF_C_STS` `RO 0x0`	`NOC_10_INTF_B_STS` `RO 0x0`	`NOC_10_INTF_A_STS` `RO 0x0`	`NOC_9_INTF_D_STS` `RO 0x0`	`NOC_9_INTF_C_STS` `RO 0x0`	`NOC_9_INTF_B_STS` `RO 0x0`	`NOC_9_INTF_A_STS` `RO 0x0`	`NOC_8_INTF_D_STS` `RO 0x0`	`NOC_8_INTF_C_STS` `RO 0x0`	`NOC_8_INTF_B_STS` `RO 0x0`	`NOC_8_INTF_A_STS` `RO 0x0`
`bridge_rbm_m_16_66_rxid` `0x1B8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x10`
`bridge_rbm_m_16_66_txid` `0x78` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_31_16` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZEROES` `RO 0x0`								`ID` `RO 0x10`
`agent_ccc0_ccc_active_vector_0` `0x30020` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`ACTIVE_AGENT_VECTOR` `RO 0x7`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`ACTIVE_AGENT_VECTOR` `RO 0x7`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ACTIVE_AGENT_VECTOR` `RO 0x7`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ACTIVE_AGENT_VECTOR` `RO 0x7`
`agent_ccc0_ccc_agent_disable_status` `0x30038` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_1` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_1` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_1` `RO 0x0`															`stat` `RO 0x1`
`agent_ccc0_ccc_crt_status_0` `0x30140` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`CRT_STATUS_63_0` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`CRT_STATUS_63_0` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CRT_STATUS_63_0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CRT_STATUS_63_0` `RO 0x0`
`agent_ccc0_ccc_crt_status_1` `0x30148` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`CRT_STATUS_127_64` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`CRT_STATUS_127_64` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CRT_STATUS_127_64` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CRT_STATUS_127_64` `RO 0x0`
`agent_ccc0_ccc_crt_status_2` `0x30150` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`CRT_STATUS_191_128` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`CRT_STATUS_191_128` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CRT_STATUS_191_128` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CRT_STATUS_191_128` `RO 0x0`
`agent_ccc0_ccc_crt_status_3` `0x30158` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`CRT_STATUS_255_192` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`CRT_STATUS_255_192` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CRT_STATUS_255_192` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CRT_STATUS_255_192` `RO 0x0`
`agent_ccc0_ccc_crt_status_4` `0x30160` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`CRT_STATUS_319_256` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`CRT_STATUS_319_256` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CRT_STATUS_319_256` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CRT_STATUS_319_256` `RO 0x0`
`agent_ccc0_ccc_crt_status_5` `0x30168` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`CRT_STATUS_383_320` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`CRT_STATUS_383_320` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CRT_STATUS_383_320` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CRT_STATUS_383_320` `RO 0x0`
`agent_ccc0_ccc_crt_status_6` `0x30170` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`CRT_STATUS_447_384` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`CRT_STATUS_447_384` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CRT_STATUS_447_384` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CRT_STATUS_447_384` `RO 0x0`
`agent_ccc0_ccc_crt_status_7` `0x30178` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`CRT_STATUS_511_448` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`CRT_STATUS_511_448` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CRT_STATUS_511_448` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CRT_STATUS_511_448` `RO 0x0`
`agent_ccc0_ccc_directory_inv` `0x30080` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`ZERO` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`ZERO` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ZERO` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ZERO` `RW 0x0`															`VLD` `RW 0x0`
`agent_ccc0_ccc_ecc_disable` `0x30028` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_1` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_1` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_1` `RO 0x0`															`DIS` `RW 0x0`
`agent_ccc0_ccc_ecc_info` `0x30180` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_44` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_44` `RO 0x0`				`DIR_INDEX` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ECC_COUNT` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_15_3` `RO 0x0`													`WAY` `RW 0x0`	`DB` `RW 0x0`	`SB` `RW 0x0`
`agent_ccc0_ccc_event_counter_mask` `0x30100` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_14` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_14` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_14` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_14` `RO 0x0`		`E13` `RW 0x0`	`E12` `RW 0x0`	`E11` `RW 0x0`	`E10` `RW 0x0`	`E9` `RW 0x0`	`E8` `RW 0x0`	`E7` `RW 0x0`	`E6` `RW 0x0`	`E5` `RW 0x0`	`E4` `RW 0x0`	`E3` `RW 0x0`	`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`agent_ccc0_ccc_event_counter_value` `0x30108` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`VALUE` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`VALUE` `RW 0x0`
`agent_ccc0_ccc_hash_bypass` `0x30030` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_1` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_1` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_1` `RO 0x0`															`DIS` `RW 0x0`
`agent_ccc0_ccc_indirect_access_trig` `0x30088` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD` `RO 0x0`	`INDEX` `RW 0x0`												`WAY` `RW 0x0`	`CMD` `RW 0x0`
`agent_ccc0_ccc_indirect_ram_cont_0` `0x30090` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`RAM_CONTENTS_63_0` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`RAM_CONTENTS_63_0` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RAM_CONTENTS_63_0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RAM_CONTENTS_63_0` `RW 0x0`
`agent_ccc0_ccc_indirect_ram_cont_1` `0x30098` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`RAM_CONTENTS_127_64` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`RAM_CONTENTS_127_64` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RAM_CONTENTS_127_64` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RAM_CONTENTS_127_64` `RW 0x0`
`agent_ccc0_ccc_indirect_ram_cont_2` `0x300A0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`RAM_CONTENTS_132_128` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`RAM_CONTENTS_132_128` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RAM_CONTENTS_132_128` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RAM_CONTENTS_132_128` `RW 0x0`
`agent_ccc0_ccc_indirect_ram_cont_3` `0x300A8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`RAM_CONTENTS_255_192` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`RAM_CONTENTS_255_192` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RAM_CONTENTS_255_192` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RAM_CONTENTS_255_192` `RW 0x0`
`agent_ccc0_ccc_indirect_ram_cont_4` `0x300B0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`RAM_CONTENTS_319_256` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`RAM_CONTENTS_319_256` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RAM_CONTENTS_319_256` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RAM_CONTENTS_319_256` `RW 0x0`
`agent_ccc0_ccc_indirect_ram_cont_5` `0x300B8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`RAM_CONTENTS_383_320` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`RAM_CONTENTS_383_320` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RAM_CONTENTS_383_320` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RAM_CONTENTS_383_320` `RW 0x0`
`agent_ccc0_ccc_indirect_ram_cont_6` `0x300C0` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`RAM_CONTENTS_447_384` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`RAM_CONTENTS_447_384` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RAM_CONTENTS_447_384` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RAM_CONTENTS_447_384` `RW 0x0`
`agent_ccc0_ccc_indirect_ram_cont_7` `0x300C8` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`RAM_CONTENTS_511_448` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`RAM_CONTENTS_511_448` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RAM_CONTENTS_511_448` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RAM_CONTENTS_511_448` `RW 0x0`
`agent_ccc0_ccc_interrupt_err` `0x30198` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_3` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_3` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_3` `RO 0x0`													`E2` `RW 0x0`	`E1` `RW 0x0`	`E0` `RW 0x0`
`agent_ccc0_ccc_interrupt_mask` `0x30190` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_3` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_3` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_3` `RO 0x0`													`M2` `RW 0x1`	`M1` `RW 0x1`	`M0` `RW 0x0`
`agent_ccc0_ccc_llc_control` `0x30040` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_2` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_2` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_2` `RO 0x0`														`CM` `RW 0x0`	`WE` `RW 0x0`
`agent_ccc0_ccc_spec_fetch_0` `0x30000` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`SPEC_FETCH_VECTOR` `RW 0x3`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`SPEC_FETCH_VECTOR` `RW 0x3`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SPEC_FETCH_VECTOR` `RW 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SPEC_FETCH_VECTOR` `RW 0x3`
`agent_ccc0_ccc_spec_fetch_1` `0x30008` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`SPEC_FETCH_VECTOR` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`SPEC_FETCH_VECTOR` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SPEC_FETCH_VECTOR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SPEC_FETCH_VECTOR` `RW 0x0`
`agent_ccc0_ccc_spec_fetch_2` `0x30010` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`SPEC_FETCH_VECTOR` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`SPEC_FETCH_VECTOR` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SPEC_FETCH_VECTOR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SPEC_FETCH_VECTOR` `RW 0x0`
`agent_ccc0_ccc_spec_fetch_3` `0x30018` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`SPEC_FETCH_VECTOR` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`SPEC_FETCH_VECTOR` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`SPEC_FETCH_VECTOR` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SPEC_FETCH_VECTOR` `RW 0x0`
`agent_dvm0_dvm_active_vector_0` `0x34000` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`ACTIVE_VECTOR` `RO 0xB`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`ACTIVE_VECTOR` `RO 0xB`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ACTIVE_VECTOR` `RO 0xB`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ACTIVE_VECTOR` `RO 0xB`
`agent_dvm0_dvm_agent_disable_status` `0x34048` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_1` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_1` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_1` `RO 0x0`															`stat` `RO 0x1`
`agent_dvm0_dvm_fault_log_0` `0x34020` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`FAULT_LOG` `RW 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`FAULT_LOG` `RW 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`FAULT_LOG` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FAULT_LOG` `RW 0x0`
`agent_dvm0_dvm_sts` `0x34040` 64-bit	63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
	`UNSD_63_13` `RO 0x0`
	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
	`UNSD_63_13` `RO 0x0`
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UNSD_63_13` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UNSD_63_13` `RO 0x0`			`A` `RO 0x0`	`O` `RO 0x0`	`C` `RO 0x0`	`S` `RO 0x0`	`D7` `RO 0x0`	`D6` `RO 0x0`	`D5` `RO 0x0`	`D4` `RO 0x0`	`D3` `RO 0x0`	`D2` `RO 0x0`	`D1` `RO 0x0`	`D0` `RO 0x0`	`F` `RO 0x0`