agent_ccc0_ccc_crt_status_3

         This register tracks the current state of the Coherency Request Trackers. These are the state-machines that track coherent request from the time they are started to the time they are completed. This can be used to determine if there are requests that have made it to the CCC but are not done being processed.
A bit value of 1 indicates a request is still in flight. There are 32 CRTs in a CCC. The reset value for this register is 0, and that is the value under idle conditions where no request are outstanding.

Module Instance	Base Address	Register Address
`i_ccu_noc_registers`	`0xF7000000`	`0xF7030158`

Size: 64

Offset: 0x30158

Access: RO

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`CRT_STATUS_255_192` `RO 0x0`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`CRT_STATUS_255_192` `RO 0x0`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`CRT_STATUS_255_192` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`CRT_STATUS_255_192` `RO 0x0`

agent_ccc0_ccc_crt_status_3 Fields

Bit	Name	Description	Access	Reset
63:0	`CRT_STATUS_255_192`		`RO`	`0x0`